Lines Matching +full:j721e +full:- +full:system +full:- +full:controller
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j7200-som-p0.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include <dt-bindings/mux/ti-serdes.h>
12 #include <dt-bindings/phy/phy.h>
16 stdout-path = "serial2:115200n8";
20 evm_12v0: fixedregulator-evm12v0 {
22 compatible = "regulator-fixed";
23 regulator-name = "evm_12v0";
24 regulator-min-microvolt = <12000000>;
25 regulator-max-microvolt = <12000000>;
26 regulator-always-on;
27 regulator-boot-on;
30 vsys_3v3: fixedregulator-vsys3v3 {
32 compatible = "regulator-fixed";
33 regulator-name = "vsys_3v3";
34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <3300000>;
36 vin-supply = <&evm_12v0>;
37 regulator-always-on;
38 regulator-boot-on;
41 vsys_5v0: fixedregulator-vsys5v0 {
43 compatible = "regulator-fixed";
44 regulator-name = "vsys_5v0";
45 regulator-min-microvolt = <5000000>;
46 regulator-max-microvolt = <5000000>;
47 vin-supply = <&evm_12v0>;
48 regulator-always-on;
49 regulator-boot-on;
52 vdd_mmc1: fixedregulator-sd {
54 compatible = "regulator-fixed";
55 regulator-name = "vdd_mmc1";
56 regulator-min-microvolt = <3300000>;
57 regulator-max-microvolt = <3300000>;
58 regulator-boot-on;
59 enable-active-high;
60 vin-supply = <&vsys_3v3>;
64 vdd_sd_dv: gpio-regulator-TLV71033 {
66 compatible = "regulator-gpio";
67 regulator-name = "tlv71033";
68 pinctrl-names = "default";
69 pinctrl-0 = <&vdd_sd_dv_pins_default>;
70 regulator-min-microvolt = <1800000>;
71 regulator-max-microvolt = <3300000>;
72 regulator-boot-on;
73 vin-supply = <&vsys_5v0>;
81 mcu_cpsw_pins_default: mcu-cpsw-pins-default {
82 pinctrl-single,pins = <
98 mcu_mdio_pins_default: mcu-mdio1-pins-default {
99 pinctrl-single,pins = <
107 main_i2c0_pins_default: main-i2c0-pins-default {
108 pinctrl-single,pins = <
114 main_i2c1_pins_default: main-i2c1-pins-default {
115 pinctrl-single,pins = <
121 main_mmc1_pins_default: main-mmc1-pins-default {
122 pinctrl-single,pins = <
134 main_usbss0_pins_default: main-usbss0-pins-default {
135 pinctrl-single,pins = <
140 vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
141 pinctrl-single,pins = <
148 /* Wakeup UART is used by System firmware */
154 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
219 phy0: ethernet-phy@0 {
221 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
222 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
227 phy-mode = "rgmii-rxid";
228 phy-handle = <&phy0>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&main_i2c0_pins_default>;
234 clock-frequency = <400000>;
239 gpio-controller;
240 #gpio-cells = <2>;
246 gpio-controller;
247 #gpio-cells = <2>;
252 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
259 pinctrl-names = "default";
260 pinctrl-0 = <&main_i2c1_pins_default>;
261 clock-frequency = <400000>;
266 gpio-controller;
267 #gpio-cells = <2>;
268 gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
276 non-removable;
277 ti,driver-strength-ohm = <50>;
278 disable-wp;
283 pinctrl-0 = <&main_mmc1_pins_default>;
284 pinctrl-names = "default";
285 vmmc-supply = <&vdd_mmc1>;
286 vqmmc-supply = <&vdd_sd_dv>;
287 ti,driver-strength-ohm = <50>;
288 disable-wp;
292 idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
297 idle-states = <1>; /* USB0 to SERDES lane 3 */
301 pinctrl-names = "default";
302 pinctrl-0 = <&main_usbss0_pins_default>;
303 ti,vbus-divider;
304 ti,usb2-only;
309 maximum-speed = "high-speed";
314 ti,adc-channels = <0 1 2 3 4 5 6 7>;
319 clock-frequency = <100000000>;
325 cdns,num-lanes = <2>;
326 #phy-cells = <0>;
327 cdns,phy-type = <PHY_TYPE_PCIE>;
333 cdns,num-lanes = <1>;
334 #phy-cells = <0>;
335 cdns,phy-type = <PHY_TYPE_QSGMII>;
341 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
343 phy-names = "pcie-phy";
344 num-lanes = <2>;
349 phy-names = "pcie-phy";
350 num-lanes = <2>;