Lines Matching +full:0 +full:x8c
24 reg = <0 0x20210000 0 0x10000>;
29 reg = <0 0x402b0000 0 0x10000>;
34 reg = <0 0x402e0000 0 0x10000>;
39 reg = <0 0x40400000 0 0x10000>;
44 reg = <0 0x415e0000 0 0x1000000>;
49 reg = <0 0x61100000 0 0x10000>;
54 reg = <0 0x62100000 0 0x10000>;
59 reg = <0 0x63100000 0 0x10000>;
64 reg = <0 0x70b00000 0 0x40000>;
71 ranges = <0 0x0 0x70000000 0x10000000>;
73 uart0: serial@0 {
76 reg = <0x0 0x100>;
87 reg = <0x100000 0x100>;
98 reg = <0x200000 0x100>;
109 reg = <0x300000 0x100>;
126 reg = <0 0x20100000 0 0x4000>;
136 reg = <0 0x50430000 0 0x1000>;
146 sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>;
147 sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>;
148 sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>;
149 sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>;
171 reg = <0 0x40030000 0 0x10000>;
172 hwlocks = <&hwlock 0>;
175 #size-cells = <0>;
180 reg = <0 0x40050000 0 0x20>;
187 reg = <0 0x40050020 0 0x20>;
193 reg = <0 0x40500000 0 0x1000>;
201 reg = <0 0x40210000 0 0x80>;
211 reg = <0 0x40210080 0 0x20>;
221 reg = <0 0x402100a0 0 0x20>;
231 reg = <0 0x402100c0 0 0x20>;
241 reg = <0 0x40280000 0 0x1000>;
251 reg = <0 0x402a0000 0 0x10000>;
256 reg = <0 0x40310000 0 0x1000>;
273 reg = <0 0x41580000 0 0x4000>;
285 #clock-cells = <0>;
292 #clock-cells = <0>;
299 #clock-cells = <0>;
306 #clock-cells = <0>;