Lines Matching +full:dw +full:- +full:apb +full:- +full:gpio
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
46 #address-cells = <2>;
47 #size-cells = <0>;
51 compatible = "arm,cortex-a55";
54 enable-method = "psci";
55 operating-points-v2 = <&cpu0_opp_table>;
60 compatible = "arm,cortex-a55";
62 enable-method = "psci";
63 operating-points-v2 = <&cpu0_opp_table>;
68 compatible = "arm,cortex-a55";
70 enable-method = "psci";
71 operating-points-v2 = <&cpu0_opp_table>;
76 compatible = "arm,cortex-a55";
78 enable-method = "psci";
79 operating-points-v2 = <&cpu0_opp_table>;
83 cpu0_opp_table: cpu0-opp-table {
84 compatible = "operating-points-v2";
85 opp-shared;
87 opp-408000000 {
88 opp-hz = /bits/ 64 <408000000>;
89 opp-microvolt = <900000 900000 1150000>;
90 clock-latency-ns = <40000>;
93 opp-600000000 {
94 opp-hz = /bits/ 64 <600000000>;
95 opp-microvolt = <900000 900000 1150000>;
98 opp-816000000 {
99 opp-hz = /bits/ 64 <816000000>;
100 opp-microvolt = <900000 900000 1150000>;
101 opp-suspend;
104 opp-1104000000 {
105 opp-hz = /bits/ 64 <1104000000>;
106 opp-microvolt = <900000 900000 1150000>;
109 opp-1416000000 {
110 opp-hz = /bits/ 64 <1416000000>;
111 opp-microvolt = <900000 900000 1150000>;
114 opp-1608000000 {
115 opp-hz = /bits/ 64 <1608000000>;
116 opp-microvolt = <975000 975000 1150000>;
119 opp-1800000000 {
120 opp-hz = /bits/ 64 <1800000000>;
121 opp-microvolt = <1050000 1050000 1150000>;
124 opp-1992000000 {
125 opp-hz = /bits/ 64 <1992000000>;
126 opp-microvolt = <1150000 1150000 1150000>;
132 compatible = "arm,scmi-smc";
133 arm,smc-id = <0x82000010>;
135 #address-cells = <1>;
136 #size-cells = <0>;
140 #clock-cells = <1>;
146 compatible = "arm,cortex-a55-pmu";
151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
155 compatible = "arm,psci-1.0";
160 compatible = "arm,armv8-timer";
165 arm,no-tick-in-suspend;
169 compatible = "fixed-clock";
170 clock-frequency = <24000000>;
171 clock-output-names = "xin24m";
172 #clock-cells = <0>;
176 compatible = "fixed-clock";
177 clock-frequency = <32768>;
178 clock-output-names = "xin32k";
179 pinctrl-0 = <&clk32k_out0>;
180 pinctrl-names = "default";
181 #clock-cells = <0>;
185 compatible = "mmio-sram";
187 #address-cells = <1>;
188 #size-cells = <1>;
192 compatible = "arm,scmi-shmem";
197 gic: interrupt-controller@fd400000 {
198 compatible = "arm,gic-v3";
202 interrupt-controller;
203 #interrupt-cells = <3>;
204 mbi-alias = <0x0 0xfd100000>;
205 mbi-ranges = <296 24>;
206 msi-controller;
210 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
215 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
219 pmucru: clock-controller@fdd00000 {
220 compatible = "rockchip,rk3568-pmucru";
222 #clock-cells = <1>;
223 #reset-cells = <1>;
226 cru: clock-controller@fdd20000 {
227 compatible = "rockchip,rk3568-cru";
229 #clock-cells = <1>;
230 #reset-cells = <1>;
234 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
238 clock-names = "i2c", "pclk";
239 pinctrl-0 = <&i2c0_xfer>;
240 pinctrl-names = "default";
241 #address-cells = <1>;
242 #size-cells = <0>;
247 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
251 clock-names = "baudclk", "apb_pclk";
253 pinctrl-0 = <&uart0_xfer>;
254 pinctrl-names = "default";
255 reg-io-width = <4>;
256 reg-shift = <2>;
261 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
266 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
267 fifo-depth = <0x100>;
268 max-frequency = <150000000>;
270 reset-names = "reset";
275 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
280 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
281 fifo-depth = <0x100>;
282 max-frequency = <150000000>;
284 reset-names = "reset";
289 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
294 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
295 fifo-depth = <0x100>;
296 max-frequency = <150000000>;
298 reset-names = "reset";
303 compatible = "rockchip,rk3568-dwcmshc";
306 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
307 assigned-clock-rates = <200000000>, <24000000>;
311 clock-names = "core", "bus", "axi", "block", "timer";
320 arm,pl330-periph-burst;
322 clock-names = "apb_pclk";
323 #dma-cells = <1>;
331 arm,pl330-periph-burst;
333 clock-names = "apb_pclk";
334 #dma-cells = <1>;
338 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
342 clock-names = "i2c", "pclk";
343 pinctrl-0 = <&i2c1_xfer>;
344 pinctrl-names = "default";
345 #address-cells = <1>;
346 #size-cells = <0>;
351 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
355 clock-names = "i2c", "pclk";
356 pinctrl-0 = <&i2c2m0_xfer>;
357 pinctrl-names = "default";
358 #address-cells = <1>;
359 #size-cells = <0>;
364 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
368 clock-names = "i2c", "pclk";
369 pinctrl-0 = <&i2c3m0_xfer>;
370 pinctrl-names = "default";
371 #address-cells = <1>;
372 #size-cells = <0>;
377 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
381 clock-names = "i2c", "pclk";
382 pinctrl-0 = <&i2c4m0_xfer>;
383 pinctrl-names = "default";
384 #address-cells = <1>;
385 #size-cells = <0>;
390 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
394 clock-names = "i2c", "pclk";
395 pinctrl-0 = <&i2c5m0_xfer>;
396 pinctrl-names = "default";
397 #address-cells = <1>;
398 #size-cells = <0>;
403 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
407 clock-names = "baudclk", "apb_pclk";
409 pinctrl-0 = <&uart1m0_xfer>;
410 pinctrl-names = "default";
411 reg-io-width = <4>;
412 reg-shift = <2>;
417 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
421 clock-names = "baudclk", "apb_pclk";
423 pinctrl-0 = <&uart2m0_xfer>;
424 pinctrl-names = "default";
425 reg-io-width = <4>;
426 reg-shift = <2>;
431 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
435 clock-names = "baudclk", "apb_pclk";
437 pinctrl-0 = <&uart3m0_xfer>;
438 pinctrl-names = "default";
439 reg-io-width = <4>;
440 reg-shift = <2>;
445 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
449 clock-names = "baudclk", "apb_pclk";
451 pinctrl-0 = <&uart4m0_xfer>;
452 pinctrl-names = "default";
453 reg-io-width = <4>;
454 reg-shift = <2>;
459 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
463 clock-names = "baudclk", "apb_pclk";
465 pinctrl-0 = <&uart5m0_xfer>;
466 pinctrl-names = "default";
467 reg-io-width = <4>;
468 reg-shift = <2>;
473 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
477 clock-names = "baudclk", "apb_pclk";
479 pinctrl-0 = <&uart6m0_xfer>;
480 pinctrl-names = "default";
481 reg-io-width = <4>;
482 reg-shift = <2>;
487 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
491 clock-names = "baudclk", "apb_pclk";
493 pinctrl-0 = <&uart7m0_xfer>;
494 pinctrl-names = "default";
495 reg-io-width = <4>;
496 reg-shift = <2>;
501 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
505 clock-names = "baudclk", "apb_pclk";
507 pinctrl-0 = <&uart8m0_xfer>;
508 pinctrl-names = "default";
509 reg-io-width = <4>;
510 reg-shift = <2>;
515 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
519 clock-names = "baudclk", "apb_pclk";
521 pinctrl-0 = <&uart9m0_xfer>;
522 pinctrl-names = "default";
523 reg-io-width = <4>;
524 reg-shift = <2>;
529 compatible = "rockchip,rk3568-pinctrl";
532 #address-cells = <2>;
533 #size-cells = <2>;
536 gpio0: gpio@fdd60000 {
537 compatible = "rockchip,gpio-bank";
541 gpio-controller;
542 #gpio-cells = <2>;
543 interrupt-controller;
544 #interrupt-cells = <2>;
547 gpio1: gpio@fe740000 {
548 compatible = "rockchip,gpio-bank";
552 gpio-controller;
553 #gpio-cells = <2>;
554 interrupt-controller;
555 #interrupt-cells = <2>;
558 gpio2: gpio@fe750000 {
559 compatible = "rockchip,gpio-bank";
563 gpio-controller;
564 #gpio-cells = <2>;
565 interrupt-controller;
566 #interrupt-cells = <2>;
569 gpio3: gpio@fe760000 {
570 compatible = "rockchip,gpio-bank";
574 gpio-controller;
575 #gpio-cells = <2>;
576 interrupt-controller;
577 #interrupt-cells = <2>;
580 gpio4: gpio@fe770000 {
581 compatible = "rockchip,gpio-bank";
585 gpio-controller;
586 #gpio-cells = <2>;
587 interrupt-controller;
588 #interrupt-cells = <2>;
593 #include "rk3568-pinctrl.dtsi"