Lines Matching +full:rk3288 +full:- +full:dw +full:- +full:mshc
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
40 #address-cells = <2>;
41 #size-cells = <0>;
43 cpu-map {
71 compatible = "arm,cortex-a53";
73 enable-method = "psci";
74 capacity-dmips-mhz = <485>;
76 #cooling-cells = <2>; /* min followed by max */
77 dynamic-power-coefficient = <100>;
78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
83 compatible = "arm,cortex-a53";
85 enable-method = "psci";
86 capacity-dmips-mhz = <485>;
88 #cooling-cells = <2>; /* min followed by max */
89 dynamic-power-coefficient = <100>;
90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
95 compatible = "arm,cortex-a53";
97 enable-method = "psci";
98 capacity-dmips-mhz = <485>;
100 #cooling-cells = <2>; /* min followed by max */
101 dynamic-power-coefficient = <100>;
102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
107 compatible = "arm,cortex-a53";
109 enable-method = "psci";
110 capacity-dmips-mhz = <485>;
112 #cooling-cells = <2>; /* min followed by max */
113 dynamic-power-coefficient = <100>;
114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
119 compatible = "arm,cortex-a72";
121 enable-method = "psci";
122 capacity-dmips-mhz = <1024>;
124 #cooling-cells = <2>; /* min followed by max */
125 dynamic-power-coefficient = <436>;
126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
131 compatible = "arm,cortex-a72";
133 enable-method = "psci";
134 capacity-dmips-mhz = <1024>;
136 #cooling-cells = <2>; /* min followed by max */
137 dynamic-power-coefficient = <436>;
138 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
141 idle-states {
142 entry-method = "psci";
144 CPU_SLEEP: cpu-sleep {
145 compatible = "arm,idle-state";
146 local-timer-stop;
147 arm,psci-suspend-param = <0x0010000>;
148 entry-latency-us = <120>;
149 exit-latency-us = <250>;
150 min-residency-us = <900>;
153 CLUSTER_SLEEP: cluster-sleep {
154 compatible = "arm,idle-state";
155 local-timer-stop;
156 arm,psci-suspend-param = <0x1010000>;
157 entry-latency-us = <400>;
158 exit-latency-us = <500>;
159 min-residency-us = <2000>;
164 display-subsystem {
165 compatible = "rockchip,display-subsystem";
170 compatible = "arm,cortex-a53-pmu";
175 compatible = "arm,cortex-a72-pmu";
180 compatible = "arm,psci-1.0";
185 compatible = "arm,armv8-timer";
190 arm,no-tick-in-suspend;
194 compatible = "fixed-clock";
195 clock-frequency = <24000000>;
196 clock-output-names = "xin24m";
197 #clock-cells = <0>;
201 compatible = "rockchip,rk3399-pcie";
204 reg-names = "axi-base", "apb-base";
206 #address-cells = <3>;
207 #size-cells = <2>;
208 #interrupt-cells = <1>;
209 aspm-no-l0s;
210 bus-range = <0x0 0x1f>;
213 clock-names = "aclk", "aclk-perf",
218 interrupt-names = "sys", "legacy", "client";
219 interrupt-map-mask = <0 0 0 7>;
220 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
224 max-link-speed = <1>;
225 msi-map = <0x0 &its 0x0 0x1000>;
228 phy-names = "pcie-phy-0", "pcie-phy-1",
229 "pcie-phy-2", "pcie-phy-3";
236 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
240 pcie0_intc: interrupt-controller {
241 interrupt-controller;
242 #address-cells = <0>;
243 #interrupt-cells = <1>;
248 compatible = "rockchip,rk3399-gmac";
251 interrupt-names = "macirq";
256 clock-names = "stmmaceth", "mac_clk_rx",
260 power-domains = <&power RK3399_PD_GMAC>;
262 reset-names = "stmmaceth";
269 compatible = "rockchip,rk3399-dw-mshc",
270 "rockchip,rk3288-dw-mshc";
273 max-frequency = <150000000>;
276 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
277 fifo-depth = <0x100>;
278 power-domains = <&power RK3399_PD_SDIOAUDIO>;
280 reset-names = "reset";
285 compatible = "rockchip,rk3399-dw-mshc",
286 "rockchip,rk3288-dw-mshc";
289 max-frequency = <150000000>;
290 assigned-clocks = <&cru HCLK_SD>;
291 assigned-clock-rates = <200000000>;
294 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
295 fifo-depth = <0x100>;
296 power-domains = <&power RK3399_PD_SD>;
298 reset-names = "reset";
303 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
306 arasan,soc-ctl-syscon = <&grf>;
307 assigned-clocks = <&cru SCLK_EMMC>;
308 assigned-clock-rates = <200000000>;
310 clock-names = "clk_xin", "clk_ahb";
311 clock-output-names = "emmc_cardclock";
312 #clock-cells = <0>;
314 phy-names = "phy_arasan";
315 power-domains = <&power RK3399_PD_EMMC>;
316 disable-cqe-dcmd;
321 compatible = "generic-ehci";
327 phy-names = "usb";
332 compatible = "generic-ohci";
338 phy-names = "usb";
343 compatible = "generic-ehci";
349 phy-names = "usb";
354 compatible = "generic-ohci";
360 phy-names = "usb";
365 compatible = "rockchip,rk3399-dwc3";
366 #address-cells = <2>;
367 #size-cells = <2>;
372 clock-names = "ref_clk", "suspend_clk",
376 reset-names = "usb3-otg";
385 clock-names = "ref", "bus_early", "suspend";
388 phy-names = "usb2-phy", "usb3-phy";
391 snps,dis-u2-freeclk-exists-quirk;
393 snps,dis-del-phy-power-chg-quirk;
394 snps,dis-tx-ipgap-linecheck-quirk;
395 power-domains = <&power RK3399_PD_USB3>;
401 compatible = "rockchip,rk3399-dwc3";
402 #address-cells = <2>;
403 #size-cells = <2>;
408 clock-names = "ref_clk", "suspend_clk",
412 reset-names = "usb3-otg";
421 clock-names = "ref", "bus_early", "suspend";
424 phy-names = "usb2-phy", "usb3-phy";
427 snps,dis-u2-freeclk-exists-quirk;
429 snps,dis-del-phy-power-chg-quirk;
430 snps,dis-tx-ipgap-linecheck-quirk;
431 power-domains = <&power RK3399_PD_USB3>;
437 compatible = "rockchip,rk3399-cdn-dp";
440 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
441 assigned-clock-rates = <100000000>, <200000000>;
444 clock-names = "core-clk", "pclk", "spdif", "grf";
446 power-domains = <&power RK3399_PD_HDCP>;
449 reset-names = "spdif", "dptx", "apb", "core";
451 #sound-dai-cells = <1>;
456 #address-cells = <1>;
457 #size-cells = <0>;
461 remote-endpoint = <&vopb_out_dp>;
466 remote-endpoint = <&vopl_out_dp>;
472 gic: interrupt-controller@fee00000 {
473 compatible = "arm,gic-v3";
474 #interrupt-cells = <4>;
475 #address-cells = <2>;
476 #size-cells = <2>;
478 interrupt-controller;
486 its: interrupt-controller@fee20000 {
487 compatible = "arm,gic-v3-its";
488 msi-controller;
489 #msi-cells = <1>;
493 ppi-partitions {
494 ppi_cluster0: interrupt-partition-0 {
498 ppi_cluster1: interrupt-partition-1 {
505 compatible = "rockchip,rk3399-saradc";
508 #io-channel-cells = <1>;
510 clock-names = "saradc", "apb_pclk";
512 reset-names = "saradc-apb";
517 compatible = "rockchip,rk3399-i2c";
519 assigned-clocks = <&cru SCLK_I2C1>;
520 assigned-clock-rates = <200000000>;
522 clock-names = "i2c", "pclk";
524 pinctrl-names = "default";
525 pinctrl-0 = <&i2c1_xfer>;
526 #address-cells = <1>;
527 #size-cells = <0>;
532 compatible = "rockchip,rk3399-i2c";
534 assigned-clocks = <&cru SCLK_I2C2>;
535 assigned-clock-rates = <200000000>;
537 clock-names = "i2c", "pclk";
539 pinctrl-names = "default";
540 pinctrl-0 = <&i2c2_xfer>;
541 #address-cells = <1>;
542 #size-cells = <0>;
547 compatible = "rockchip,rk3399-i2c";
549 assigned-clocks = <&cru SCLK_I2C3>;
550 assigned-clock-rates = <200000000>;
552 clock-names = "i2c", "pclk";
554 pinctrl-names = "default";
555 pinctrl-0 = <&i2c3_xfer>;
556 #address-cells = <1>;
557 #size-cells = <0>;
562 compatible = "rockchip,rk3399-i2c";
564 assigned-clocks = <&cru SCLK_I2C5>;
565 assigned-clock-rates = <200000000>;
567 clock-names = "i2c", "pclk";
569 pinctrl-names = "default";
570 pinctrl-0 = <&i2c5_xfer>;
571 #address-cells = <1>;
572 #size-cells = <0>;
577 compatible = "rockchip,rk3399-i2c";
579 assigned-clocks = <&cru SCLK_I2C6>;
580 assigned-clock-rates = <200000000>;
582 clock-names = "i2c", "pclk";
584 pinctrl-names = "default";
585 pinctrl-0 = <&i2c6_xfer>;
586 #address-cells = <1>;
587 #size-cells = <0>;
592 compatible = "rockchip,rk3399-i2c";
594 assigned-clocks = <&cru SCLK_I2C7>;
595 assigned-clock-rates = <200000000>;
597 clock-names = "i2c", "pclk";
599 pinctrl-names = "default";
600 pinctrl-0 = <&i2c7_xfer>;
601 #address-cells = <1>;
602 #size-cells = <0>;
607 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
610 clock-names = "baudclk", "apb_pclk";
612 reg-shift = <2>;
613 reg-io-width = <4>;
614 pinctrl-names = "default";
615 pinctrl-0 = <&uart0_xfer>;
620 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
623 clock-names = "baudclk", "apb_pclk";
625 reg-shift = <2>;
626 reg-io-width = <4>;
627 pinctrl-names = "default";
628 pinctrl-0 = <&uart1_xfer>;
633 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
636 clock-names = "baudclk", "apb_pclk";
638 reg-shift = <2>;
639 reg-io-width = <4>;
640 pinctrl-names = "default";
641 pinctrl-0 = <&uart2c_xfer>;
646 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
649 clock-names = "baudclk", "apb_pclk";
651 reg-shift = <2>;
652 reg-io-width = <4>;
653 pinctrl-names = "default";
654 pinctrl-0 = <&uart3_xfer>;
659 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
662 clock-names = "spiclk", "apb_pclk";
665 dma-names = "tx", "rx";
666 pinctrl-names = "default";
667 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
668 #address-cells = <1>;
669 #size-cells = <0>;
674 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
677 clock-names = "spiclk", "apb_pclk";
680 dma-names = "tx", "rx";
681 pinctrl-names = "default";
682 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
683 #address-cells = <1>;
684 #size-cells = <0>;
689 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
692 clock-names = "spiclk", "apb_pclk";
695 dma-names = "tx", "rx";
696 pinctrl-names = "default";
697 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
698 #address-cells = <1>;
699 #size-cells = <0>;
704 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
707 clock-names = "spiclk", "apb_pclk";
710 dma-names = "tx", "rx";
711 pinctrl-names = "default";
712 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
713 #address-cells = <1>;
714 #size-cells = <0>;
719 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
722 clock-names = "spiclk", "apb_pclk";
725 dma-names = "tx", "rx";
726 pinctrl-names = "default";
727 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
728 power-domains = <&power RK3399_PD_SDIOAUDIO>;
729 #address-cells = <1>;
730 #size-cells = <0>;
734 thermal_zones: thermal-zones {
735 cpu_thermal: cpu-thermal {
736 polling-delay-passive = <100>;
737 polling-delay = <1000>;
739 thermal-sensors = <&tsadc 0>;
759 cooling-maps {
762 cooling-device =
768 cooling-device =
779 gpu_thermal: gpu-thermal {
780 polling-delay-passive = <100>;
781 polling-delay = <1000>;
783 thermal-sensors = <&tsadc 1>;
798 cooling-maps {
801 cooling-device =
809 compatible = "rockchip,rk3399-tsadc";
812 assigned-clocks = <&cru SCLK_TSADC>;
813 assigned-clock-rates = <750000>;
815 clock-names = "tsadc", "apb_pclk";
817 reset-names = "tsadc-apb";
819 rockchip,hw-tshut-temp = <95000>;
820 pinctrl-names = "init", "default", "sleep";
821 pinctrl-0 = <&otp_pin>;
822 pinctrl-1 = <&otp_out>;
823 pinctrl-2 = <&otp_pin>;
824 #thermal-sensor-cells = <1>;
829 compatible = "rockchip,rk3399-qos", "syscon";
834 compatible = "rockchip,rk3399-qos", "syscon";
839 compatible = "rockchip,rk3399-qos", "syscon";
844 compatible = "rockchip,rk3399-qos", "syscon";
849 compatible = "rockchip,rk3399-qos", "syscon";
854 compatible = "rockchip,rk3399-qos", "syscon";
859 compatible = "rockchip,rk3399-qos", "syscon";
864 compatible = "rockchip,rk3399-qos", "syscon";
869 compatible = "rockchip,rk3399-qos", "syscon";
874 compatible = "rockchip,rk3399-qos", "syscon";
879 compatible = "rockchip,rk3399-qos", "syscon";
884 compatible = "rockchip,rk3399-qos", "syscon";
889 compatible = "rockchip,rk3399-qos", "syscon";
894 compatible = "rockchip,rk3399-qos", "syscon";
899 compatible = "rockchip,rk3399-qos", "syscon";
904 compatible = "rockchip,rk3399-qos", "syscon";
909 compatible = "rockchip,rk3399-qos", "syscon";
914 compatible = "rockchip,rk3399-qos", "syscon";
919 compatible = "rockchip,rk3399-qos", "syscon";
924 compatible = "rockchip,rk3399-qos", "syscon";
929 compatible = "rockchip,rk3399-qos", "syscon";
934 compatible = "rockchip,rk3399-qos", "syscon";
939 compatible = "rockchip,rk3399-qos", "syscon";
944 compatible = "rockchip,rk3399-qos", "syscon";
949 compatible = "rockchip,rk3399-qos", "syscon";
953 pmu: power-management@ff310000 {
954 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
964 power: power-controller {
965 compatible = "rockchip,rk3399-power-controller";
966 #power-domain-cells = <1>;
967 #address-cells = <1>;
968 #size-cells = <0>;
971 power-domain@RK3399_PD_IEP {
976 #power-domain-cells = <0>;
978 power-domain@RK3399_PD_RGA {
984 #power-domain-cells = <0>;
986 power-domain@RK3399_PD_VCODEC {
991 #power-domain-cells = <0>;
993 power-domain@RK3399_PD_VDU {
999 #power-domain-cells = <0>;
1003 power-domain@RK3399_PD_GPU {
1007 #power-domain-cells = <0>;
1011 power-domain@RK3399_PD_EDP {
1014 #power-domain-cells = <0>;
1016 power-domain@RK3399_PD_EMMC {
1020 #power-domain-cells = <0>;
1022 power-domain@RK3399_PD_GMAC {
1027 #power-domain-cells = <0>;
1029 power-domain@RK3399_PD_SD {
1034 #power-domain-cells = <0>;
1036 power-domain@RK3399_PD_SDIOAUDIO {
1040 #power-domain-cells = <0>;
1042 power-domain@RK3399_PD_TCPD0 {
1046 #power-domain-cells = <0>;
1048 power-domain@RK3399_PD_TCPD1 {
1052 #power-domain-cells = <0>;
1054 power-domain@RK3399_PD_USB3 {
1059 #power-domain-cells = <0>;
1061 power-domain@RK3399_PD_VIO {
1063 #power-domain-cells = <1>;
1064 #address-cells = <1>;
1065 #size-cells = <0>;
1067 power-domain@RK3399_PD_HDCP {
1073 #power-domain-cells = <0>;
1075 power-domain@RK3399_PD_ISP0 {
1081 #power-domain-cells = <0>;
1083 power-domain@RK3399_PD_ISP1 {
1089 #power-domain-cells = <0>;
1091 power-domain@RK3399_PD_VO {
1093 #power-domain-cells = <1>;
1094 #address-cells = <1>;
1095 #size-cells = <0>;
1097 power-domain@RK3399_PD_VOPB {
1103 #power-domain-cells = <0>;
1105 power-domain@RK3399_PD_VOPL {
1110 #power-domain-cells = <0>;
1118 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1121 pmu_io_domains: io-domains {
1122 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1128 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1131 clock-names = "spiclk", "apb_pclk";
1133 pinctrl-names = "default";
1134 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1141 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1144 clock-names = "baudclk", "apb_pclk";
1146 reg-shift = <2>;
1147 reg-io-width = <4>;
1148 pinctrl-names = "default";
1149 pinctrl-0 = <&uart4_xfer>;
1154 compatible = "rockchip,rk3399-i2c";
1156 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1157 assigned-clock-rates = <200000000>;
1159 clock-names = "i2c", "pclk";
1161 pinctrl-names = "default";
1162 pinctrl-0 = <&i2c0_xfer>;
1163 #address-cells = <1>;
1164 #size-cells = <0>;
1169 compatible = "rockchip,rk3399-i2c";
1171 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1172 assigned-clock-rates = <200000000>;
1174 clock-names = "i2c", "pclk";
1176 pinctrl-names = "default";
1177 pinctrl-0 = <&i2c4_xfer>;
1178 #address-cells = <1>;
1179 #size-cells = <0>;
1184 compatible = "rockchip,rk3399-i2c";
1186 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1187 assigned-clock-rates = <200000000>;
1189 clock-names = "i2c", "pclk";
1191 pinctrl-names = "default";
1192 pinctrl-0 = <&i2c8_xfer>;
1193 #address-cells = <1>;
1194 #size-cells = <0>;
1199 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1201 #pwm-cells = <3>;
1202 pinctrl-names = "default";
1203 pinctrl-0 = <&pwm0_pin>;
1209 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1211 #pwm-cells = <3>;
1212 pinctrl-names = "default";
1213 pinctrl-0 = <&pwm1_pin>;
1219 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1221 #pwm-cells = <3>;
1222 pinctrl-names = "default";
1223 pinctrl-0 = <&pwm2_pin>;
1229 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1231 #pwm-cells = <3>;
1232 pinctrl-names = "default";
1233 pinctrl-0 = <&pwm3a_pin>;
1238 vpu: video-codec@ff650000 {
1239 compatible = "rockchip,rk3399-vpu";
1243 interrupt-names = "vepu", "vdpu";
1245 clock-names = "aclk", "hclk";
1247 power-domains = <&power RK3399_PD_VCODEC>;
1254 interrupt-names = "vpu_mmu";
1256 clock-names = "aclk", "iface";
1257 #iommu-cells = <0>;
1258 power-domains = <&power RK3399_PD_VCODEC>;
1261 vdec: video-codec@ff660000 {
1262 compatible = "rockchip,rk3399-vdec";
1267 clock-names = "axi", "ahb", "cabac", "core";
1269 power-domains = <&power RK3399_PD_VDU>;
1276 interrupt-names = "vdec_mmu";
1278 clock-names = "aclk", "iface";
1279 power-domains = <&power RK3399_PD_VDU>;
1280 #iommu-cells = <0>;
1287 interrupt-names = "iep_mmu";
1289 clock-names = "aclk", "iface";
1290 #iommu-cells = <0>;
1295 compatible = "rockchip,rk3399-rga";
1299 clock-names = "aclk", "hclk", "sclk";
1301 reset-names = "core", "axi", "ahb";
1302 power-domains = <&power RK3399_PD_RGA>;
1306 compatible = "rockchip,rk3399-efuse";
1308 #address-cells = <1>;
1309 #size-cells = <1>;
1311 clock-names = "pclk_efuse";
1314 cpu_id: cpu-id@7 {
1317 cpub_leakage: cpu-leakage@17 {
1320 gpu_leakage: gpu-leakage@18 {
1323 center_leakage: center-leakage@19 {
1326 cpul_leakage: cpu-leakage@1a {
1329 logic_leakage: logic-leakage@1b {
1332 wafer_info: wafer-info@1c {
1337 dmac_bus: dma-controller@ff6d0000 {
1342 #dma-cells = <1>;
1343 arm,pl330-periph-burst;
1345 clock-names = "apb_pclk";
1348 dmac_peri: dma-controller@ff6e0000 {
1353 #dma-cells = <1>;
1354 arm,pl330-periph-burst;
1356 clock-names = "apb_pclk";
1359 pmucru: pmu-clock-controller@ff750000 {
1360 compatible = "rockchip,rk3399-pmucru";
1363 #clock-cells = <1>;
1364 #reset-cells = <1>;
1365 assigned-clocks = <&pmucru PLL_PPLL>;
1366 assigned-clock-rates = <676000000>;
1369 cru: clock-controller@ff760000 {
1370 compatible = "rockchip,rk3399-cru";
1373 #clock-cells = <1>;
1374 #reset-cells = <1>;
1375 assigned-clocks =
1386 assigned-clock-rates =
1400 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1402 #address-cells = <1>;
1403 #size-cells = <1>;
1405 io_domains: io-domains {
1406 compatible = "rockchip,rk3399-io-voltage-domain";
1410 mipi_dphy_rx0: mipi-dphy-rx0 {
1411 compatible = "rockchip,rk3399-mipi-dphy-rx0";
1415 clock-names = "dphy-ref", "dphy-cfg", "grf";
1416 power-domains = <&power RK3399_PD_VIO>;
1417 #phy-cells = <0>;
1422 compatible = "rockchip,rk3399-usb2phy";
1425 clock-names = "phyclk";
1426 #clock-cells = <0>;
1427 clock-output-names = "clk_usbphy0_480m";
1430 u2phy0_host: host-port {
1431 #phy-cells = <0>;
1433 interrupt-names = "linestate";
1437 u2phy0_otg: otg-port {
1438 #phy-cells = <0>;
1442 interrupt-names = "otg-bvalid", "otg-id",
1449 compatible = "rockchip,rk3399-usb2phy";
1452 clock-names = "phyclk";
1453 #clock-cells = <0>;
1454 clock-output-names = "clk_usbphy1_480m";
1457 u2phy1_host: host-port {
1458 #phy-cells = <0>;
1460 interrupt-names = "linestate";
1464 u2phy1_otg: otg-port {
1465 #phy-cells = <0>;
1469 interrupt-names = "otg-bvalid", "otg-id",
1476 compatible = "rockchip,rk3399-emmc-phy";
1479 clock-names = "emmcclk";
1480 #phy-cells = <0>;
1484 pcie_phy: pcie-phy {
1485 compatible = "rockchip,rk3399-pcie-phy";
1487 clock-names = "refclk";
1488 #phy-cells = <1>;
1490 drive-impedance-ohm = <50>;
1491 reset-names = "phy";
1497 compatible = "rockchip,rk3399-typec-phy";
1501 clock-names = "tcpdcore", "tcpdphy-ref";
1502 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1503 assigned-clock-rates = <50000000>;
1504 power-domains = <&power RK3399_PD_TCPD0>;
1508 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1512 tcphy0_dp: dp-port {
1513 #phy-cells = <0>;
1516 tcphy0_usb3: usb3-port {
1517 #phy-cells = <0>;
1522 compatible = "rockchip,rk3399-typec-phy";
1526 clock-names = "tcpdcore", "tcpdphy-ref";
1527 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1528 assigned-clock-rates = <50000000>;
1529 power-domains = <&power RK3399_PD_TCPD1>;
1533 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1537 tcphy1_dp: dp-port {
1538 #phy-cells = <0>;
1541 tcphy1_usb3: usb3-port {
1542 #phy-cells = <0>;
1547 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt";
1554 compatible = "rockchip,rk3399-timer";
1558 clock-names = "pclk", "timer";
1562 compatible = "rockchip,rk3399-spdif";
1566 dma-names = "tx";
1567 clock-names = "mclk", "hclk";
1569 pinctrl-names = "default";
1570 pinctrl-0 = <&spdif_bus>;
1571 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1572 #sound-dai-cells = <0>;
1577 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1582 dma-names = "tx", "rx";
1583 clock-names = "i2s_clk", "i2s_hclk";
1585 pinctrl-names = "default";
1586 pinctrl-0 = <&i2s0_8ch_bus>;
1587 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1588 #sound-dai-cells = <0>;
1593 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1597 dma-names = "tx", "rx";
1598 clock-names = "i2s_clk", "i2s_hclk";
1600 pinctrl-names = "default";
1601 pinctrl-0 = <&i2s1_2ch_bus>;
1602 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1603 #sound-dai-cells = <0>;
1608 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1612 dma-names = "tx", "rx";
1613 clock-names = "i2s_clk", "i2s_hclk";
1615 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1616 #sound-dai-cells = <0>;
1621 compatible = "rockchip,rk3399-vop-lit";
1624 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1625 assigned-clock-rates = <400000000>, <100000000>;
1627 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1629 power-domains = <&power RK3399_PD_VOPL>;
1631 reset-names = "axi", "ahb", "dclk";
1635 #address-cells = <1>;
1636 #size-cells = <0>;
1640 remote-endpoint = <&mipi_in_vopl>;
1645 remote-endpoint = <&edp_in_vopl>;
1650 remote-endpoint = <&hdmi_in_vopl>;
1655 remote-endpoint = <&mipi1_in_vopl>;
1660 remote-endpoint = <&dp_in_vopl>;
1669 interrupt-names = "vopl_mmu";
1671 clock-names = "aclk", "iface";
1672 power-domains = <&power RK3399_PD_VOPL>;
1673 #iommu-cells = <0>;
1678 compatible = "rockchip,rk3399-vop-big";
1681 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1682 assigned-clock-rates = <400000000>, <100000000>;
1684 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1686 power-domains = <&power RK3399_PD_VOPB>;
1688 reset-names = "axi", "ahb", "dclk";
1692 #address-cells = <1>;
1693 #size-cells = <0>;
1697 remote-endpoint = <&edp_in_vopb>;
1702 remote-endpoint = <&mipi_in_vopb>;
1707 remote-endpoint = <&hdmi_in_vopb>;
1712 remote-endpoint = <&mipi1_in_vopb>;
1717 remote-endpoint = <&dp_in_vopb>;
1726 interrupt-names = "vopb_mmu";
1728 clock-names = "aclk", "iface";
1729 power-domains = <&power RK3399_PD_VOPB>;
1730 #iommu-cells = <0>;
1735 compatible = "rockchip,rk3399-cif-isp";
1741 clock-names = "isp", "aclk", "hclk";
1744 phy-names = "dphy";
1745 power-domains = <&power RK3399_PD_ISP0>;
1749 #address-cells = <1>;
1750 #size-cells = <0>;
1754 #address-cells = <1>;
1755 #size-cells = <0>;
1764 interrupt-names = "isp0_mmu";
1766 clock-names = "aclk", "iface";
1767 #iommu-cells = <0>;
1768 power-domains = <&power RK3399_PD_ISP0>;
1769 rockchip,disable-mmu-reset;
1776 interrupt-names = "isp1_mmu";
1778 clock-names = "aclk", "iface";
1779 #iommu-cells = <0>;
1780 power-domains = <&power RK3399_PD_ISP1>;
1781 rockchip,disable-mmu-reset;
1784 hdmi_sound: hdmi-sound {
1785 compatible = "simple-audio-card";
1786 simple-audio-card,format = "i2s";
1787 simple-audio-card,mclk-fs = <256>;
1788 simple-audio-card,name = "hdmi-sound";
1791 simple-audio-card,cpu {
1792 sound-dai = <&i2s2>;
1794 simple-audio-card,codec {
1795 sound-dai = <&hdmi>;
1800 compatible = "rockchip,rk3399-dw-hdmi";
1808 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
1809 power-domains = <&power RK3399_PD_HDCP>;
1810 reg-io-width = <4>;
1812 #sound-dai-cells = <0>;
1817 #address-cells = <1>;
1818 #size-cells = <0>;
1822 remote-endpoint = <&vopb_out_hdmi>;
1826 remote-endpoint = <&vopl_out_hdmi>;
1833 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1838 clock-names = "ref", "pclk", "phy_cfg", "grf";
1839 power-domains = <&power RK3399_PD_VIO>;
1841 reset-names = "apb";
1843 #address-cells = <1>;
1844 #size-cells = <0>;
1848 #address-cells = <1>;
1849 #size-cells = <0>;
1853 #address-cells = <1>;
1854 #size-cells = <0>;
1858 remote-endpoint = <&vopb_out_mipi>;
1862 remote-endpoint = <&vopl_out_mipi>;
1869 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1874 clock-names = "ref", "pclk", "phy_cfg", "grf";
1875 power-domains = <&power RK3399_PD_VIO>;
1877 reset-names = "apb";
1879 #address-cells = <1>;
1880 #size-cells = <0>;
1884 #address-cells = <1>;
1885 #size-cells = <0>;
1889 #address-cells = <1>;
1890 #size-cells = <0>;
1894 remote-endpoint = <&vopb_out_mipi1>;
1899 remote-endpoint = <&vopl_out_mipi1>;
1906 compatible = "rockchip,rk3399-edp";
1910 clock-names = "dp", "pclk", "grf";
1911 pinctrl-names = "default";
1912 pinctrl-0 = <&edp_hpd>;
1913 power-domains = <&power RK3399_PD_EDP>;
1915 reset-names = "dp";
1920 #address-cells = <1>;
1921 #size-cells = <0>;
1924 #address-cells = <1>;
1925 #size-cells = <0>;
1929 remote-endpoint = <&vopb_out_edp>;
1934 remote-endpoint = <&vopl_out_edp>;
1941 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1946 interrupt-names = "job", "mmu", "gpu";
1948 #cooling-cells = <2>;
1949 power-domains = <&power RK3399_PD_GPU>;
1954 compatible = "rockchip,rk3399-pinctrl";
1957 #address-cells = <2>;
1958 #size-cells = <2>;
1962 compatible = "rockchip,gpio-bank";
1967 gpio-controller;
1968 #gpio-cells = <0x2>;
1970 interrupt-controller;
1971 #interrupt-cells = <0x2>;
1975 compatible = "rockchip,gpio-bank";
1980 gpio-controller;
1981 #gpio-cells = <0x2>;
1983 interrupt-controller;
1984 #interrupt-cells = <0x2>;
1988 compatible = "rockchip,gpio-bank";
1993 gpio-controller;
1994 #gpio-cells = <0x2>;
1996 interrupt-controller;
1997 #interrupt-cells = <0x2>;
2001 compatible = "rockchip,gpio-bank";
2006 gpio-controller;
2007 #gpio-cells = <0x2>;
2009 interrupt-controller;
2010 #interrupt-cells = <0x2>;
2014 compatible = "rockchip,gpio-bank";
2019 gpio-controller;
2020 #gpio-cells = <0x2>;
2022 interrupt-controller;
2023 #interrupt-cells = <0x2>;
2026 pcfg_pull_up: pcfg-pull-up {
2027 bias-pull-up;
2030 pcfg_pull_down: pcfg-pull-down {
2031 bias-pull-down;
2034 pcfg_pull_none: pcfg-pull-none {
2035 bias-disable;
2038 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2039 bias-disable;
2040 drive-strength = <12>;
2043 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2044 bias-disable;
2045 drive-strength = <13>;
2048 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2049 bias-disable;
2050 drive-strength = <18>;
2053 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2054 bias-disable;
2055 drive-strength = <20>;
2058 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2059 bias-pull-up;
2060 drive-strength = <2>;
2063 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2064 bias-pull-up;
2065 drive-strength = <8>;
2068 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2069 bias-pull-up;
2070 drive-strength = <18>;
2073 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2074 bias-pull-up;
2075 drive-strength = <20>;
2078 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2079 bias-pull-down;
2080 drive-strength = <4>;
2083 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2084 bias-pull-down;
2085 drive-strength = <8>;
2088 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2089 bias-pull-down;
2090 drive-strength = <12>;
2093 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2094 bias-pull-down;
2095 drive-strength = <18>;
2098 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2099 bias-pull-down;
2100 drive-strength = <20>;
2103 pcfg_output_high: pcfg-output-high {
2104 output-high;
2107 pcfg_output_low: pcfg-output-low {
2108 output-low;
2112 clk_32k: clk-32k {
2118 edp_hpd: edp-hpd {
2125 rgmii_pins: rgmii-pins {
2159 rmii_pins: rmii-pins {
2185 i2c0_xfer: i2c0-xfer {
2193 i2c1_xfer: i2c1-xfer {
2201 i2c2_xfer: i2c2-xfer {
2209 i2c3_xfer: i2c3-xfer {
2217 i2c4_xfer: i2c4-xfer {
2225 i2c5_xfer: i2c5-xfer {
2233 i2c6_xfer: i2c6-xfer {
2241 i2c7_xfer: i2c7-xfer {
2249 i2c8_xfer: i2c8-xfer {
2257 i2s0_2ch_bus: i2s0-2ch-bus {
2267 i2s0_8ch_bus: i2s0-8ch-bus {
2282 i2s1_2ch_bus: i2s1-2ch-bus {
2293 sdio0_bus1: sdio0-bus1 {
2298 sdio0_bus4: sdio0-bus4 {
2306 sdio0_cmd: sdio0-cmd {
2311 sdio0_clk: sdio0-clk {
2316 sdio0_cd: sdio0-cd {
2321 sdio0_pwr: sdio0-pwr {
2326 sdio0_bkpwr: sdio0-bkpwr {
2331 sdio0_wp: sdio0-wp {
2336 sdio0_int: sdio0-int {
2343 sdmmc_bus1: sdmmc-bus1 {
2348 sdmmc_bus4: sdmmc-bus4 {
2356 sdmmc_clk: sdmmc-clk {
2361 sdmmc_cmd: sdmmc-cmd {
2366 sdmmc_cd: sdmmc-cd {
2371 sdmmc_wp: sdmmc-wp {
2378 ap_pwroff: ap-pwroff {
2382 ddrio_pwroff: ddrio-pwroff {
2388 spdif_bus: spdif-bus {
2393 spdif_bus_1: spdif-bus-1 {
2400 spi0_clk: spi0-clk {
2404 spi0_cs0: spi0-cs0 {
2408 spi0_cs1: spi0-cs1 {
2412 spi0_tx: spi0-tx {
2416 spi0_rx: spi0-rx {
2423 spi1_clk: spi1-clk {
2427 spi1_cs0: spi1-cs0 {
2431 spi1_rx: spi1-rx {
2435 spi1_tx: spi1-tx {
2442 spi2_clk: spi2-clk {
2446 spi2_cs0: spi2-cs0 {
2450 spi2_rx: spi2-rx {
2454 spi2_tx: spi2-tx {
2461 spi3_clk: spi3-clk {
2465 spi3_cs0: spi3-cs0 {
2469 spi3_rx: spi3-rx {
2473 spi3_tx: spi3-tx {
2480 spi4_clk: spi4-clk {
2484 spi4_cs0: spi4-cs0 {
2488 spi4_rx: spi4-rx {
2492 spi4_tx: spi4-tx {
2499 spi5_clk: spi5-clk {
2503 spi5_cs0: spi5-cs0 {
2507 spi5_rx: spi5-rx {
2511 spi5_tx: spi5-tx {
2518 test_clkout0: test-clkout0 {
2523 test_clkout1: test-clkout1 {
2528 test_clkout2: test-clkout2 {
2535 otp_pin: otp-pin {
2539 otp_out: otp-out {
2545 uart0_xfer: uart0-xfer {
2551 uart0_cts: uart0-cts {
2556 uart0_rts: uart0-rts {
2563 uart1_xfer: uart1-xfer {
2571 uart2a_xfer: uart2a-xfer {
2579 uart2b_xfer: uart2b-xfer {
2587 uart2c_xfer: uart2c-xfer {
2595 uart3_xfer: uart3-xfer {
2601 uart3_cts: uart3-cts {
2606 uart3_rts: uart3-rts {
2613 uart4_xfer: uart4-xfer {
2621 uarthdcp_xfer: uarthdcp-xfer {
2629 pwm0_pin: pwm0-pin {
2634 pwm0_pin_pull_down: pwm0-pin-pull-down {
2639 vop0_pwm_pin: vop0-pwm-pin {
2644 vop1_pwm_pin: vop1-pwm-pin {
2651 pwm1_pin: pwm1-pin {
2656 pwm1_pin_pull_down: pwm1-pin-pull-down {
2663 pwm2_pin: pwm2-pin {
2668 pwm2_pin_pull_down: pwm2-pin-pull-down {
2675 pwm3a_pin: pwm3a-pin {
2682 pwm3b_pin: pwm3b-pin {
2689 hdmi_i2c_xfer: hdmi-i2c-xfer {
2695 hdmi_cec: hdmi-cec {
2702 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2707 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {