Lines Matching +full:rk3288 +full:- +full:dw +full:- +full:mshc
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
39 #address-cells = <0x2>;
40 #size-cells = <0x0>;
42 cpu-map {
76 compatible = "arm,cortex-a53";
78 enable-method = "psci";
79 #cooling-cells = <2>; /* min followed by max */
84 compatible = "arm,cortex-a53";
86 enable-method = "psci";
87 #cooling-cells = <2>; /* min followed by max */
92 compatible = "arm,cortex-a53";
94 enable-method = "psci";
95 #cooling-cells = <2>; /* min followed by max */
100 compatible = "arm,cortex-a53";
102 enable-method = "psci";
103 #cooling-cells = <2>; /* min followed by max */
108 compatible = "arm,cortex-a53";
110 enable-method = "psci";
111 #cooling-cells = <2>; /* min followed by max */
116 compatible = "arm,cortex-a53";
118 enable-method = "psci";
119 #cooling-cells = <2>; /* min followed by max */
124 compatible = "arm,cortex-a53";
126 enable-method = "psci";
127 #cooling-cells = <2>; /* min followed by max */
132 compatible = "arm,cortex-a53";
134 enable-method = "psci";
135 #cooling-cells = <2>; /* min followed by max */
139 arm-pmu {
140 compatible = "arm,armv8-pmuv3";
149 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
155 compatible = "arm,psci-0.2";
160 compatible = "arm,armv8-timer";
172 compatible = "fixed-clock";
173 clock-frequency = <24000000>;
174 clock-output-names = "xin24m";
175 #clock-cells = <0>;
179 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
181 max-frequency = <150000000>;
184 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
185 fifo-depth = <0x100>;
188 reset-names = "reset";
193 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
195 max-frequency = <150000000>;
198 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
199 fifo-depth = <0x100>;
202 reset-names = "reset";
207 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
209 max-frequency = <150000000>;
212 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
213 fifo-depth = <0x100>;
216 reset-names = "reset";
224 #io-channel-cells = <1>;
226 clock-names = "saradc", "apb_pclk";
228 reset-names = "saradc-apb";
233 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
236 clock-names = "spiclk", "apb_pclk";
238 pinctrl-names = "default";
239 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
240 #address-cells = <1>;
241 #size-cells = <0>;
246 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
249 clock-names = "spiclk", "apb_pclk";
251 pinctrl-names = "default";
252 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
253 #address-cells = <1>;
254 #size-cells = <0>;
259 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
262 clock-names = "spiclk", "apb_pclk";
264 pinctrl-names = "default";
265 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
266 #address-cells = <1>;
267 #size-cells = <0>;
272 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
275 #address-cells = <1>;
276 #size-cells = <0>;
277 clock-names = "i2c";
279 pinctrl-names = "default";
280 pinctrl-0 = <&i2c2_xfer>;
285 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
288 #address-cells = <1>;
289 #size-cells = <0>;
290 clock-names = "i2c";
292 pinctrl-names = "default";
293 pinctrl-0 = <&i2c3_xfer>;
298 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
301 #address-cells = <1>;
302 #size-cells = <0>;
303 clock-names = "i2c";
305 pinctrl-names = "default";
306 pinctrl-0 = <&i2c4_xfer>;
311 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
314 #address-cells = <1>;
315 #size-cells = <0>;
316 clock-names = "i2c";
318 pinctrl-names = "default";
319 pinctrl-0 = <&i2c5_xfer>;
324 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
326 clock-frequency = <24000000>;
328 clock-names = "baudclk", "apb_pclk";
330 reg-shift = <2>;
331 reg-io-width = <4>;
336 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
338 clock-frequency = <24000000>;
340 clock-names = "baudclk", "apb_pclk";
342 reg-shift = <2>;
343 reg-io-width = <4>;
348 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
350 clock-frequency = <24000000>;
352 clock-names = "baudclk", "apb_pclk";
354 reg-shift = <2>;
355 reg-io-width = <4>;
360 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
362 clock-frequency = <24000000>;
364 clock-names = "baudclk", "apb_pclk";
366 reg-shift = <2>;
367 reg-io-width = <4>;
371 dmac_peri: dma-controller@ff250000 {
376 #dma-cells = <1>;
377 arm,pl330-broken-no-flushp;
378 arm,pl330-periph-burst;
380 clock-names = "apb_pclk";
383 thermal-zones {
384 cpu_thermal: cpu-thermal {
385 polling-delay-passive = <100>; /* milliseconds */
386 polling-delay = <5000>; /* milliseconds */
388 thermal-sensors = <&tsadc 0>;
408 cooling-maps {
411 cooling-device =
419 cooling-device =
428 gpu_thermal: gpu-thermal {
429 polling-delay-passive = <100>; /* milliseconds */
430 polling-delay = <5000>; /* milliseconds */
432 thermal-sensors = <&tsadc 1>;
447 cooling-maps {
450 cooling-device =
461 compatible = "rockchip,rk3368-tsadc";
465 clock-names = "tsadc", "apb_pclk";
467 reset-names = "tsadc-apb";
468 pinctrl-names = "init", "default", "sleep";
469 pinctrl-0 = <&otp_pin>;
470 pinctrl-1 = <&otp_out>;
471 pinctrl-2 = <&otp_pin>;
472 #thermal-sensor-cells = <1>;
473 rockchip,hw-tshut-temp = <95000>;
478 compatible = "rockchip,rk3368-gmac";
481 interrupt-names = "macirq";
487 clock-names = "stmmaceth",
495 compatible = "generic-ehci";
503 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
508 clock-names = "otg";
510 g-np-tx-fifo-size = <16>;
511 g-rx-fifo-size = <275>;
512 g-tx-fifo-size = <256 128 128 64 64 32>;
516 dmac_bus: dma-controller@ff600000 {
521 #dma-cells = <1>;
522 arm,pl330-broken-no-flushp;
523 arm,pl330-periph-burst;
525 clock-names = "apb_pclk";
529 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
532 clock-names = "i2c";
534 pinctrl-names = "default";
535 pinctrl-0 = <&i2c0_xfer>;
536 #address-cells = <1>;
537 #size-cells = <0>;
542 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
545 #address-cells = <1>;
546 #size-cells = <0>;
547 clock-names = "i2c";
549 pinctrl-names = "default";
550 pinctrl-0 = <&i2c1_xfer>;
555 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
557 #pwm-cells = <3>;
558 pinctrl-names = "default";
559 pinctrl-0 = <&pwm0_pin>;
565 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
567 #pwm-cells = <3>;
568 pinctrl-names = "default";
569 pinctrl-0 = <&pwm1_pin>;
575 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
577 #pwm-cells = <3>;
583 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
585 #pwm-cells = <3>;
586 pinctrl-names = "default";
587 pinctrl-0 = <&pwm3_pin>;
593 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
596 clock-names = "baudclk", "apb_pclk";
598 pinctrl-names = "default";
599 pinctrl-0 = <&uart2_xfer>;
600 reg-shift = <2>;
601 reg-io-width = <4>;
606 compatible = "rockchip,rk3368-mailbox";
613 clock-names = "pclk_mailbox";
614 #mbox-cells = <1>;
619 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
622 pmu_io_domains: io-domains {
623 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
627 reboot-mode {
628 compatible = "syscon-reboot-mode";
630 mode-normal = <BOOT_NORMAL>;
631 mode-recovery = <BOOT_RECOVERY>;
632 mode-bootloader = <BOOT_FASTBOOT>;
633 mode-loader = <BOOT_BL_DOWNLOAD>;
637 cru: clock-controller@ff760000 {
638 compatible = "rockchip,rk3368-cru";
641 #clock-cells = <1>;
642 #reset-cells = <1>;
646 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
649 io_domains: io-domains {
650 compatible = "rockchip,rk3368-io-voltage-domain";
656 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
664 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
668 clock-names = "pclk", "timer";
672 compatible = "rockchip,rk3368-spdif";
676 clock-names = "mclk", "hclk";
678 dma-names = "tx";
679 pinctrl-names = "default";
680 pinctrl-0 = <&spdif_tx>;
684 i2s_2ch: i2s-2ch@ff890000 {
685 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
688 clock-names = "i2s_clk", "i2s_hclk";
691 dma-names = "tx", "rx";
695 i2s_8ch: i2s-8ch@ff898000 {
696 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
699 clock-names = "i2s_clk", "i2s_hclk";
702 dma-names = "tx", "rx";
703 pinctrl-names = "default";
704 pinctrl-0 = <&i2s_8ch_bus>;
712 interrupt-names = "iep_mmu";
714 clock-names = "aclk", "iface";
715 #iommu-cells = <0>;
724 interrupt-names = "isp_mmu";
726 clock-names = "aclk", "iface";
727 #iommu-cells = <0>;
728 rockchip,disable-mmu-reset;
736 interrupt-names = "vop_mmu";
738 clock-names = "aclk", "iface";
739 #iommu-cells = <0>;
748 interrupt-names = "hevc_mmu";
750 clock-names = "aclk", "iface";
751 #iommu-cells = <0>;
760 interrupt-names = "vepu_mmu", "vdpu_mmu";
762 clock-names = "aclk", "iface";
763 #iommu-cells = <0>;
768 compatible = "rockchip,rk3368-efuse";
770 #address-cells = <1>;
771 #size-cells = <1>;
773 clock-names = "pclk_efuse";
775 cpu_leakage: cpu-leakage@17 {
778 temp_adjust: temp-adjust@1f {
783 gic: interrupt-controller@ffb71000 {
784 compatible = "arm,gic-400";
785 interrupt-controller;
786 #interrupt-cells = <3>;
787 #address-cells = <0>;
798 compatible = "rockchip,rk3368-pinctrl";
801 #address-cells = <0x2>;
802 #size-cells = <0x2>;
806 compatible = "rockchip,gpio-bank";
811 gpio-controller;
812 #gpio-cells = <0x2>;
814 interrupt-controller;
815 #interrupt-cells = <0x2>;
819 compatible = "rockchip,gpio-bank";
824 gpio-controller;
825 #gpio-cells = <0x2>;
827 interrupt-controller;
828 #interrupt-cells = <0x2>;
832 compatible = "rockchip,gpio-bank";
837 gpio-controller;
838 #gpio-cells = <0x2>;
840 interrupt-controller;
841 #interrupt-cells = <0x2>;
845 compatible = "rockchip,gpio-bank";
850 gpio-controller;
851 #gpio-cells = <0x2>;
853 interrupt-controller;
854 #interrupt-cells = <0x2>;
857 pcfg_pull_up: pcfg-pull-up {
858 bias-pull-up;
861 pcfg_pull_down: pcfg-pull-down {
862 bias-pull-down;
865 pcfg_pull_none: pcfg-pull-none {
866 bias-disable;
869 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
870 bias-disable;
871 drive-strength = <12>;
875 emmc_clk: emmc-clk {
879 emmc_cmd: emmc-cmd {
883 emmc_pwr: emmc-pwr {
887 emmc_bus1: emmc-bus1 {
891 emmc_bus4: emmc-bus4 {
898 emmc_bus8: emmc-bus8 {
911 rgmii_pins: rgmii-pins {
929 rmii_pins: rmii-pins {
944 i2c0_xfer: i2c0-xfer {
951 i2c1_xfer: i2c1-xfer {
958 i2c2_xfer: i2c2-xfer {
965 i2c3_xfer: i2c3-xfer {
972 i2c4_xfer: i2c4-xfer {
979 i2c5_xfer: i2c5-xfer {
986 i2s_8ch_bus: i2s-8ch-bus {
1000 pwm0_pin: pwm0-pin {
1006 pwm1_pin: pwm1-pin {
1012 pwm3_pin: pwm3-pin {
1018 sdio0_bus1: sdio0-bus1 {
1022 sdio0_bus4: sdio0-bus4 {
1029 sdio0_cmd: sdio0-cmd {
1033 sdio0_clk: sdio0-clk {
1037 sdio0_cd: sdio0-cd {
1041 sdio0_wp: sdio0-wp {
1045 sdio0_pwr: sdio0-pwr {
1049 sdio0_bkpwr: sdio0-bkpwr {
1053 sdio0_int: sdio0-int {
1059 sdmmc_clk: sdmmc-clk {
1063 sdmmc_cmd: sdmmc-cmd {
1067 sdmmc_cd: sdmmc-cd {
1071 sdmmc_bus1: sdmmc-bus1 {
1075 sdmmc_bus4: sdmmc-bus4 {
1084 spdif_tx: spdif-tx {
1090 spi0_clk: spi0-clk {
1093 spi0_cs0: spi0-cs0 {
1096 spi0_cs1: spi0-cs1 {
1099 spi0_tx: spi0-tx {
1102 spi0_rx: spi0-rx {
1108 spi1_clk: spi1-clk {
1111 spi1_cs0: spi1-cs0 {
1114 spi1_cs1: spi1-cs1 {
1117 spi1_rx: spi1-rx {
1120 spi1_tx: spi1-tx {
1126 spi2_clk: spi2-clk {
1129 spi2_cs0: spi2-cs0 {
1132 spi2_rx: spi2-rx {
1135 spi2_tx: spi2-tx {
1141 otp_pin: otp-pin {
1145 otp_out: otp-out {
1151 uart0_xfer: uart0-xfer {
1156 uart0_cts: uart0-cts {
1160 uart0_rts: uart0-rts {
1166 uart1_xfer: uart1-xfer {
1171 uart1_cts: uart1-cts {
1175 uart1_rts: uart1-rts {
1181 uart2_xfer: uart2-xfer {
1189 uart3_xfer: uart3-xfer {
1194 uart3_cts: uart3-cts {
1198 uart3_rts: uart3-rts {
1204 uart4_xfer: uart4-xfer {
1209 uart4_cts: uart4-cts {
1213 uart4_rts: uart4-rts {