Lines Matching +full:rk3399 +full:- +full:dwc3
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
35 #address-cells = <2>;
36 #size-cells = <0>;
40 compatible = "arm,cortex-a53";
43 #cooling-cells = <2>;
44 cpu-idle-states = <&CPU_SLEEP>;
45 dynamic-power-coefficient = <120>;
46 enable-method = "psci";
47 next-level-cache = <&l2>;
48 operating-points-v2 = <&cpu0_opp_table>;
53 compatible = "arm,cortex-a53";
56 #cooling-cells = <2>;
57 cpu-idle-states = <&CPU_SLEEP>;
58 dynamic-power-coefficient = <120>;
59 enable-method = "psci";
60 next-level-cache = <&l2>;
61 operating-points-v2 = <&cpu0_opp_table>;
66 compatible = "arm,cortex-a53";
69 #cooling-cells = <2>;
70 cpu-idle-states = <&CPU_SLEEP>;
71 dynamic-power-coefficient = <120>;
72 enable-method = "psci";
73 next-level-cache = <&l2>;
74 operating-points-v2 = <&cpu0_opp_table>;
79 compatible = "arm,cortex-a53";
82 #cooling-cells = <2>;
83 cpu-idle-states = <&CPU_SLEEP>;
84 dynamic-power-coefficient = <120>;
85 enable-method = "psci";
86 next-level-cache = <&l2>;
87 operating-points-v2 = <&cpu0_opp_table>;
90 idle-states {
91 entry-method = "psci";
93 CPU_SLEEP: cpu-sleep {
94 compatible = "arm,idle-state";
95 local-timer-stop;
96 arm,psci-suspend-param = <0x0010000>;
97 entry-latency-us = <120>;
98 exit-latency-us = <250>;
99 min-residency-us = <900>;
103 l2: l2-cache0 {
109 compatible = "operating-points-v2";
110 opp-shared;
112 opp-408000000 {
113 opp-hz = /bits/ 64 <408000000>;
114 opp-microvolt = <950000>;
115 clock-latency-ns = <40000>;
116 opp-suspend;
118 opp-600000000 {
119 opp-hz = /bits/ 64 <600000000>;
120 opp-microvolt = <950000>;
121 clock-latency-ns = <40000>;
123 opp-816000000 {
124 opp-hz = /bits/ 64 <816000000>;
125 opp-microvolt = <1000000>;
126 clock-latency-ns = <40000>;
128 opp-1008000000 {
129 opp-hz = /bits/ 64 <1008000000>;
130 opp-microvolt = <1100000>;
131 clock-latency-ns = <40000>;
133 opp-1200000000 {
134 opp-hz = /bits/ 64 <1200000000>;
135 opp-microvolt = <1225000>;
136 clock-latency-ns = <40000>;
138 opp-1296000000 {
139 opp-hz = /bits/ 64 <1296000000>;
140 opp-microvolt = <1300000>;
141 clock-latency-ns = <40000>;
145 analog_sound: analog-sound {
146 compatible = "simple-audio-card";
147 simple-audio-card,format = "i2s";
148 simple-audio-card,mclk-fs = <256>;
149 simple-audio-card,name = "Analog";
152 simple-audio-card,cpu {
153 sound-dai = <&i2s1>;
156 simple-audio-card,codec {
157 sound-dai = <&codec>;
161 arm-pmu {
162 compatible = "arm,cortex-a53-pmu";
167 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
170 display_subsystem: display-subsystem {
171 compatible = "rockchip,display-subsystem";
175 hdmi_sound: hdmi-sound {
176 compatible = "simple-audio-card";
177 simple-audio-card,format = "i2s";
178 simple-audio-card,mclk-fs = <128>;
179 simple-audio-card,name = "HDMI";
182 simple-audio-card,cpu {
183 sound-dai = <&i2s0>;
186 simple-audio-card,codec {
187 sound-dai = <&hdmi>;
192 compatible = "arm,psci-1.0", "arm,psci-0.2";
197 compatible = "arm,armv8-timer";
205 compatible = "fixed-clock";
206 #clock-cells = <0>;
207 clock-frequency = <24000000>;
208 clock-output-names = "xin24m";
212 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
216 clock-names = "i2s_clk", "i2s_hclk";
218 dma-names = "tx", "rx";
219 #sound-dai-cells = <0>;
224 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
228 clock-names = "i2s_clk", "i2s_hclk";
230 dma-names = "tx", "rx";
231 #sound-dai-cells = <0>;
236 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
240 clock-names = "i2s_clk", "i2s_hclk";
242 dma-names = "tx", "rx";
243 #sound-dai-cells = <0>;
248 compatible = "rockchip,rk3328-spdif";
252 clock-names = "mclk", "hclk";
254 dma-names = "tx";
255 pinctrl-names = "default";
256 pinctrl-0 = <&spdifm2_tx>;
257 #sound-dai-cells = <0>;
265 clock-names = "pdm_clk", "pdm_hclk";
267 dma-names = "rx";
268 pinctrl-names = "default", "sleep";
269 pinctrl-0 = <&pdmm0_clk
274 pinctrl-1 = <&pdmm0_clk_sleep
283 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
286 io_domains: io-domains {
287 compatible = "rockchip,rk3328-io-voltage-domain";
292 compatible = "rockchip,rk3328-grf-gpio";
293 gpio-controller;
294 #gpio-cells = <2>;
297 power: power-controller {
298 compatible = "rockchip,rk3328-power-controller";
299 #power-domain-cells = <1>;
300 #address-cells = <1>;
301 #size-cells = <0>;
303 power-domain@RK3328_PD_HEVC {
305 #power-domain-cells = <0>;
307 power-domain@RK3328_PD_VIDEO {
309 #power-domain-cells = <0>;
311 power-domain@RK3328_PD_VPU {
314 #power-domain-cells = <0>;
318 reboot-mode {
319 compatible = "syscon-reboot-mode";
321 mode-normal = <BOOT_NORMAL>;
322 mode-recovery = <BOOT_RECOVERY>;
323 mode-bootloader = <BOOT_FASTBOOT>;
324 mode-loader = <BOOT_BL_DOWNLOAD>;
329 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
333 clock-names = "baudclk", "apb_pclk";
335 dma-names = "tx", "rx";
336 pinctrl-names = "default";
337 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
338 reg-io-width = <4>;
339 reg-shift = <2>;
344 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
348 clock-names = "baudclk", "apb_pclk";
350 dma-names = "tx", "rx";
351 pinctrl-names = "default";
352 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
353 reg-io-width = <4>;
354 reg-shift = <2>;
359 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
363 clock-names = "baudclk", "apb_pclk";
365 dma-names = "tx", "rx";
366 pinctrl-names = "default";
367 pinctrl-0 = <&uart2m1_xfer>;
368 reg-io-width = <4>;
369 reg-shift = <2>;
374 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
377 #address-cells = <1>;
378 #size-cells = <0>;
380 clock-names = "i2c", "pclk";
381 pinctrl-names = "default";
382 pinctrl-0 = <&i2c0_xfer>;
387 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
390 #address-cells = <1>;
391 #size-cells = <0>;
393 clock-names = "i2c", "pclk";
394 pinctrl-names = "default";
395 pinctrl-0 = <&i2c1_xfer>;
400 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
403 #address-cells = <1>;
404 #size-cells = <0>;
406 clock-names = "i2c", "pclk";
407 pinctrl-names = "default";
408 pinctrl-0 = <&i2c2_xfer>;
413 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
416 #address-cells = <1>;
417 #size-cells = <0>;
419 clock-names = "i2c", "pclk";
420 pinctrl-names = "default";
421 pinctrl-0 = <&i2c3_xfer>;
426 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
429 #address-cells = <1>;
430 #size-cells = <0>;
432 clock-names = "spiclk", "apb_pclk";
434 dma-names = "tx", "rx";
435 pinctrl-names = "default";
436 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
441 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt";
448 compatible = "rockchip,rk3328-pwm";
451 clock-names = "pwm", "pclk";
452 pinctrl-names = "default";
453 pinctrl-0 = <&pwm0_pin>;
454 #pwm-cells = <3>;
459 compatible = "rockchip,rk3328-pwm";
462 clock-names = "pwm", "pclk";
463 pinctrl-names = "default";
464 pinctrl-0 = <&pwm1_pin>;
465 #pwm-cells = <3>;
470 compatible = "rockchip,rk3328-pwm";
473 clock-names = "pwm", "pclk";
474 pinctrl-names = "default";
475 pinctrl-0 = <&pwm2_pin>;
476 #pwm-cells = <3>;
481 compatible = "rockchip,rk3328-pwm";
485 clock-names = "pwm", "pclk";
486 pinctrl-names = "default";
487 pinctrl-0 = <&pwmir_pin>;
488 #pwm-cells = <3>;
497 arm,pl330-periph-burst;
499 clock-names = "apb_pclk";
500 #dma-cells = <1>;
503 thermal-zones {
504 soc_thermal: soc-thermal {
505 polling-delay-passive = <20>;
506 polling-delay = <1000>;
507 sustainable-power = <1000>;
509 thermal-sensors = <&tsadc 0>;
512 threshold: trip-point0 {
517 target: trip-point1 {
522 soc_crit: soc-crit {
529 cooling-maps {
532 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
544 compatible = "rockchip,rk3328-tsadc";
547 assigned-clocks = <&cru SCLK_TSADC>;
548 assigned-clock-rates = <50000>;
550 clock-names = "tsadc", "apb_pclk";
551 pinctrl-names = "init", "default", "sleep";
552 pinctrl-0 = <&otp_pin>;
553 pinctrl-1 = <&otp_out>;
554 pinctrl-2 = <&otp_pin>;
556 reset-names = "tsadc-apb";
558 rockchip,hw-tshut-temp = <100000>;
559 #thermal-sensor-cells = <1>;
564 compatible = "rockchip,rk3328-efuse";
566 #address-cells = <1>;
567 #size-cells = <1>;
569 clock-names = "pclk_efuse";
570 rockchip,efuse-size = <0x20>;
576 cpu_leakage: cpu-leakage@17 {
579 logic_leakage: logic-leakage@19 {
582 efuse_cpu_version: cpu-version@1a {
589 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
592 #io-channel-cells = <1>;
594 clock-names = "saradc", "apb_pclk";
596 reset-names = "saradc-apb";
601 compatible = "rockchip,rk3328-mali", "arm,mali-450";
610 interrupt-names = "gp",
618 clock-names = "bus", "core";
626 interrupt-names = "h265e_mmu";
628 clock-names = "aclk", "iface";
629 #iommu-cells = <0>;
637 interrupt-names = "vepu_mmu";
639 clock-names = "aclk", "iface";
640 #iommu-cells = <0>;
644 vpu: video-codec@ff350000 {
645 compatible = "rockchip,rk3328-vpu";
648 interrupt-names = "vdpu";
650 clock-names = "aclk", "hclk";
652 power-domains = <&power RK3328_PD_VPU>;
659 interrupt-names = "vpu_mmu";
661 clock-names = "aclk", "iface";
662 #iommu-cells = <0>;
663 power-domains = <&power RK3328_PD_VPU>;
670 interrupt-names = "rkvdec_mmu";
672 clock-names = "aclk", "iface";
673 #iommu-cells = <0>;
678 compatible = "rockchip,rk3328-vop";
682 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
684 reset-names = "axi", "ahb", "dclk";
689 #address-cells = <1>;
690 #size-cells = <0>;
694 remote-endpoint = <&hdmi_in_vop>;
703 interrupt-names = "vop_mmu";
705 clock-names = "aclk", "iface";
706 #iommu-cells = <0>;
711 compatible = "rockchip,rk3328-dw-hdmi";
713 reg-io-width = <4>;
719 clock-names = "iahb",
723 phy-names = "hdmi";
724 pinctrl-names = "default";
725 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
727 #sound-dai-cells = <0>;
733 remote-endpoint = <&vop_out_hdmi>;
740 compatible = "rockchip,rk3328-codec";
743 clock-names = "pclk", "mclk";
745 #sound-dai-cells = <0>;
750 compatible = "rockchip,rk3328-hdmi-phy";
754 clock-names = "sysclk", "refoclk", "refpclk";
755 clock-output-names = "hdmi_phy";
756 #clock-cells = <0>;
757 nvmem-cells = <&efuse_cpu_version>;
758 nvmem-cell-names = "cpu-version";
759 #phy-cells = <0>;
763 cru: clock-controller@ff440000 {
764 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
767 #clock-cells = <1>;
768 #reset-cells = <1>;
769 assigned-clocks =
792 assigned-clock-parents =
796 assigned-clock-rates =
816 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
817 "simple-mfd";
819 #address-cells = <1>;
820 #size-cells = <1>;
823 compatible = "rockchip,rk3328-usb2phy";
826 clock-names = "phyclk";
827 clock-output-names = "usb480m_phy";
828 #clock-cells = <0>;
829 assigned-clocks = <&cru USB480M>;
830 assigned-clock-parents = <&u2phy>;
833 u2phy_otg: otg-port {
834 #phy-cells = <0>;
838 interrupt-names = "otg-bvalid", "otg-id",
843 u2phy_host: host-port {
844 #phy-cells = <0>;
846 interrupt-names = "linestate";
853 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
858 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
859 fifo-depth = <0x100>;
860 max-frequency = <150000000>;
865 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
870 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
871 fifo-depth = <0x100>;
872 max-frequency = <150000000>;
877 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
882 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
883 fifo-depth = <0x100>;
884 max-frequency = <150000000>;
889 compatible = "rockchip,rk3328-gmac";
892 interrupt-names = "macirq";
897 clock-names = "stmmaceth", "mac_clk_rx",
902 reset-names = "stmmaceth";
909 compatible = "rockchip,rk3328-gmac";
913 interrupt-names = "macirq";
918 clock-names = "stmmaceth", "mac_clk_rx",
923 reset-names = "stmmaceth";
924 phy-mode = "rmii";
925 phy-handle = <&phy>;
931 compatible = "snps,dwmac-mdio";
932 #address-cells = <1>;
933 #size-cells = <0>;
935 phy: ethernet-phy@0 {
936 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
940 pinctrl-names = "default";
941 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
942 phy-is-integrated;
948 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
953 clock-names = "otg";
955 g-np-tx-fifo-size = <16>;
956 g-rx-fifo-size = <280>;
957 g-tx-fifo-size = <256 128 128 64 32 16>;
959 phy-names = "usb2-phy";
964 compatible = "generic-ehci";
969 phy-names = "usb";
974 compatible = "generic-ohci";
979 phy-names = "usb";
984 compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
989 clock-names = "ref_clk", "suspend_clk",
993 snps,dis-del-phy-power-chg-quirk;
995 snps,dis-tx-ipgap-linecheck-quirk;
996 snps,dis-u2-freeclk-exists-quirk;
1002 gic: interrupt-controller@ff811000 {
1003 compatible = "arm,gic-400";
1004 #interrupt-cells = <3>;
1005 #address-cells = <0>;
1006 interrupt-controller;
1016 compatible = "rockchip,rk3328-pinctrl";
1018 #address-cells = <2>;
1019 #size-cells = <2>;
1023 compatible = "rockchip,gpio-bank";
1028 gpio-controller;
1029 #gpio-cells = <2>;
1031 interrupt-controller;
1032 #interrupt-cells = <2>;
1036 compatible = "rockchip,gpio-bank";
1041 gpio-controller;
1042 #gpio-cells = <2>;
1044 interrupt-controller;
1045 #interrupt-cells = <2>;
1049 compatible = "rockchip,gpio-bank";
1054 gpio-controller;
1055 #gpio-cells = <2>;
1057 interrupt-controller;
1058 #interrupt-cells = <2>;
1062 compatible = "rockchip,gpio-bank";
1067 gpio-controller;
1068 #gpio-cells = <2>;
1070 interrupt-controller;
1071 #interrupt-cells = <2>;
1074 pcfg_pull_up: pcfg-pull-up {
1075 bias-pull-up;
1078 pcfg_pull_down: pcfg-pull-down {
1079 bias-pull-down;
1082 pcfg_pull_none: pcfg-pull-none {
1083 bias-disable;
1086 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1087 bias-disable;
1088 drive-strength = <2>;
1091 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1092 bias-pull-up;
1093 drive-strength = <2>;
1096 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1097 bias-pull-up;
1098 drive-strength = <4>;
1101 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1102 bias-disable;
1103 drive-strength = <4>;
1106 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1107 bias-pull-down;
1108 drive-strength = <4>;
1111 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1112 bias-disable;
1113 drive-strength = <8>;
1116 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1117 bias-pull-up;
1118 drive-strength = <8>;
1121 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1122 bias-disable;
1123 drive-strength = <12>;
1126 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1127 bias-pull-up;
1128 drive-strength = <12>;
1131 pcfg_output_high: pcfg-output-high {
1132 output-high;
1135 pcfg_output_low: pcfg-output-low {
1136 output-low;
1139 pcfg_input_high: pcfg-input-high {
1140 bias-pull-up;
1141 input-enable;
1144 pcfg_input: pcfg-input {
1145 input-enable;
1149 i2c0_xfer: i2c0-xfer {
1156 i2c1_xfer: i2c1-xfer {
1163 i2c2_xfer: i2c2-xfer {
1170 i2c3_xfer: i2c3-xfer {
1174 i2c3_pins: i2c3-pins {
1182 hdmii2c_xfer: hdmii2c-xfer {
1188 pdm-0 {
1189 pdmm0_clk: pdmm0-clk {
1193 pdmm0_fsync: pdmm0-fsync {
1197 pdmm0_sdi0: pdmm0-sdi0 {
1201 pdmm0_sdi1: pdmm0-sdi1 {
1205 pdmm0_sdi2: pdmm0-sdi2 {
1209 pdmm0_sdi3: pdmm0-sdi3 {
1213 pdmm0_clk_sleep: pdmm0-clk-sleep {
1218 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1223 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1228 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1233 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1238 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1245 otp_pin: otp-pin {
1249 otp_out: otp-out {
1255 uart0_xfer: uart0-xfer {
1260 uart0_cts: uart0-cts {
1264 uart0_rts: uart0-rts {
1268 uart0_rts_pin: uart0-rts-pin {
1274 uart1_xfer: uart1-xfer {
1279 uart1_cts: uart1-cts {
1283 uart1_rts: uart1-rts {
1287 uart1_rts_pin: uart1-rts-pin {
1292 uart2-0 {
1293 uart2m0_xfer: uart2m0-xfer {
1299 uart2-1 {
1300 uart2m1_xfer: uart2m1-xfer {
1306 spi0-0 {
1307 spi0m0_clk: spi0m0-clk {
1311 spi0m0_cs0: spi0m0-cs0 {
1315 spi0m0_tx: spi0m0-tx {
1319 spi0m0_rx: spi0m0-rx {
1323 spi0m0_cs1: spi0m0-cs1 {
1328 spi0-1 {
1329 spi0m1_clk: spi0m1-clk {
1333 spi0m1_cs0: spi0m1-cs0 {
1337 spi0m1_tx: spi0m1-tx {
1341 spi0m1_rx: spi0m1-rx {
1345 spi0m1_cs1: spi0m1-cs1 {
1350 spi0-2 {
1351 spi0m2_clk: spi0m2-clk {
1355 spi0m2_cs0: spi0m2-cs0 {
1359 spi0m2_tx: spi0m2-tx {
1363 spi0m2_rx: spi0m2-rx {
1369 i2s1_mclk: i2s1-mclk {
1373 i2s1_sclk: i2s1-sclk {
1377 i2s1_lrckrx: i2s1-lrckrx {
1381 i2s1_lrcktx: i2s1-lrcktx {
1385 i2s1_sdi: i2s1-sdi {
1389 i2s1_sdo: i2s1-sdo {
1393 i2s1_sdio1: i2s1-sdio1 {
1397 i2s1_sdio2: i2s1-sdio2 {
1401 i2s1_sdio3: i2s1-sdio3 {
1405 i2s1_sleep: i2s1-sleep {
1419 i2s2-0 {
1420 i2s2m0_mclk: i2s2m0-mclk {
1424 i2s2m0_sclk: i2s2m0-sclk {
1428 i2s2m0_lrckrx: i2s2m0-lrckrx {
1432 i2s2m0_lrcktx: i2s2m0-lrcktx {
1436 i2s2m0_sdi: i2s2m0-sdi {
1440 i2s2m0_sdo: i2s2m0-sdo {
1444 i2s2m0_sleep: i2s2m0-sleep {
1455 i2s2-1 {
1456 i2s2m1_mclk: i2s2m1-mclk {
1460 i2s2m1_sclk: i2s2m1-sclk {
1464 i2s2m1_lrckrx: i2sm1-lrckrx {
1468 i2s2m1_lrcktx: i2s2m1-lrcktx {
1472 i2s2m1_sdi: i2s2m1-sdi {
1476 i2s2m1_sdo: i2s2m1-sdo {
1480 i2s2m1_sleep: i2s2m1-sleep {
1490 spdif-0 {
1491 spdifm0_tx: spdifm0-tx {
1496 spdif-1 {
1497 spdifm1_tx: spdifm1-tx {
1502 spdif-2 {
1503 spdifm2_tx: spdifm2-tx {
1508 sdmmc0-0 {
1509 sdmmc0m0_pwren: sdmmc0m0-pwren {
1513 sdmmc0m0_pin: sdmmc0m0-pin {
1518 sdmmc0-1 {
1519 sdmmc0m1_pwren: sdmmc0m1-pwren {
1523 sdmmc0m1_pin: sdmmc0m1-pin {
1529 sdmmc0_clk: sdmmc0-clk {
1533 sdmmc0_cmd: sdmmc0-cmd {
1537 sdmmc0_dectn: sdmmc0-dectn {
1541 sdmmc0_wrprt: sdmmc0-wrprt {
1545 sdmmc0_bus1: sdmmc0-bus1 {
1549 sdmmc0_bus4: sdmmc0-bus4 {
1556 sdmmc0_pins: sdmmc0-pins {
1570 sdmmc0ext_clk: sdmmc0ext-clk {
1574 sdmmc0ext_cmd: sdmmc0ext-cmd {
1578 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1582 sdmmc0ext_dectn: sdmmc0ext-dectn {
1586 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1590 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1598 sdmmc0ext_pins: sdmmc0ext-pins {
1612 sdmmc1_clk: sdmmc1-clk {
1616 sdmmc1_cmd: sdmmc1-cmd {
1620 sdmmc1_pwren: sdmmc1-pwren {
1624 sdmmc1_wrprt: sdmmc1-wrprt {
1628 sdmmc1_dectn: sdmmc1-dectn {
1632 sdmmc1_bus1: sdmmc1-bus1 {
1636 sdmmc1_bus4: sdmmc1-bus4 {
1643 sdmmc1_pins: sdmmc1-pins {
1658 emmc_clk: emmc-clk {
1662 emmc_cmd: emmc-cmd {
1666 emmc_pwren: emmc-pwren {
1670 emmc_rstnout: emmc-rstnout {
1674 emmc_bus1: emmc-bus1 {
1678 emmc_bus4: emmc-bus4 {
1686 emmc_bus8: emmc-bus8 {
1700 pwm0_pin: pwm0-pin {
1706 pwm1_pin: pwm1-pin {
1712 pwm2_pin: pwm2-pin {
1718 pwmir_pin: pwmir-pin {
1723 gmac-1 {
1724 rgmiim1_pins: rgmiim1-pins {
1773 rmiim1_pins: rmiim1-pins {
1812 fephyled_speed10: fephyled-speed10 {
1816 fephyled_duplex: fephyled-duplex {
1820 fephyled_rxm1: fephyled-rxm1 {
1824 fephyled_txm1: fephyled-txm1 {
1828 fephyled_linkm1: fephyled-linkm1 {
1834 tsadc_int: tsadc-int {
1837 tsadc_pin: tsadc-pin {
1843 hdmi_cec: hdmi-cec {
1847 hdmi_hpd: hdmi-hpd {
1852 cif-0 {
1853 dvp_d2d9_m0:dvp-d2d9-m0 {
1882 cif-1 {
1883 dvp_d2d9_m1:dvp-d2d9-m1 {