Lines Matching +full:rk3288 +full:- +full:dw +full:- +full:mshc
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/rk3308-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
38 #address-cells = <2>;
39 #size-cells = <0>;
43 compatible = "arm,cortex-a35";
45 enable-method = "psci";
47 #cooling-cells = <2>;
48 dynamic-power-coefficient = <90>;
49 operating-points-v2 = <&cpu0_opp_table>;
50 cpu-idle-states = <&CPU_SLEEP>;
51 next-level-cache = <&l2>;
56 compatible = "arm,cortex-a35";
58 enable-method = "psci";
59 operating-points-v2 = <&cpu0_opp_table>;
60 cpu-idle-states = <&CPU_SLEEP>;
61 next-level-cache = <&l2>;
66 compatible = "arm,cortex-a35";
68 enable-method = "psci";
69 operating-points-v2 = <&cpu0_opp_table>;
70 cpu-idle-states = <&CPU_SLEEP>;
71 next-level-cache = <&l2>;
76 compatible = "arm,cortex-a35";
78 enable-method = "psci";
79 operating-points-v2 = <&cpu0_opp_table>;
80 cpu-idle-states = <&CPU_SLEEP>;
81 next-level-cache = <&l2>;
84 idle-states {
85 entry-method = "psci";
87 CPU_SLEEP: cpu-sleep {
88 compatible = "arm,idle-state";
89 local-timer-stop;
90 arm,psci-suspend-param = <0x0010000>;
91 entry-latency-us = <120>;
92 exit-latency-us = <250>;
93 min-residency-us = <900>;
97 l2: l2-cache {
102 cpu0_opp_table: cpu0-opp-table {
103 compatible = "operating-points-v2";
104 opp-shared;
106 opp-408000000 {
107 opp-hz = /bits/ 64 <408000000>;
108 opp-microvolt = <950000 950000 1340000>;
109 clock-latency-ns = <40000>;
110 opp-suspend;
112 opp-600000000 {
113 opp-hz = /bits/ 64 <600000000>;
114 opp-microvolt = <950000 950000 1340000>;
115 clock-latency-ns = <40000>;
117 opp-816000000 {
118 opp-hz = /bits/ 64 <816000000>;
119 opp-microvolt = <1025000 1025000 1340000>;
120 clock-latency-ns = <40000>;
122 opp-1008000000 {
123 opp-hz = /bits/ 64 <1008000000>;
124 opp-microvolt = <1125000 1125000 1340000>;
125 clock-latency-ns = <40000>;
129 arm-pmu {
130 compatible = "arm,cortex-a35-pmu";
135 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
138 mac_clkin: external-mac-clock {
139 compatible = "fixed-clock";
140 clock-frequency = <50000000>;
141 clock-output-names = "mac_clkin";
142 #clock-cells = <0>;
146 compatible = "arm,psci-1.0";
151 compatible = "arm,armv8-timer";
159 compatible = "fixed-clock";
160 #clock-cells = <0>;
161 clock-frequency = <24000000>;
162 clock-output-names = "xin24m";
166 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
169 reboot-mode {
170 compatible = "syscon-reboot-mode";
172 mode-bootloader = <BOOT_BL_DOWNLOAD>;
173 mode-loader = <BOOT_BL_DOWNLOAD>;
174 mode-normal = <BOOT_NORMAL>;
175 mode-recovery = <BOOT_RECOVERY>;
176 mode-fastboot = <BOOT_FASTBOOT>;
181 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
183 #address-cells = <1>;
184 #size-cells = <1>;
187 compatible = "rockchip,rk3308-usb2phy";
189 assigned-clocks = <&cru USB480M>;
190 assigned-clock-parents = <&u2phy>;
192 clock-names = "phyclk";
193 clock-output-names = "usb480m_phy";
194 #clock-cells = <0>;
197 u2phy_otg: otg-port {
201 interrupt-names = "otg-bvalid", "otg-id",
203 #phy-cells = <0>;
207 u2phy_host: host-port {
209 interrupt-names = "linestate";
210 #phy-cells = <0>;
217 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
219 #address-cells = <1>;
220 #size-cells = <1>;
224 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
226 #address-cells = <1>;
227 #size-cells = <1>;
231 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
234 clock-names = "i2c", "pclk";
236 pinctrl-names = "default";
237 pinctrl-0 = <&i2c0_xfer>;
238 #address-cells = <1>;
239 #size-cells = <0>;
244 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
247 clock-names = "i2c", "pclk";
249 pinctrl-names = "default";
250 pinctrl-0 = <&i2c1_xfer>;
251 #address-cells = <1>;
252 #size-cells = <0>;
257 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
260 clock-names = "i2c", "pclk";
262 pinctrl-names = "default";
263 pinctrl-0 = <&i2c2_xfer>;
264 #address-cells = <1>;
265 #size-cells = <0>;
270 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
273 clock-names = "i2c", "pclk";
275 pinctrl-names = "default";
276 pinctrl-0 = <&i2c3m0_xfer>;
277 #address-cells = <1>;
278 #size-cells = <0>;
283 compatible = "rockchip,rk3308-wdt", "snps,dw-wdt";
291 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
295 clock-names = "baudclk", "apb_pclk";
296 reg-shift = <2>;
297 reg-io-width = <4>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
304 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
308 clock-names = "baudclk", "apb_pclk";
309 reg-shift = <2>;
310 reg-io-width = <4>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
317 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
321 clock-names = "baudclk", "apb_pclk";
322 reg-shift = <2>;
323 reg-io-width = <4>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&uart2m0_xfer>;
330 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
334 clock-names = "baudclk", "apb_pclk";
335 reg-shift = <2>;
336 reg-io-width = <4>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&uart3_xfer>;
343 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
347 clock-names = "baudclk", "apb_pclk";
348 reg-shift = <2>;
349 reg-io-width = <4>;
350 pinctrl-names = "default";
351 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
356 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
359 #address-cells = <1>;
360 #size-cells = <0>;
362 clock-names = "spiclk", "apb_pclk";
364 dma-names = "tx", "rx";
365 pinctrl-names = "default";
366 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
371 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
374 #address-cells = <1>;
375 #size-cells = <0>;
377 clock-names = "spiclk", "apb_pclk";
379 dma-names = "tx", "rx";
380 pinctrl-names = "default";
381 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
386 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
389 #address-cells = <1>;
390 #size-cells = <0>;
392 clock-names = "spiclk", "apb_pclk";
394 dma-names = "tx", "rx";
395 pinctrl-names = "default";
396 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
401 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
404 clock-names = "pwm", "pclk";
405 pinctrl-names = "default";
406 pinctrl-0 = <&pwm8_pin>;
407 #pwm-cells = <3>;
412 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
415 clock-names = "pwm", "pclk";
416 pinctrl-names = "default";
417 pinctrl-0 = <&pwm9_pin>;
418 #pwm-cells = <3>;
423 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
426 clock-names = "pwm", "pclk";
427 pinctrl-names = "default";
428 pinctrl-0 = <&pwm10_pin>;
429 #pwm-cells = <3>;
434 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
437 clock-names = "pwm", "pclk";
438 pinctrl-names = "default";
439 pinctrl-0 = <&pwm11_pin>;
440 #pwm-cells = <3>;
445 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
448 clock-names = "pwm", "pclk";
449 pinctrl-names = "default";
450 pinctrl-0 = <&pwm4_pin>;
451 #pwm-cells = <3>;
456 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
459 clock-names = "pwm", "pclk";
460 pinctrl-names = "default";
461 pinctrl-0 = <&pwm5_pin>;
462 #pwm-cells = <3>;
467 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
470 clock-names = "pwm", "pclk";
471 pinctrl-names = "default";
472 pinctrl-0 = <&pwm6_pin>;
473 #pwm-cells = <3>;
478 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
481 clock-names = "pwm", "pclk";
482 pinctrl-names = "default";
483 pinctrl-0 = <&pwm7_pin>;
484 #pwm-cells = <3>;
489 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
492 clock-names = "pwm", "pclk";
493 pinctrl-names = "default";
494 pinctrl-0 = <&pwm0_pin>;
495 #pwm-cells = <3>;
500 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
503 clock-names = "pwm", "pclk";
504 pinctrl-names = "default";
505 pinctrl-0 = <&pwm1_pin>;
506 #pwm-cells = <3>;
511 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
514 clock-names = "pwm", "pclk";
515 pinctrl-names = "default";
516 pinctrl-0 = <&pwm2_pin>;
517 #pwm-cells = <3>;
522 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
525 clock-names = "pwm", "pclk";
526 pinctrl-names = "default";
527 pinctrl-0 = <&pwm3_pin>;
528 #pwm-cells = <3>;
533 compatible = "rockchip,rk3288-timer";
537 clock-names = "pclk", "timer";
541 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
545 clock-names = "saradc", "apb_pclk";
546 #io-channel-cells = <1>;
548 reset-names = "saradc-apb";
552 dmac0: dma-controller@ff2c0000 {
557 arm,pl330-periph-burst;
559 clock-names = "apb_pclk";
560 #dma-cells = <1>;
563 dmac1: dma-controller@ff2d0000 {
568 arm,pl330-periph-burst;
570 clock-names = "apb_pclk";
571 #dma-cells = <1>;
575 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
579 clock-names = "i2s_clk", "i2s_hclk";
581 dma-names = "tx", "rx";
583 reset-names = "reset-m", "reset-h";
584 pinctrl-names = "default";
585 pinctrl-0 = <&i2s_2ch_0_sclk
593 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
597 clock-names = "i2s_clk", "i2s_hclk";
599 dma-names = "rx";
601 reset-names = "reset-m", "reset-h";
605 spdif_tx: spdif-tx@ff3a0000 {
606 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif";
610 clock-names = "mclk", "hclk";
612 dma-names = "tx";
613 pinctrl-names = "default";
614 pinctrl-0 = <&spdif_out>;
619 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
624 clock-names = "otg";
626 g-np-tx-fifo-size = <16>;
627 g-rx-fifo-size = <280>;
628 g-tx-fifo-size = <256 128 128 64 32 16>;
630 phy-names = "usb2-phy";
635 compatible = "generic-ehci";
640 phy-names = "usb";
645 compatible = "generic-ohci";
650 phy-names = "usb";
655 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
658 bus-width = <4>;
661 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
662 fifo-depth = <0x100>;
663 max-frequency = <150000000>;
664 pinctrl-names = "default";
665 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
670 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
673 bus-width = <8>;
676 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
677 fifo-depth = <0x100>;
678 max-frequency = <150000000>;
683 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
686 bus-width = <4>;
689 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
690 fifo-depth = <0x100>;
691 max-frequency = <150000000>;
692 pinctrl-names = "default";
693 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
697 nfc: nand-controller@ff4b0000 {
698 compatible = "rockchip,rk3308-nfc",
699 "rockchip,rv1108-nfc";
703 clock-names = "ahb", "nfc";
704 assigned-clocks = <&cru SCLK_NANDC>;
705 assigned-clock-rates = <150000000>;
706 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
708 pinctrl-names = "default";
713 compatible = "rockchip,rk3308-gmac";
716 interrupt-names = "macirq";
721 clock-names = "stmmaceth", "mac_clk_rx",
725 phy-mode = "rmii";
726 pinctrl-names = "default";
727 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
729 reset-names = "stmmaceth";
734 cru: clock-controller@ff500000 {
735 compatible = "rockchip,rk3308-cru";
737 #clock-cells = <1>;
738 #reset-cells = <1>;
741 assigned-clocks = <&cru SCLK_RTC32K>;
742 assigned-clock-rates = <32768>;
745 gic: interrupt-controller@ff580000 {
746 compatible = "arm,gic-400";
752 #interrupt-cells = <3>;
753 interrupt-controller;
754 #address-cells = <0>;
758 compatible = "mmio-sram";
761 #address-cells = <1>;
762 #size-cells = <1>;
765 ddr-sram@0 {
770 vad_sram: vad-sram@8000 {
776 compatible = "rockchip,rk3308-pinctrl";
778 #address-cells = <2>;
779 #size-cells = <2>;
783 compatible = "rockchip,gpio-bank";
787 gpio-controller;
788 #gpio-cells = <2>;
789 interrupt-controller;
790 #interrupt-cells = <2>;
794 compatible = "rockchip,gpio-bank";
798 gpio-controller;
799 #gpio-cells = <2>;
800 interrupt-controller;
801 #interrupt-cells = <2>;
805 compatible = "rockchip,gpio-bank";
809 gpio-controller;
810 #gpio-cells = <2>;
811 interrupt-controller;
812 #interrupt-cells = <2>;
816 compatible = "rockchip,gpio-bank";
820 gpio-controller;
821 #gpio-cells = <2>;
822 interrupt-controller;
823 #interrupt-cells = <2>;
827 compatible = "rockchip,gpio-bank";
831 gpio-controller;
832 #gpio-cells = <2>;
833 interrupt-controller;
834 #interrupt-cells = <2>;
837 pcfg_pull_up: pcfg-pull-up {
838 bias-pull-up;
841 pcfg_pull_down: pcfg-pull-down {
842 bias-pull-down;
845 pcfg_pull_none: pcfg-pull-none {
846 bias-disable;
849 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
850 bias-disable;
851 drive-strength = <2>;
854 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
855 bias-pull-up;
856 drive-strength = <2>;
859 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
860 bias-pull-up;
861 drive-strength = <4>;
864 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
865 bias-disable;
866 drive-strength = <4>;
869 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
870 bias-pull-down;
871 drive-strength = <4>;
874 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
875 bias-disable;
876 drive-strength = <8>;
879 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
880 bias-pull-up;
881 drive-strength = <8>;
884 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
885 bias-disable;
886 drive-strength = <12>;
889 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
890 bias-pull-up;
891 drive-strength = <12>;
894 pcfg_pull_none_smt: pcfg-pull-none-smt {
895 bias-disable;
896 input-schmitt-enable;
899 pcfg_output_high: pcfg-output-high {
900 output-high;
903 pcfg_output_low: pcfg-output-low {
904 output-low;
907 pcfg_input_high: pcfg-input-high {
908 bias-pull-up;
909 input-enable;
912 pcfg_input: pcfg-input {
913 input-enable;
917 emmc_clk: emmc-clk {
922 emmc_cmd: emmc-cmd {
927 emmc_pwren: emmc-pwren {
932 emmc_rstn: emmc-rstn {
937 emmc_bus1: emmc-bus1 {
942 emmc_bus4: emmc-bus4 {
950 emmc_bus8: emmc-bus8 {
964 flash_csn0: flash-csn0 {
969 flash_rdy: flash-rdy {
974 flash_ale: flash-ale {
979 flash_cle: flash-cle {
984 flash_wrn: flash-wrn {
989 flash_rdn: flash-rdn {
994 flash_bus8: flash-bus8 {
1008 rmii_pins: rmii-pins {
1030 mac_refclk_12ma: mac-refclk-12ma {
1035 mac_refclk: mac-refclk {
1041 gmac-m1 {
1042 rmiim1_pins: rmiim1-pins {
1064 macm1_refclk_12ma: macm1-refclk-12ma {
1069 macm1_refclk: macm1-refclk {
1076 i2c0_xfer: i2c0-xfer {
1084 i2c1_xfer: i2c1-xfer {
1092 i2c2_xfer: i2c2-xfer {
1099 i2c3-m0 {
1100 i2c3m0_xfer: i2c3m0-xfer {
1107 i2c3-m1 {
1108 i2c3m1_xfer: i2c3m1-xfer {
1115 i2c3-m2 {
1116 i2c3m2_xfer: i2c3m2-xfer {
1124 i2s_2ch_0_mclk: i2s-2ch-0-mclk {
1129 i2s_2ch_0_sclk: i2s-2ch-0-sclk {
1134 i2s_2ch_0_lrck: i2s-2ch-0-lrck {
1139 i2s_2ch_0_sdo: i2s-2ch-0-sdo {
1144 i2s_2ch_0_sdi: i2s-2ch-0-sdi {
1151 i2s_8ch_0_mclk: i2s-8ch-0-mclk {
1156 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
1161 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
1166 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
1171 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
1176 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
1181 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
1186 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
1191 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
1196 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
1201 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
1206 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
1211 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
1218 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
1223 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
1228 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
1233 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
1238 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
1243 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
1248 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 {
1253 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 {
1258 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 {
1263 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 {
1270 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
1275 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
1280 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
1285 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
1290 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
1295 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
1300 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 {
1305 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 {
1310 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 {
1315 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 {
1322 pdm_m0_clk: pdm-m0-clk {
1327 pdm_m0_sdi0: pdm-m0-sdi0 {
1332 pdm_m0_sdi1: pdm-m0-sdi1 {
1337 pdm_m0_sdi2: pdm-m0-sdi2 {
1342 pdm_m0_sdi3: pdm-m0-sdi3 {
1349 pdm_m1_clk: pdm-m1-clk {
1354 pdm_m1_sdi0: pdm-m1-sdi0 {
1359 pdm_m1_sdi1: pdm-m1-sdi1 {
1364 pdm_m1_sdi2: pdm-m1-sdi2 {
1369 pdm_m1_sdi3: pdm-m1-sdi3 {
1376 pdm_m2_clkm: pdm-m2-clkm {
1381 pdm_m2_clk: pdm-m2-clk {
1386 pdm_m2_sdi0: pdm-m2-sdi0 {
1391 pdm_m2_sdi1: pdm-m2-sdi1 {
1396 pdm_m2_sdi2: pdm-m2-sdi2 {
1401 pdm_m2_sdi3: pdm-m2-sdi3 {
1408 pwm0_pin: pwm0-pin {
1413 pwm0_pin_pull_down: pwm0-pin-pull-down {
1420 pwm1_pin: pwm1-pin {
1425 pwm1_pin_pull_down: pwm1-pin-pull-down {
1432 pwm2_pin: pwm2-pin {
1437 pwm2_pin_pull_down: pwm2-pin-pull-down {
1444 pwm3_pin: pwm3-pin {
1449 pwm3_pin_pull_down: pwm3-pin-pull-down {
1456 pwm4_pin: pwm4-pin {
1461 pwm4_pin_pull_down: pwm4-pin-pull-down {
1468 pwm5_pin: pwm5-pin {
1473 pwm5_pin_pull_down: pwm5-pin-pull-down {
1480 pwm6_pin: pwm6-pin {
1485 pwm6_pin_pull_down: pwm6-pin-pull-down {
1492 pwm7_pin: pwm7-pin {
1497 pwm7_pin_pull_down: pwm7-pin-pull-down {
1504 pwm8_pin: pwm8-pin {
1509 pwm8_pin_pull_down: pwm8-pin-pull-down {
1516 pwm9_pin: pwm9-pin {
1521 pwm9_pin_pull_down: pwm9-pin-pull-down {
1528 pwm10_pin: pwm10-pin {
1533 pwm10_pin_pull_down: pwm10-pin-pull-down {
1540 pwm11_pin: pwm11-pin {
1545 pwm11_pin_pull_down: pwm11-pin-pull-down {
1552 rtc_32k: rtc-32k {
1559 sdmmc_clk: sdmmc-clk {
1564 sdmmc_cmd: sdmmc-cmd {
1569 sdmmc_det: sdmmc-det {
1574 sdmmc_pwren: sdmmc-pwren {
1579 sdmmc_bus1: sdmmc-bus1 {
1584 sdmmc_bus4: sdmmc-bus4 {
1594 sdio_clk: sdio-clk {
1599 sdio_cmd: sdio-cmd {
1604 sdio_pwren: sdio-pwren {
1609 sdio_wrpt: sdio-wrpt {
1614 sdio_intn: sdio-intn {
1619 sdio_bus1: sdio-bus1 {
1624 sdio_bus4: sdio-bus4 {
1634 spdif_in: spdif-in {
1641 spdif_out: spdif-out {
1648 spi0_clk: spi0-clk {
1653 spi0_csn0: spi0-csn0 {
1658 spi0_miso: spi0-miso {
1663 spi0_mosi: spi0-mosi {
1670 spi1_clk: spi1-clk {
1675 spi1_csn0: spi1-csn0 {
1680 spi1_miso: spi1-miso {
1685 spi1_mosi: spi1-mosi {
1691 spi1-m1 {
1692 spi1m1_miso: spi1m1-miso {
1697 spi1m1_mosi: spi1m1-mosi {
1702 spi1m1_clk: spi1m1-clk {
1707 spi1m1_csn0: spi1m1-csn0 {
1714 spi2_clk: spi2-clk {
1719 spi2_csn0: spi2-csn0 {
1724 spi2_miso: spi2-miso {
1729 spi2_mosi: spi2-mosi {
1736 tsadc_otp_pin: tsadc-otp-pin {
1741 tsadc_otp_out: tsadc-otp-out {
1748 uart0_xfer: uart0-xfer {
1754 uart0_cts: uart0-cts {
1759 uart0_rts: uart0-rts {
1764 uart0_rts_pin: uart0-rts-pin {
1771 uart1_xfer: uart1-xfer {
1777 uart1_cts: uart1-cts {
1782 uart1_rts: uart1-rts {
1788 uart2-m0 {
1789 uart2m0_xfer: uart2m0-xfer {
1796 uart2-m1 {
1797 uart2m1_xfer: uart2m1-xfer {
1805 uart3_xfer: uart3-xfer {
1812 uart3-m1 {
1813 uart3m1_xfer: uart3m1-xfer {
1821 uart4_xfer: uart4-xfer {
1827 uart4_cts: uart4-cts {
1832 uart4_rts: uart4-rts {
1837 uart4_rts_pin: uart4-rts-pin {