Lines Matching +full:rk3288 +full:- +full:dw +full:- +full:mshc
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
39 #address-cells = <2>;
40 #size-cells = <0>;
44 compatible = "arm,cortex-a35";
46 enable-method = "psci";
48 #cooling-cells = <2>;
49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
50 dynamic-power-coefficient = <90>;
51 operating-points-v2 = <&cpu0_opp_table>;
56 compatible = "arm,cortex-a35";
58 enable-method = "psci";
60 #cooling-cells = <2>;
61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
62 dynamic-power-coefficient = <90>;
63 operating-points-v2 = <&cpu0_opp_table>;
68 compatible = "arm,cortex-a35";
70 enable-method = "psci";
72 #cooling-cells = <2>;
73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
74 dynamic-power-coefficient = <90>;
75 operating-points-v2 = <&cpu0_opp_table>;
80 compatible = "arm,cortex-a35";
82 enable-method = "psci";
84 #cooling-cells = <2>;
85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
86 dynamic-power-coefficient = <90>;
87 operating-points-v2 = <&cpu0_opp_table>;
90 idle-states {
91 entry-method = "psci";
93 CPU_SLEEP: cpu-sleep {
94 compatible = "arm,idle-state";
95 local-timer-stop;
96 arm,psci-suspend-param = <0x0010000>;
97 entry-latency-us = <120>;
98 exit-latency-us = <250>;
99 min-residency-us = <900>;
102 CLUSTER_SLEEP: cluster-sleep {
103 compatible = "arm,idle-state";
104 local-timer-stop;
105 arm,psci-suspend-param = <0x1010000>;
106 entry-latency-us = <400>;
107 exit-latency-us = <500>;
108 min-residency-us = <2000>;
113 cpu0_opp_table: cpu0-opp-table {
114 compatible = "operating-points-v2";
115 opp-shared;
117 opp-600000000 {
118 opp-hz = /bits/ 64 <600000000>;
119 opp-microvolt = <950000 950000 1350000>;
120 clock-latency-ns = <40000>;
121 opp-suspend;
123 opp-816000000 {
124 opp-hz = /bits/ 64 <816000000>;
125 opp-microvolt = <1050000 1050000 1350000>;
126 clock-latency-ns = <40000>;
128 opp-1008000000 {
129 opp-hz = /bits/ 64 <1008000000>;
130 opp-microvolt = <1175000 1175000 1350000>;
131 clock-latency-ns = <40000>;
133 opp-1200000000 {
134 opp-hz = /bits/ 64 <1200000000>;
135 opp-microvolt = <1300000 1300000 1350000>;
136 clock-latency-ns = <40000>;
138 opp-1296000000 {
139 opp-hz = /bits/ 64 <1296000000>;
140 opp-microvolt = <1350000 1350000 1350000>;
141 clock-latency-ns = <40000>;
145 arm-pmu {
146 compatible = "arm,cortex-a35-pmu";
151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
154 display_subsystem: display-subsystem {
155 compatible = "rockchip,display-subsystem";
160 gmac_clkin: external-gmac-clock {
161 compatible = "fixed-clock";
162 clock-frequency = <50000000>;
163 clock-output-names = "gmac_clkin";
164 #clock-cells = <0>;
168 compatible = "arm,psci-1.0";
173 compatible = "arm,armv8-timer";
180 thermal_zones: thermal-zones {
181 soc_thermal: soc-thermal {
182 polling-delay-passive = <20>;
183 polling-delay = <1000>;
184 sustainable-power = <750>;
185 thermal-sensors = <&tsadc 0>;
188 threshold: trip-point-0 {
194 target: trip-point-1 {
200 soc_crit: soc-crit {
207 cooling-maps {
210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
216 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
222 gpu_thermal: gpu-thermal {
223 polling-delay-passive = <100>; /* milliseconds */
224 polling-delay = <1000>; /* milliseconds */
225 thermal-sensors = <&tsadc 1>;
230 compatible = "fixed-clock";
231 #clock-cells = <0>;
232 clock-frequency = <24000000>;
233 clock-output-names = "xin24m";
236 pmu: power-management@ff000000 {
237 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
240 power: power-controller {
241 compatible = "rockchip,px30-power-controller";
242 #power-domain-cells = <1>;
243 #address-cells = <1>;
244 #size-cells = <0>;
247 power-domain@PX30_PD_USB {
253 #power-domain-cells = <0>;
255 power-domain@PX30_PD_SDCARD {
260 #power-domain-cells = <0>;
262 power-domain@PX30_PD_GMAC {
269 #power-domain-cells = <0>;
271 power-domain@PX30_PD_MMC_NAND {
283 #power-domain-cells = <0>;
285 power-domain@PX30_PD_VPU {
291 #power-domain-cells = <0>;
293 power-domain@PX30_PD_VO {
308 #power-domain-cells = <0>;
310 power-domain@PX30_PD_VI {
320 #power-domain-cells = <0>;
322 power-domain@PX30_PD_GPU {
326 #power-domain-cells = <0>;
332 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
334 #address-cells = <1>;
335 #size-cells = <1>;
337 pmu_io_domains: io-domains {
338 compatible = "rockchip,px30-pmu-io-voltage-domain";
342 reboot-mode {
343 compatible = "syscon-reboot-mode";
345 mode-bootloader = <BOOT_BL_DOWNLOAD>;
346 mode-fastboot = <BOOT_FASTBOOT>;
347 mode-loader = <BOOT_BL_DOWNLOAD>;
348 mode-normal = <BOOT_NORMAL>;
349 mode-recovery = <BOOT_RECOVERY>;
354 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
358 clock-names = "baudclk", "apb_pclk";
360 dma-names = "tx", "rx";
361 reg-shift = <2>;
362 reg-io-width = <4>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
369 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
373 clock-names = "i2s_clk", "i2s_hclk";
375 dma-names = "tx", "rx";
376 pinctrl-names = "default";
377 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
379 #sound-dai-cells = <0>;
384 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
388 clock-names = "i2s_clk", "i2s_hclk";
390 dma-names = "tx", "rx";
391 pinctrl-names = "default";
392 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
394 #sound-dai-cells = <0>;
398 gic: interrupt-controller@ff131000 {
399 compatible = "arm,gic-400";
400 #interrupt-cells = <3>;
401 #address-cells = <0>;
402 interrupt-controller;
412 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
414 #address-cells = <1>;
415 #size-cells = <1>;
417 io_domains: io-domains {
418 compatible = "rockchip,px30-io-voltage-domain";
423 compatible = "rockchip,px30-lvds";
425 phy-names = "dphy";
431 #address-cells = <1>;
432 #size-cells = <0>;
436 #address-cells = <1>;
437 #size-cells = <0>;
441 remote-endpoint = <&vopb_out_lvds>;
446 remote-endpoint = <&vopl_out_lvds>;
454 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
458 clock-names = "baudclk", "apb_pclk";
460 dma-names = "tx", "rx";
461 reg-shift = <2>;
462 reg-io-width = <4>;
463 pinctrl-names = "default";
464 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
469 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
473 clock-names = "baudclk", "apb_pclk";
475 dma-names = "tx", "rx";
476 reg-shift = <2>;
477 reg-io-width = <4>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&uart2m0_xfer>;
484 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
488 clock-names = "baudclk", "apb_pclk";
490 dma-names = "tx", "rx";
491 reg-shift = <2>;
492 reg-io-width = <4>;
493 pinctrl-names = "default";
494 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
499 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
503 clock-names = "baudclk", "apb_pclk";
505 dma-names = "tx", "rx";
506 reg-shift = <2>;
507 reg-io-width = <4>;
508 pinctrl-names = "default";
509 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
514 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
518 clock-names = "baudclk", "apb_pclk";
520 dma-names = "tx", "rx";
521 reg-shift = <2>;
522 reg-io-width = <4>;
523 pinctrl-names = "default";
524 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
529 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
532 clock-names = "i2c", "pclk";
534 pinctrl-names = "default";
535 pinctrl-0 = <&i2c0_xfer>;
536 #address-cells = <1>;
537 #size-cells = <0>;
542 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
545 clock-names = "i2c", "pclk";
547 pinctrl-names = "default";
548 pinctrl-0 = <&i2c1_xfer>;
549 #address-cells = <1>;
550 #size-cells = <0>;
555 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
558 clock-names = "i2c", "pclk";
560 pinctrl-names = "default";
561 pinctrl-0 = <&i2c2_xfer>;
562 #address-cells = <1>;
563 #size-cells = <0>;
568 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
571 clock-names = "i2c", "pclk";
573 pinctrl-names = "default";
574 pinctrl-0 = <&i2c3_xfer>;
575 #address-cells = <1>;
576 #size-cells = <0>;
581 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
585 clock-names = "spiclk", "apb_pclk";
587 dma-names = "tx", "rx";
588 pinctrl-names = "default";
589 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
590 #address-cells = <1>;
591 #size-cells = <0>;
596 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
600 clock-names = "spiclk", "apb_pclk";
602 dma-names = "tx", "rx";
603 pinctrl-names = "default";
604 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
605 #address-cells = <1>;
606 #size-cells = <0>;
611 compatible = "rockchip,px30-wdt", "snps,dw-wdt";
619 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
622 clock-names = "pwm", "pclk";
623 pinctrl-names = "default";
624 pinctrl-0 = <&pwm0_pin>;
625 #pwm-cells = <3>;
630 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
633 clock-names = "pwm", "pclk";
634 pinctrl-names = "default";
635 pinctrl-0 = <&pwm1_pin>;
636 #pwm-cells = <3>;
641 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
644 clock-names = "pwm", "pclk";
645 pinctrl-names = "default";
646 pinctrl-0 = <&pwm2_pin>;
647 #pwm-cells = <3>;
652 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
655 clock-names = "pwm", "pclk";
656 pinctrl-names = "default";
657 pinctrl-0 = <&pwm3_pin>;
658 #pwm-cells = <3>;
663 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
666 clock-names = "pwm", "pclk";
667 pinctrl-names = "default";
668 pinctrl-0 = <&pwm4_pin>;
669 #pwm-cells = <3>;
674 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
677 clock-names = "pwm", "pclk";
678 pinctrl-names = "default";
679 pinctrl-0 = <&pwm5_pin>;
680 #pwm-cells = <3>;
685 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
688 clock-names = "pwm", "pclk";
689 pinctrl-names = "default";
690 pinctrl-0 = <&pwm6_pin>;
691 #pwm-cells = <3>;
696 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
699 clock-names = "pwm", "pclk";
700 pinctrl-names = "default";
701 pinctrl-0 = <&pwm7_pin>;
702 #pwm-cells = <3>;
707 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
711 clock-names = "pclk", "timer";
719 arm,pl330-periph-burst;
721 clock-names = "apb_pclk";
722 #dma-cells = <1>;
726 compatible = "rockchip,px30-tsadc";
729 assigned-clocks = <&cru SCLK_TSADC>;
730 assigned-clock-rates = <50000>;
732 clock-names = "tsadc", "apb_pclk";
734 reset-names = "tsadc-apb";
736 rockchip,hw-tshut-temp = <120000>;
737 pinctrl-names = "init", "default", "sleep";
738 pinctrl-0 = <&tsadc_otp_pin>;
739 pinctrl-1 = <&tsadc_otp_out>;
740 pinctrl-2 = <&tsadc_otp_pin>;
741 #thermal-sensor-cells = <1>;
746 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
749 #io-channel-cells = <1>;
751 clock-names = "saradc", "apb_pclk";
753 reset-names = "saradc-apb";
758 compatible = "rockchip,px30-otp";
762 clock-names = "otp", "apb_pclk", "phy";
764 reset-names = "phy";
765 #address-cells = <1>;
766 #size-cells = <1>;
772 cpu_leakage: cpu-leakage@17 {
781 cru: clock-controller@ff2b0000 {
782 compatible = "rockchip,px30-cru";
785 clock-names = "xin24m", "gpll";
787 #clock-cells = <1>;
788 #reset-cells = <1>;
790 assigned-clocks = <&cru PLL_NPLL>,
795 assigned-clock-rates = <1188000000>,
801 pmucru: clock-controller@ff2bc000 {
802 compatible = "rockchip,px30-pmucru";
805 clock-names = "xin24m";
807 #clock-cells = <1>;
808 #reset-cells = <1>;
810 assigned-clocks =
813 assigned-clock-rates =
819 compatible = "rockchip,px30-usb2phy-grf", "syscon",
820 "simple-mfd";
822 #address-cells = <1>;
823 #size-cells = <1>;
826 compatible = "rockchip,px30-usb2phy";
829 clock-names = "phyclk";
830 #clock-cells = <0>;
831 assigned-clocks = <&cru USB480M>;
832 assigned-clock-parents = <&u2phy>;
833 clock-output-names = "usb480m_phy";
836 u2phy_host: host-port {
837 #phy-cells = <0>;
839 interrupt-names = "linestate";
843 u2phy_otg: otg-port {
844 #phy-cells = <0>;
848 interrupt-names = "otg-bvalid", "otg-id",
856 compatible = "rockchip,px30-dsi-dphy";
859 clock-names = "ref", "pclk";
861 reset-names = "apb";
862 #phy-cells = <0>;
863 power-domains = <&power PX30_PD_VO>;
868 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
873 clock-names = "otg";
875 g-np-tx-fifo-size = <16>;
876 g-rx-fifo-size = <280>;
877 g-tx-fifo-size = <256 128 128 64 32 16>;
879 phy-names = "usb2-phy";
880 power-domains = <&power PX30_PD_USB>;
885 compatible = "generic-ehci";
890 phy-names = "usb";
891 power-domains = <&power PX30_PD_USB>;
896 compatible = "generic-ohci";
901 phy-names = "usb";
902 power-domains = <&power PX30_PD_USB>;
907 compatible = "rockchip,px30-gmac";
910 interrupt-names = "macirq";
915 clock-names = "stmmaceth", "mac_clk_rx",
920 phy-mode = "rmii";
921 pinctrl-names = "default";
922 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
923 power-domains = <&power PX30_PD_GMAC>;
925 reset-names = "stmmaceth";
930 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
935 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
936 bus-width = <4>;
937 fifo-depth = <0x100>;
938 max-frequency = <150000000>;
939 pinctrl-names = "default";
940 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
941 power-domains = <&power PX30_PD_SDCARD>;
946 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
951 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
952 bus-width = <4>;
953 fifo-depth = <0x100>;
954 max-frequency = <150000000>;
955 pinctrl-names = "default";
956 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
957 power-domains = <&power PX30_PD_MMC_NAND>;
962 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
967 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
968 bus-width = <8>;
969 fifo-depth = <0x100>;
970 max-frequency = <150000000>;
971 pinctrl-names = "default";
972 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
973 power-domains = <&power PX30_PD_MMC_NAND>;
977 nfc: nand-controller@ff3b0000 {
978 compatible = "rockchip,px30-nfc";
982 clock-names = "ahb", "nfc";
983 assigned-clocks = <&cru SCLK_NANDC>;
984 assigned-clock-rates = <150000000>;
985 pinctrl-names = "default";
986 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
988 power-domains = <&power PX30_PD_MMC_NAND>;
992 gpu_opp_table: opp-table2 {
993 compatible = "operating-points-v2";
995 opp-200000000 {
996 opp-hz = /bits/ 64 <200000000>;
997 opp-microvolt = <950000>;
999 opp-300000000 {
1000 opp-hz = /bits/ 64 <300000000>;
1001 opp-microvolt = <975000>;
1003 opp-400000000 {
1004 opp-hz = /bits/ 64 <400000000>;
1005 opp-microvolt = <1050000>;
1007 opp-480000000 {
1008 opp-hz = /bits/ 64 <480000000>;
1009 opp-microvolt = <1125000>;
1014 compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1019 interrupt-names = "job", "mmu", "gpu";
1021 #cooling-cells = <2>;
1022 power-domains = <&power PX30_PD_GPU>;
1023 operating-points-v2 = <&gpu_opp_table>;
1028 compatible = "rockchip,px30-mipi-dsi";
1032 clock-names = "pclk";
1034 phy-names = "dphy";
1035 power-domains = <&power PX30_PD_VO>;
1037 reset-names = "apb";
1039 #address-cells = <1>;
1040 #size-cells = <0>;
1044 #address-cells = <1>;
1045 #size-cells = <0>;
1049 #address-cells = <1>;
1050 #size-cells = <0>;
1054 remote-endpoint = <&vopb_out_dsi>;
1059 remote-endpoint = <&vopl_out_dsi>;
1066 compatible = "rockchip,px30-vop-big";
1071 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1073 reset-names = "axi", "ahb", "dclk";
1075 power-domains = <&power PX30_PD_VO>;
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1084 remote-endpoint = <&dsi_in_vopb>;
1089 remote-endpoint = <&lvds_vopb_in>;
1099 clock-names = "aclk", "iface";
1100 power-domains = <&power PX30_PD_VO>;
1101 #iommu-cells = <0>;
1106 compatible = "rockchip,px30-vop-lit";
1111 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1113 reset-names = "axi", "ahb", "dclk";
1115 power-domains = <&power PX30_PD_VO>;
1119 #address-cells = <1>;
1120 #size-cells = <0>;
1124 remote-endpoint = <&dsi_in_vopl>;
1129 remote-endpoint = <&lvds_vopl_in>;
1139 clock-names = "aclk", "iface";
1140 power-domains = <&power PX30_PD_VO>;
1141 #iommu-cells = <0>;
1146 compatible = "rockchip,px30-qos", "syscon";
1151 compatible = "rockchip,px30-qos", "syscon";
1156 compatible = "rockchip,px30-qos", "syscon";
1161 compatible = "rockchip,px30-qos", "syscon";
1166 compatible = "rockchip,px30-qos", "syscon";
1171 compatible = "rockchip,px30-qos", "syscon";
1176 compatible = "rockchip,px30-qos", "syscon";
1181 compatible = "rockchip,px30-qos", "syscon";
1186 compatible = "rockchip,px30-qos", "syscon";
1191 compatible = "rockchip,px30-qos", "syscon";
1196 compatible = "rockchip,px30-qos", "syscon";
1201 compatible = "rockchip,px30-qos", "syscon";
1206 compatible = "rockchip,px30-qos", "syscon";
1211 compatible = "rockchip,px30-qos", "syscon";
1216 compatible = "rockchip,px30-qos", "syscon";
1221 compatible = "rockchip,px30-qos", "syscon";
1226 compatible = "rockchip,px30-qos", "syscon";
1231 compatible = "rockchip,px30-qos", "syscon";
1236 compatible = "rockchip,px30-qos", "syscon";
1241 compatible = "rockchip,px30-qos", "syscon";
1246 compatible = "rockchip,px30-pinctrl";
1249 #address-cells = <2>;
1250 #size-cells = <2>;
1254 compatible = "rockchip,gpio-bank";
1258 gpio-controller;
1259 #gpio-cells = <2>;
1261 interrupt-controller;
1262 #interrupt-cells = <2>;
1266 compatible = "rockchip,gpio-bank";
1270 gpio-controller;
1271 #gpio-cells = <2>;
1273 interrupt-controller;
1274 #interrupt-cells = <2>;
1278 compatible = "rockchip,gpio-bank";
1282 gpio-controller;
1283 #gpio-cells = <2>;
1285 interrupt-controller;
1286 #interrupt-cells = <2>;
1290 compatible = "rockchip,gpio-bank";
1294 gpio-controller;
1295 #gpio-cells = <2>;
1297 interrupt-controller;
1298 #interrupt-cells = <2>;
1301 pcfg_pull_up: pcfg-pull-up {
1302 bias-pull-up;
1305 pcfg_pull_down: pcfg-pull-down {
1306 bias-pull-down;
1309 pcfg_pull_none: pcfg-pull-none {
1310 bias-disable;
1313 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1314 bias-disable;
1315 drive-strength = <2>;
1318 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1319 bias-pull-up;
1320 drive-strength = <2>;
1323 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1324 bias-pull-up;
1325 drive-strength = <4>;
1328 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1329 bias-disable;
1330 drive-strength = <4>;
1333 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1334 bias-pull-down;
1335 drive-strength = <4>;
1338 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1339 bias-disable;
1340 drive-strength = <8>;
1343 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1344 bias-pull-up;
1345 drive-strength = <8>;
1348 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1349 bias-disable;
1350 drive-strength = <12>;
1353 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1354 bias-pull-up;
1355 drive-strength = <12>;
1358 pcfg_pull_none_smt: pcfg-pull-none-smt {
1359 bias-disable;
1360 input-schmitt-enable;
1363 pcfg_output_high: pcfg-output-high {
1364 output-high;
1367 pcfg_output_low: pcfg-output-low {
1368 output-low;
1371 pcfg_input_high: pcfg-input-high {
1372 bias-pull-up;
1373 input-enable;
1376 pcfg_input: pcfg-input {
1377 input-enable;
1381 i2c0_xfer: i2c0-xfer {
1389 i2c1_xfer: i2c1-xfer {
1397 i2c2_xfer: i2c2-xfer {
1405 i2c3_xfer: i2c3-xfer {
1413 tsadc_otp_pin: tsadc-otp-pin {
1418 tsadc_otp_out: tsadc-otp-out {
1425 uart0_xfer: uart0-xfer {
1431 uart0_cts: uart0-cts {
1436 uart0_rts: uart0-rts {
1443 uart1_xfer: uart1-xfer {
1449 uart1_cts: uart1-cts {
1454 uart1_rts: uart1-rts {
1460 uart2-m0 {
1461 uart2m0_xfer: uart2m0-xfer {
1468 uart2-m1 {
1469 uart2m1_xfer: uart2m1-xfer {
1476 uart3-m0 {
1477 uart3m0_xfer: uart3m0-xfer {
1483 uart3m0_cts: uart3m0-cts {
1488 uart3m0_rts: uart3m0-rts {
1494 uart3-m1 {
1495 uart3m1_xfer: uart3m1-xfer {
1501 uart3m1_cts: uart3m1-cts {
1506 uart3m1_rts: uart3m1-rts {
1513 uart4_xfer: uart4-xfer {
1519 uart4_cts: uart4-cts {
1524 uart4_rts: uart4-rts {
1531 uart5_xfer: uart5-xfer {
1537 uart5_cts: uart5-cts {
1542 uart5_rts: uart5-rts {
1549 spi0_clk: spi0-clk {
1554 spi0_csn: spi0-csn {
1559 spi0_miso: spi0-miso {
1564 spi0_mosi: spi0-mosi {
1569 spi0_clk_hs: spi0-clk-hs {
1574 spi0_miso_hs: spi0-miso-hs {
1579 spi0_mosi_hs: spi0-mosi-hs {
1586 spi1_clk: spi1-clk {
1591 spi1_csn0: spi1-csn0 {
1596 spi1_csn1: spi1-csn1 {
1601 spi1_miso: spi1-miso {
1606 spi1_mosi: spi1-mosi {
1611 spi1_clk_hs: spi1-clk-hs {
1616 spi1_miso_hs: spi1-miso-hs {
1621 spi1_mosi_hs: spi1-mosi-hs {
1628 pdm_clk0m0: pdm-clk0m0 {
1633 pdm_clk0m1: pdm-clk0m1 {
1638 pdm_clk1: pdm-clk1 {
1643 pdm_sdi0m0: pdm-sdi0m0 {
1648 pdm_sdi0m1: pdm-sdi0m1 {
1653 pdm_sdi1: pdm-sdi1 {
1658 pdm_sdi2: pdm-sdi2 {
1663 pdm_sdi3: pdm-sdi3 {
1668 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1673 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1678 pdm_clk1_sleep: pdm-clk1-sleep {
1683 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1688 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1693 pdm_sdi1_sleep: pdm-sdi1-sleep {
1698 pdm_sdi2_sleep: pdm-sdi2-sleep {
1703 pdm_sdi3_sleep: pdm-sdi3-sleep {
1710 i2s0_8ch_mclk: i2s0-8ch-mclk {
1715 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1720 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1725 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1730 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1735 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1740 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1745 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1750 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1755 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1760 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1765 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1770 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1777 i2s1_2ch_mclk: i2s1-2ch-mclk {
1782 i2s1_2ch_sclk: i2s1-2ch-sclk {
1787 i2s1_2ch_lrck: i2s1-2ch-lrck {
1792 i2s1_2ch_sdi: i2s1-2ch-sdi {
1797 i2s1_2ch_sdo: i2s1-2ch-sdo {
1804 i2s2_2ch_mclk: i2s2-2ch-mclk {
1809 i2s2_2ch_sclk: i2s2-2ch-sclk {
1814 i2s2_2ch_lrck: i2s2-2ch-lrck {
1819 i2s2_2ch_sdi: i2s2-2ch-sdi {
1824 i2s2_2ch_sdo: i2s2-2ch-sdo {
1831 sdmmc_clk: sdmmc-clk {
1836 sdmmc_cmd: sdmmc-cmd {
1841 sdmmc_det: sdmmc-det {
1846 sdmmc_bus1: sdmmc-bus1 {
1851 sdmmc_bus4: sdmmc-bus4 {
1861 sdio_clk: sdio-clk {
1866 sdio_cmd: sdio-cmd {
1871 sdio_bus4: sdio-bus4 {
1881 emmc_clk: emmc-clk {
1886 emmc_cmd: emmc-cmd {
1891 emmc_rstnout: emmc-rstnout {
1896 emmc_bus1: emmc-bus1 {
1901 emmc_bus4: emmc-bus4 {
1909 emmc_bus8: emmc-bus8 {
1923 flash_cs0: flash-cs0 {
1928 flash_rdy: flash-rdy {
1933 flash_dqs: flash-dqs {
1938 flash_ale: flash-ale {
1943 flash_cle: flash-cle {
1948 flash_wrn: flash-wrn {
1953 flash_csl: flash-csl {
1958 flash_rdn: flash-rdn {
1963 flash_bus8: flash-bus8 {
1977 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
1982 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
1987 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
1992 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
1997 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2025 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2047 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2067 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2088 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2103 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2118 pwm0_pin: pwm0-pin {
2125 pwm1_pin: pwm1-pin {
2132 pwm2_pin: pwm2-pin {
2139 pwm3_pin: pwm3-pin {
2146 pwm4_pin: pwm4-pin {
2153 pwm5_pin: pwm5-pin {
2160 pwm6_pin: pwm6-pin {
2167 pwm7_pin: pwm7-pin {
2174 rmii_pins: rmii-pins {
2187 mac_refclk_12ma: mac-refclk-12ma {
2192 mac_refclk: mac-refclk {
2198 cif-m0 {
2199 cif_clkout_m0: cif-clkout-m0 {
2204 dvp_d2d9_m0: dvp-d2d9-m0 {
2220 dvp_d0d1_m0: dvp-d0d1-m0 {
2226 dvp_d10d11_m0:d10-d11-m0 {
2233 cif-m1 {
2234 cif_clkout_m1: cif-clkout-m1 {
2239 dvp_d2d9_m1: dvp-d2d9-m1 {
2255 dvp_d0d1_m1: dvp-d0d1-m1 {
2261 dvp_d10d11_m1:d10-d11-m1 {
2269 isp_prelight: isp-prelight {