Lines Matching +full:gic +full:- +full:v3
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 /* External CAN clock - to be overridden by boards that provide it */
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <0>;
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
28 clock-frequency = <0>;
32 compatible = "arm,psci-1.0", "arm,psci-0.2";
37 #address-cells = <1>;
38 #size-cells = <0>;
40 cpu-map {
52 compatible = "arm,cortex-a55";
55 next-level-cache = <&L3_CA55>;
56 enable-method = "psci";
60 compatible = "arm,cortex-a55";
63 next-level-cache = <&L3_CA55>;
64 enable-method = "psci";
67 L3_CA55: cache-controller-0 {
69 cache-unified;
70 cache-size = <0x40000>;
75 compatible = "simple-bus";
76 interrupt-parent = <&gic>;
77 #address-cells = <2>;
78 #size-cells = <2>;
82 compatible = "renesas,scif-r9a07g044";
90 interrupt-names = "eri", "rxi", "txi",
93 clock-names = "fck";
94 power-domains = <&cpg>;
100 compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
110 interrupt-names = "g_err", "g_recc",
116 clock-names = "fck", "canfd", "can_clk";
117 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
118 assigned-clock-rates = <50000000>;
121 reset-names = "rstp_n", "rstc_n";
122 power-domains = <&cpg>;
134 #address-cells = <1>;
135 #size-cells = <0>;
136 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
146 interrupt-names = "tei", "ri", "ti", "spi", "sti",
149 clock-frequency = <100000>;
151 power-domains = <&cpg>;
156 #address-cells = <1>;
157 #size-cells = <0>;
158 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
168 interrupt-names = "tei", "ri", "ti", "spi", "sti",
171 clock-frequency = <100000>;
173 power-domains = <&cpg>;
178 #address-cells = <1>;
179 #size-cells = <0>;
180 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
190 interrupt-names = "tei", "ri", "ti", "spi", "sti",
193 clock-frequency = <100000>;
195 power-domains = <&cpg>;
200 #address-cells = <1>;
201 #size-cells = <0>;
202 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
212 interrupt-names = "tei", "ri", "ti", "spi", "sti",
215 clock-frequency = <100000>;
217 power-domains = <&cpg>;
222 compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
227 clock-names = "adclk", "pclk";
230 reset-names = "presetn", "adrst-n";
231 power-domains = <&cpg>;
234 #address-cells = <1>;
235 #size-cells = <0>;
263 cpg: clock-controller@11010000 {
264 compatible = "renesas,r9a07g044-cpg";
267 clock-names = "extal";
268 #clock-cells = <2>;
269 #reset-cells = <1>;
270 #power-domain-cells = <0>;
273 sysc: system-controller@11020000 {
274 compatible = "renesas,r9a07g044-sysc";
280 interrupt-names = "lpm_int", "ca55stbydone_int",
285 pinctrl: pin-controller@11030000 {
286 compatible = "renesas,r9a07g044-pinctrl";
288 gpio-controller;
289 #gpio-cells = <2>;
290 gpio-ranges = <&pinctrl 0 0 392>;
292 power-domains = <&cpg>;
298 gic: interrupt-controller@11900000 { label
299 compatible = "arm,gic-v3";
300 #interrupt-cells = <3>;
301 #address-cells = <0>;
302 interrupt-controller;
310 compatible = "arm,armv8-timer";
311 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
312 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
313 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
314 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;