Lines Matching +full:ch3 +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car D3 (R8A77995) SoC
9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/r8a77995-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 * The external audio clocks are configured as 0 Hz fixed frequency
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <0>;
35 /* External CAN clock - to be overridden by boards that provide it */
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <0>;
43 #address-cells = <1>;
44 #size-cells = <0>;
46 a53_0: cpu@0 {
47 compatible = "arm,cortex-a53";
48 reg = <0x0>;
50 power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
51 next-level-cache = <&L2_CA53>;
52 enable-method = "psci";
55 L2_CA53: cache-controller-1 {
57 power-domains = <&sysc R8A77995_PD_CA53_SCU>;
58 cache-unified;
59 cache-level = <2>;
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
67 clock-frequency = <0>;
71 compatible = "arm,cortex-a53-pmu";
72 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
76 compatible = "arm,psci-1.0", "arm,psci-0.2";
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <0>;
87 compatible = "simple-bus";
88 interrupt-parent = <&gic>;
89 #address-cells = <2>;
90 #size-cells = <2>;
94 compatible = "renesas,r8a77995-wdt",
95 "renesas,rcar-gen3-wdt";
96 reg = <0 0xe6020000 0 0x0c>;
98 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
104 compatible = "renesas,gpio-r8a77995",
105 "renesas,rcar-gen3-gpio";
106 reg = <0 0xe6050000 0 0x50>;
108 #gpio-cells = <2>;
109 gpio-controller;
110 gpio-ranges = <&pfc 0 0 9>;
111 #interrupt-cells = <2>;
112 interrupt-controller;
114 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
119 compatible = "renesas,gpio-r8a77995",
120 "renesas,rcar-gen3-gpio";
121 reg = <0 0xe6051000 0 0x50>;
123 #gpio-cells = <2>;
124 gpio-controller;
125 gpio-ranges = <&pfc 0 32 32>;
126 #interrupt-cells = <2>;
127 interrupt-controller;
129 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
134 compatible = "renesas,gpio-r8a77995",
135 "renesas,rcar-gen3-gpio";
136 reg = <0 0xe6052000 0 0x50>;
138 #gpio-cells = <2>;
139 gpio-controller;
140 gpio-ranges = <&pfc 0 64 32>;
141 #interrupt-cells = <2>;
142 interrupt-controller;
144 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
149 compatible = "renesas,gpio-r8a77995",
150 "renesas,rcar-gen3-gpio";
151 reg = <0 0xe6053000 0 0x50>;
153 #gpio-cells = <2>;
154 gpio-controller;
155 gpio-ranges = <&pfc 0 96 10>;
156 #interrupt-cells = <2>;
157 interrupt-controller;
159 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
164 compatible = "renesas,gpio-r8a77995",
165 "renesas,rcar-gen3-gpio";
166 reg = <0 0xe6054000 0 0x50>;
168 #gpio-cells = <2>;
169 gpio-controller;
170 gpio-ranges = <&pfc 0 128 32>;
171 #interrupt-cells = <2>;
172 interrupt-controller;
174 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
179 compatible = "renesas,gpio-r8a77995",
180 "renesas,rcar-gen3-gpio";
181 reg = <0 0xe6055000 0 0x50>;
183 #gpio-cells = <2>;
184 gpio-controller;
185 gpio-ranges = <&pfc 0 160 21>;
186 #interrupt-cells = <2>;
187 interrupt-controller;
189 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
194 compatible = "renesas,gpio-r8a77995",
195 "renesas,rcar-gen3-gpio";
196 reg = <0 0xe6055400 0 0x50>;
198 #gpio-cells = <2>;
199 gpio-controller;
200 gpio-ranges = <&pfc 0 192 14>;
201 #interrupt-cells = <2>;
202 interrupt-controller;
204 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
209 compatible = "renesas,pfc-r8a77995";
210 reg = <0 0xe6060000 0 0x508>;
214 compatible = "renesas,r8a77995-cmt0",
215 "renesas,rcar-gen3-cmt0";
216 reg = <0 0xe60f0000 0 0x1004>;
220 clock-names = "fck";
221 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
227 compatible = "renesas,r8a77995-cmt1",
228 "renesas,rcar-gen3-cmt1";
229 reg = <0 0xe6130000 0 0x1004>;
239 clock-names = "fck";
240 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
246 compatible = "renesas,r8a77995-cmt1",
247 "renesas,rcar-gen3-cmt1";
248 reg = <0 0xe6140000 0 0x1004>;
258 clock-names = "fck";
259 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
265 compatible = "renesas,r8a77995-cmt1",
266 "renesas,rcar-gen3-cmt1";
267 reg = <0 0xe6148000 0 0x1004>;
277 clock-names = "fck";
278 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
283 cpg: clock-controller@e6150000 {
284 compatible = "renesas,r8a77995-cpg-mssr";
285 reg = <0 0xe6150000 0 0x1000>;
287 clock-names = "extal";
288 #clock-cells = <2>;
289 #power-domain-cells = <0>;
290 #reset-cells = <1>;
293 rst: reset-controller@e6160000 {
294 compatible = "renesas,r8a77995-rst";
295 reg = <0 0xe6160000 0 0x0200>;
298 sysc: system-controller@e6180000 {
299 compatible = "renesas,r8a77995-sysc";
300 reg = <0 0xe6180000 0 0x0400>;
301 #power-domain-cells = <1>;
305 compatible = "renesas,thermal-r8a77995";
306 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
311 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
313 #thermal-sensor-cells = <0>;
316 intc_ex: interrupt-controller@e61c0000 {
317 compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
318 #interrupt-cells = <2>;
319 interrupt-controller;
320 reg = <0 0xe61c0000 0 0x200>;
321 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
328 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
333 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
334 reg = <0 0xe61e0000 0 0x30>;
339 clock-names = "fck";
340 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
346 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
347 reg = <0 0xe6fc0000 0 0x30>;
352 clock-names = "fck";
353 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
359 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
360 reg = <0 0xe6fd0000 0 0x30>;
365 clock-names = "fck";
366 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
372 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
373 reg = <0 0xe6fe0000 0 0x30>;
378 clock-names = "fck";
379 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
385 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
386 reg = <0 0xffc00000 0 0x30>;
391 clock-names = "fck";
392 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
398 #address-cells = <1>;
399 #size-cells = <0>;
400 compatible = "renesas,i2c-r8a77995",
401 "renesas,rcar-gen3-i2c";
402 reg = <0 0xe6500000 0 0x40>;
405 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
407 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
408 <&dmac2 0x91>, <&dmac2 0x90>;
409 dma-names = "tx", "rx", "tx", "rx";
410 i2c-scl-internal-delay-ns = <6>;
415 #address-cells = <1>;
416 #size-cells = <0>;
417 compatible = "renesas,i2c-r8a77995",
418 "renesas,rcar-gen3-i2c";
419 reg = <0 0xe6508000 0 0x40>;
422 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
424 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
425 <&dmac2 0x93>, <&dmac2 0x92>;
426 dma-names = "tx", "rx", "tx", "rx";
427 i2c-scl-internal-delay-ns = <6>;
432 #address-cells = <1>;
433 #size-cells = <0>;
434 compatible = "renesas,i2c-r8a77995",
435 "renesas,rcar-gen3-i2c";
436 reg = <0 0xe6510000 0 0x40>;
439 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
441 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
442 <&dmac2 0x95>, <&dmac2 0x94>;
443 dma-names = "tx", "rx", "tx", "rx";
444 i2c-scl-internal-delay-ns = <6>;
449 #address-cells = <1>;
450 #size-cells = <0>;
451 compatible = "renesas,i2c-r8a77995",
452 "renesas,rcar-gen3-i2c";
453 reg = <0 0xe66d0000 0 0x40>;
456 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
458 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
459 dma-names = "tx", "rx";
460 i2c-scl-internal-delay-ns = <6>;
465 compatible = "renesas,hscif-r8a77995",
466 "renesas,rcar-gen3-hscif",
468 reg = <0 0xe6540000 0 0x60>;
473 clock-names = "fck", "brg_int", "scif_clk";
474 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
475 <&dmac2 0x31>, <&dmac2 0x30>;
476 dma-names = "tx", "rx", "tx", "rx";
477 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
483 compatible = "renesas,hscif-r8a77995",
484 "renesas,rcar-gen3-hscif",
486 reg = <0 0xe66a0000 0 0x60>;
491 clock-names = "fck", "brg_int", "scif_clk";
492 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
493 dma-names = "tx", "rx";
494 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
500 compatible = "renesas,usbhs-r8a77995",
501 "renesas,rcar-gen3-usbhs";
502 reg = <0 0xe6590000 0 0x200>;
505 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
506 <&usb_dmac1 0>, <&usb_dmac1 1>;
507 dma-names = "ch0", "ch1", "ch2", "ch3";
510 phy-names = "usb";
511 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
516 usb_dmac0: dma-controller@e65a0000 {
517 compatible = "renesas,r8a77995-usb-dmac",
518 "renesas,usb-dmac";
519 reg = <0 0xe65a0000 0 0x100>;
522 interrupt-names = "ch0", "ch1";
524 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
526 #dma-cells = <1>;
527 dma-channels = <2>;
530 usb_dmac1: dma-controller@e65b0000 {
531 compatible = "renesas,r8a77995-usb-dmac",
532 "renesas,usb-dmac";
533 reg = <0 0xe65b0000 0 0x100>;
536 interrupt-names = "ch0", "ch1";
538 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
540 #dma-cells = <1>;
541 dma-channels = <2>;
545 compatible = "arm,cryptocell-630p-ree";
547 reg = <0x0 0xe6601000 0 0x1000>;
550 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
554 compatible = "renesas,r8a77995-canfd",
555 "renesas,rcar-gen3-canfd";
556 reg = <0 0xe66c0000 0 0x8000>;
562 clock-names = "fck", "canfd", "can_clk";
563 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
564 assigned-clock-rates = <40000000>;
565 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
578 dmac0: dma-controller@e6700000 {
579 compatible = "renesas,dmac-r8a77995",
580 "renesas,rcar-dmac";
581 reg = <0 0xe6700000 0 0x10000>;
591 interrupt-names = "error",
592 "ch0", "ch1", "ch2", "ch3",
595 clock-names = "fck";
596 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
598 #dma-cells = <1>;
599 dma-channels = <8>;
600 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
606 dmac1: dma-controller@e7300000 {
607 compatible = "renesas,dmac-r8a77995",
608 "renesas,rcar-dmac";
609 reg = <0 0xe7300000 0 0x10000>;
619 interrupt-names = "error",
620 "ch0", "ch1", "ch2", "ch3",
623 clock-names = "fck";
624 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
626 #dma-cells = <1>;
627 dma-channels = <8>;
628 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
634 dmac2: dma-controller@e7310000 {
635 compatible = "renesas,dmac-r8a77995",
636 "renesas,rcar-dmac";
637 reg = <0 0xe7310000 0 0x10000>;
647 interrupt-names = "error",
648 "ch0", "ch1", "ch2", "ch3",
651 clock-names = "fck";
652 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
654 #dma-cells = <1>;
655 dma-channels = <8>;
663 compatible = "renesas,ipmmu-r8a77995";
664 reg = <0 0xe6740000 0 0x1000>;
665 renesas,ipmmu-main = <&ipmmu_mm 0>;
666 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
667 #iommu-cells = <1>;
671 compatible = "renesas,ipmmu-r8a77995";
672 reg = <0 0xe7740000 0 0x1000>;
673 renesas,ipmmu-main = <&ipmmu_mm 1>;
674 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
675 #iommu-cells = <1>;
679 compatible = "renesas,ipmmu-r8a77995";
680 reg = <0 0xe6570000 0 0x1000>;
681 renesas,ipmmu-main = <&ipmmu_mm 2>;
682 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
683 #iommu-cells = <1>;
687 compatible = "renesas,ipmmu-r8a77995";
688 reg = <0 0xe67b0000 0 0x1000>;
691 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
692 #iommu-cells = <1>;
696 compatible = "renesas,ipmmu-r8a77995";
697 reg = <0 0xec670000 0 0x1000>;
698 renesas,ipmmu-main = <&ipmmu_mm 4>;
699 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
700 #iommu-cells = <1>;
704 compatible = "renesas,ipmmu-r8a77995";
705 reg = <0 0xfd800000 0 0x1000>;
706 renesas,ipmmu-main = <&ipmmu_mm 6>;
707 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
708 #iommu-cells = <1>;
712 compatible = "renesas,ipmmu-r8a77995";
713 reg = <0 0xffc80000 0 0x1000>;
714 renesas,ipmmu-main = <&ipmmu_mm 10>;
715 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
716 #iommu-cells = <1>;
720 compatible = "renesas,ipmmu-r8a77995";
721 reg = <0 0xfe6b0000 0 0x1000>;
722 renesas,ipmmu-main = <&ipmmu_mm 12>;
723 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
724 #iommu-cells = <1>;
728 compatible = "renesas,ipmmu-r8a77995";
729 reg = <0 0xfebd0000 0 0x1000>;
730 renesas,ipmmu-main = <&ipmmu_mm 14>;
731 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
732 #iommu-cells = <1>;
736 compatible = "renesas,ipmmu-r8a77995";
737 reg = <0 0xfe990000 0 0x1000>;
738 renesas,ipmmu-main = <&ipmmu_mm 16>;
739 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
740 #iommu-cells = <1>;
744 compatible = "renesas,etheravb-r8a77995",
745 "renesas,etheravb-rcar-gen3";
746 reg = <0 0xe6800000 0 0x800>;
772 interrupt-names = "ch0", "ch1", "ch2", "ch3",
780 clock-names = "fck";
781 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
783 phy-mode = "rgmii";
784 rx-internal-delay-ps = <1800>;
786 #address-cells = <1>;
787 #size-cells = <0>;
792 compatible = "renesas,can-r8a77995",
793 "renesas,rcar-gen3-can";
794 reg = <0 0xe6c30000 0 0x1000>;
799 clock-names = "clkp1", "clkp2", "can_clk";
800 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
801 assigned-clock-rates = <40000000>;
802 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
808 compatible = "renesas,can-r8a77995",
809 "renesas,rcar-gen3-can";
810 reg = <0 0xe6c38000 0 0x1000>;
815 clock-names = "clkp1", "clkp2", "can_clk";
816 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
817 assigned-clock-rates = <40000000>;
818 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
824 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
825 reg = <0 0xe6e30000 0 0x8>;
826 #pwm-cells = <2>;
828 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
834 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
835 reg = <0 0xe6e31000 0 0x8>;
836 #pwm-cells = <2>;
838 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
844 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
845 reg = <0 0xe6e32000 0 0x8>;
846 #pwm-cells = <2>;
848 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
854 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
855 reg = <0 0xe6e33000 0 0x8>;
856 #pwm-cells = <2>;
858 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
864 compatible = "renesas,scif-r8a77995",
865 "renesas,rcar-gen3-scif", "renesas,scif";
866 reg = <0 0xe6e60000 0 64>;
871 clock-names = "fck", "brg_int", "scif_clk";
872 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
873 <&dmac2 0x51>, <&dmac2 0x50>;
874 dma-names = "tx", "rx", "tx", "rx";
875 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
881 compatible = "renesas,scif-r8a77995",
882 "renesas,rcar-gen3-scif", "renesas,scif";
883 reg = <0 0xe6e68000 0 64>;
888 clock-names = "fck", "brg_int", "scif_clk";
889 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
890 <&dmac2 0x53>, <&dmac2 0x52>;
891 dma-names = "tx", "rx", "tx", "rx";
892 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
898 compatible = "renesas,scif-r8a77995",
899 "renesas,rcar-gen3-scif", "renesas,scif";
900 reg = <0 0xe6e88000 0 64>;
905 clock-names = "fck", "brg_int", "scif_clk";
906 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
907 <&dmac2 0x13>, <&dmac2 0x12>;
908 dma-names = "tx", "rx", "tx", "rx";
909 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
915 compatible = "renesas,scif-r8a77995",
916 "renesas,rcar-gen3-scif", "renesas,scif";
917 reg = <0 0xe6c50000 0 64>;
922 clock-names = "fck", "brg_int", "scif_clk";
923 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
924 dma-names = "tx", "rx";
925 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
931 compatible = "renesas,scif-r8a77995",
932 "renesas,rcar-gen3-scif", "renesas,scif";
933 reg = <0 0xe6c40000 0 64>;
938 clock-names = "fck", "brg_int", "scif_clk";
939 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
940 dma-names = "tx", "rx";
941 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
947 compatible = "renesas,scif-r8a77995",
948 "renesas,rcar-gen3-scif", "renesas,scif";
949 reg = <0 0xe6f30000 0 64>;
954 clock-names = "fck", "brg_int", "scif_clk";
955 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
956 <&dmac2 0x5b>, <&dmac2 0x5a>;
957 dma-names = "tx", "rx", "tx", "rx";
958 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
964 compatible = "renesas,msiof-r8a77995",
965 "renesas,rcar-gen3-msiof";
966 reg = <0 0xe6e90000 0 0x64>;
969 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
970 <&dmac2 0x41>, <&dmac2 0x40>;
971 dma-names = "tx", "rx", "tx", "rx";
972 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
974 #address-cells = <1>;
975 #size-cells = <0>;
980 compatible = "renesas,msiof-r8a77995",
981 "renesas,rcar-gen3-msiof";
982 reg = <0 0xe6ea0000 0 0x64>;
985 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
986 <&dmac2 0x43>, <&dmac2 0x42>;
987 dma-names = "tx", "rx", "tx", "rx";
988 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
990 #address-cells = <1>;
991 #size-cells = <0>;
996 compatible = "renesas,msiof-r8a77995",
997 "renesas,rcar-gen3-msiof";
998 reg = <0 0xe6c00000 0 0x64>;
1001 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1002 dma-names = "tx", "rx";
1003 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1005 #address-cells = <1>;
1006 #size-cells = <0>;
1011 compatible = "renesas,msiof-r8a77995",
1012 "renesas,rcar-gen3-msiof";
1013 reg = <0 0xe6c10000 0 0x64>;
1016 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1017 dma-names = "tx", "rx";
1018 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1020 #address-cells = <1>;
1021 #size-cells = <0>;
1026 compatible = "renesas,vin-r8a77995";
1027 reg = <0 0xe6ef4000 0 0x1000>;
1030 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1038 * #sound-dai-cells is required
1040 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1041 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1044 * #clock-cells is required for audio_clkout0/1/2/3
1046 * clkout : #clock-cells = <0>; <&rcar_sound>;
1047 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1049 compatible = "renesas,rcar_sound-r8a77995", "renesas,rcar_sound-gen3";
1050 reg = <0 0xec500000 0 0x1000>, /* SCU */
1051 <0 0xec5a0000 0 0x100>, /* ADG */
1052 <0 0xec540000 0 0x1000>, /* SSIU */
1053 <0 0xec541000 0 0x280>, /* SSI */
1054 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1055 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1065 clock-names = "ssi-all",
1068 "mix.1", "mix.0",
1069 "ctu.1", "ctu.0",
1070 "dvc.0", "dvc.1",
1072 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1075 reset-names = "ssi-all",
1080 ctu00: ctu-0 { };
1081 ctu01: ctu-1 { };
1082 ctu02: ctu-2 { };
1083 ctu03: ctu-3 { };
1084 ctu10: ctu-4 { };
1085 ctu11: ctu-5 { };
1086 ctu12: ctu-6 { };
1087 ctu13: ctu-7 { };
1091 dvc0: dvc-0 {
1092 dmas = <&audma0 0xbc>;
1093 dma-names = "tx";
1095 dvc1: dvc-1 {
1096 dmas = <&audma0 0xbe>;
1097 dma-names = "tx";
1102 mix0: mix-0 { };
1103 mix1: mix-1 { };
1107 src5: src-5 {
1109 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1110 dma-names = "rx", "tx";
1112 src6: src-6 {
1114 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1115 dma-names = "rx", "tx";
1120 ssi3: ssi-3 {
1122 dmas = <&audma0 0x07>, <&audma0 0x08>,
1123 <&audma0 0x6f>, <&audma0 0x70>;
1124 dma-names = "rx", "tx", "rxu", "txu";
1126 ssi4: ssi-4 {
1128 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1129 <&audma0 0x71>, <&audma0 0x72>;
1130 dma-names = "rx", "tx", "rxu", "txu";
1135 audma0: dma-controller@ec700000 {
1136 compatible = "renesas,dmac-r8a77995",
1137 "renesas,rcar-dmac";
1138 reg = <0 0xec700000 0 0x10000>;
1156 interrupt-names = "error",
1157 "ch0", "ch1", "ch2", "ch3",
1162 clock-names = "fck";
1163 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1165 #dma-cells = <1>;
1166 dma-channels = <16>;
1167 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1178 compatible = "generic-ohci";
1179 reg = <0 0xee080000 0 0x100>;
1183 phy-names = "usb";
1184 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1190 compatible = "generic-ehci";
1191 reg = <0 0xee080100 0 0x100>;
1195 phy-names = "usb";
1197 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1202 usb2_phy0: usb-phy@ee080200 {
1203 compatible = "renesas,usb2-phy-r8a77995",
1204 "renesas,rcar-gen3-usb2-phy";
1205 reg = <0 0xee080200 0 0x700>;
1208 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1210 #phy-cells = <1>;
1215 compatible = "renesas,sdhi-r8a77995",
1216 "renesas,rcar-gen3-sdhi";
1217 reg = <0 0xee140000 0 0x2000>;
1220 max-frequency = <200000000>;
1221 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1227 gic: interrupt-controller@f1010000 {
1228 compatible = "arm,gic-400";
1229 #interrupt-cells = <3>;
1230 #address-cells = <0>;
1231 interrupt-controller;
1232 reg = <0x0 0xf1010000 0 0x1000>,
1233 <0x0 0xf1020000 0 0x20000>,
1234 <0x0 0xf1040000 0 0x20000>,
1235 <0x0 0xf1060000 0 0x20000>;
1239 clock-names = "clk";
1240 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1246 reg = <0 0xfe960000 0 0x8000>;
1249 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1256 reg = <0 0xfea20000 0 0x5000>;
1259 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1266 reg = <0 0xfea28000 0 0x5000>;
1269 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1276 reg = <0 0xfe96f000 0 0x200>;
1278 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1285 reg = <0 0xfea27000 0 0x200>;
1287 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1294 reg = <0 0xfea2f000 0 0x200>;
1296 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1302 compatible = "renesas,r8a77995-cmm",
1303 "renesas,rcar-gen3-cmm";
1304 reg = <0 0xfea40000 0 0x1000>;
1305 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1311 compatible = "renesas,r8a77995-cmm",
1312 "renesas,rcar-gen3-cmm";
1313 reg = <0 0xfea50000 0 0x1000>;
1314 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1320 compatible = "renesas,du-r8a77995";
1321 reg = <0 0xfeb00000 0 0x40000>;
1325 clock-names = "du.0", "du.1";
1327 reset-names = "du.0";
1330 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
1335 #address-cells = <1>;
1336 #size-cells = <0>;
1338 port@0 {
1339 reg = <0>;
1347 remote-endpoint = <&lvds0_in>;
1354 remote-endpoint = <&lvds1_in>;
1360 lvds0: lvds-encoder@feb90000 {
1361 compatible = "renesas,r8a77995-lvds";
1362 reg = <0 0xfeb90000 0 0x20>;
1364 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1371 #address-cells = <1>;
1372 #size-cells = <0>;
1374 port@0 {
1375 reg = <0>;
1377 remote-endpoint = <&du_out_lvds0>;
1389 lvds1: lvds-encoder@feb90100 {
1390 compatible = "renesas,r8a77995-lvds";
1391 reg = <0 0xfeb90100 0 0x20>;
1393 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1398 #address-cells = <1>;
1399 #size-cells = <0>;
1401 port@0 {
1402 reg = <0>;
1404 remote-endpoint = <&du_out_lvds1>;
1418 reg = <0 0xfff00044 0 4>;
1422 thermal-zones {
1423 cpu_thermal: cpu-thermal {
1424 polling-delay-passive = <250>;
1425 polling-delay = <1000>;
1426 thermal-sensors = <&thermal>;
1428 cooling-maps {
1432 cpu-crit {
1442 compatible = "arm,armv8-timer";
1443 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,