Lines Matching +full:pwm +full:- +full:rcar
1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3H (R8A77980) SoC
9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/r8a77980-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
28 /* External CAN clock - to be overridden by boards that provide it */
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <0>;
36 #address-cells = <1>;
37 #size-cells = <0>;
41 compatible = "arm,cortex-a53";
44 power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
45 next-level-cache = <&L2_CA53>;
46 enable-method = "psci";
51 compatible = "arm,cortex-a53";
54 power-domains = <&sysc R8A77980_PD_CA53_CPU1>;
55 next-level-cache = <&L2_CA53>;
56 enable-method = "psci";
61 compatible = "arm,cortex-a53";
64 power-domains = <&sysc R8A77980_PD_CA53_CPU2>;
65 next-level-cache = <&L2_CA53>;
66 enable-method = "psci";
71 compatible = "arm,cortex-a53";
74 power-domains = <&sysc R8A77980_PD_CA53_CPU3>;
75 next-level-cache = <&L2_CA53>;
76 enable-method = "psci";
79 L2_CA53: cache-controller {
81 power-domains = <&sysc R8A77980_PD_CA53_SCU>;
82 cache-unified;
83 cache-level = <2>;
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
91 clock-frequency = <0>;
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
98 clock-frequency = <0>;
101 /* External PCIe clock - can be overridden by the board */
103 compatible = "fixed-clock";
104 #clock-cells = <0>;
105 clock-frequency = <0>;
109 compatible = "arm,cortex-a53-pmu";
110 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
114 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
118 compatible = "arm,psci-1.0", "arm,psci-0.2";
122 /* External SCIF clock - to be overridden by boards that provide it */
124 compatible = "fixed-clock";
125 #clock-cells = <0>;
126 clock-frequency = <0>;
130 compatible = "simple-bus";
131 interrupt-parent = <&gic>;
133 #address-cells = <2>;
134 #size-cells = <2>;
138 compatible = "renesas,r8a77980-wdt",
139 "renesas,rcar-gen3-wdt";
142 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
148 compatible = "renesas,gpio-r8a77980",
149 "renesas,rcar-gen3-gpio";
152 #gpio-cells = <2>;
153 gpio-controller;
154 gpio-ranges = <&pfc 0 0 22>;
155 #interrupt-cells = <2>;
156 interrupt-controller;
158 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
163 compatible = "renesas,gpio-r8a77980",
164 "renesas,rcar-gen3-gpio";
167 #gpio-cells = <2>;
168 gpio-controller;
169 gpio-ranges = <&pfc 0 32 28>;
170 #interrupt-cells = <2>;
171 interrupt-controller;
173 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
178 compatible = "renesas,gpio-r8a77980",
179 "renesas,rcar-gen3-gpio";
182 #gpio-cells = <2>;
183 gpio-controller;
184 gpio-ranges = <&pfc 0 64 30>;
185 #interrupt-cells = <2>;
186 interrupt-controller;
188 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
193 compatible = "renesas,gpio-r8a77980",
194 "renesas,rcar-gen3-gpio";
197 #gpio-cells = <2>;
198 gpio-controller;
199 gpio-ranges = <&pfc 0 96 17>;
200 #interrupt-cells = <2>;
201 interrupt-controller;
203 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
208 compatible = "renesas,gpio-r8a77980",
209 "renesas,rcar-gen3-gpio";
212 #gpio-cells = <2>;
213 gpio-controller;
214 gpio-ranges = <&pfc 0 128 25>;
215 #interrupt-cells = <2>;
216 interrupt-controller;
218 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
223 compatible = "renesas,gpio-r8a77980",
224 "renesas,rcar-gen3-gpio";
227 #gpio-cells = <2>;
228 gpio-controller;
229 gpio-ranges = <&pfc 0 160 15>;
230 #interrupt-cells = <2>;
231 interrupt-controller;
233 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
238 compatible = "renesas,pfc-r8a77980";
243 compatible = "renesas,r8a77980-cmt0",
244 "renesas,rcar-gen3-cmt0";
249 clock-names = "fck";
250 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
256 compatible = "renesas,r8a77980-cmt1",
257 "renesas,rcar-gen3-cmt1";
268 clock-names = "fck";
269 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
275 compatible = "renesas,r8a77980-cmt1",
276 "renesas,rcar-gen3-cmt1";
287 clock-names = "fck";
288 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
294 compatible = "renesas,r8a77980-cmt1",
295 "renesas,rcar-gen3-cmt1";
306 clock-names = "fck";
307 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
312 cpg: clock-controller@e6150000 {
313 compatible = "renesas,r8a77980-cpg-mssr";
316 clock-names = "extal", "extalr";
317 #clock-cells = <2>;
318 #power-domain-cells = <0>;
319 #reset-cells = <1>;
322 rst: reset-controller@e6160000 {
323 compatible = "renesas,r8a77980-rst";
327 sysc: system-controller@e6180000 {
328 compatible = "renesas,r8a77980-sysc";
330 #power-domain-cells = <1>;
334 compatible = "renesas,r8a77980-thermal";
341 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
343 #thermal-sensor-cells = <1>;
346 intc_ex: interrupt-controller@e61c0000 {
347 compatible = "renesas,intc-ex-r8a77980", "renesas,irqc";
348 #interrupt-cells = <2>;
349 interrupt-controller;
358 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
363 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
369 clock-names = "fck";
370 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
376 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
382 clock-names = "fck";
383 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
389 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
395 clock-names = "fck";
396 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
402 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
408 clock-names = "fck";
409 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
415 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
421 clock-names = "fck";
422 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
428 compatible = "renesas,i2c-r8a77980",
429 "renesas,rcar-gen3-i2c";
433 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
437 dma-names = "tx", "rx", "tx", "rx";
438 i2c-scl-internal-delay-ns = <6>;
439 #address-cells = <1>;
440 #size-cells = <0>;
445 compatible = "renesas,i2c-r8a77980",
446 "renesas,rcar-gen3-i2c";
450 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
454 dma-names = "tx", "rx", "tx", "rx";
455 i2c-scl-internal-delay-ns = <6>;
456 #address-cells = <1>;
457 #size-cells = <0>;
462 compatible = "renesas,i2c-r8a77980",
463 "renesas,rcar-gen3-i2c";
467 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
471 dma-names = "tx", "rx", "tx", "rx";
472 i2c-scl-internal-delay-ns = <6>;
473 #address-cells = <1>;
474 #size-cells = <0>;
479 compatible = "renesas,i2c-r8a77980",
480 "renesas,rcar-gen3-i2c";
484 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
486 i2c-scl-internal-delay-ns = <6>;
487 #address-cells = <1>;
488 #size-cells = <0>;
493 compatible = "renesas,i2c-r8a77980",
494 "renesas,rcar-gen3-i2c";
498 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
500 i2c-scl-internal-delay-ns = <6>;
501 #address-cells = <1>;
502 #size-cells = <0>;
507 compatible = "renesas,i2c-r8a77980",
508 "renesas,rcar-gen3-i2c";
512 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
516 dma-names = "tx", "rx", "tx", "rx";
517 i2c-scl-internal-delay-ns = <6>;
518 #address-cells = <1>;
519 #size-cells = <0>;
524 compatible = "renesas,hscif-r8a77980",
525 "renesas,rcar-gen3-hscif",
532 clock-names = "fck", "brg_int", "scif_clk";
535 dma-names = "tx", "rx", "tx", "rx";
536 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
542 compatible = "renesas,hscif-r8a77980",
543 "renesas,rcar-gen3-hscif",
550 clock-names = "fck", "brg_int", "scif_clk";
553 dma-names = "tx", "rx", "tx", "rx";
554 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
560 compatible = "renesas,hscif-r8a77980",
561 "renesas,rcar-gen3-hscif",
568 clock-names = "fck", "brg_int", "scif_clk";
571 dma-names = "tx", "rx", "tx", "rx";
572 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
578 compatible = "renesas,hscif-r8a77980",
579 "renesas,rcar-gen3-hscif",
586 clock-names = "fck", "brg_int", "scif_clk";
589 dma-names = "tx", "rx", "tx", "rx";
590 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
595 pcie_phy: pcie-phy@e65d0000 {
596 compatible = "renesas,r8a77980-pcie-phy";
598 #phy-cells = <0>;
600 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
606 compatible = "renesas,r8a77980-canfd",
607 "renesas,rcar-gen3-canfd";
614 clock-names = "fck", "canfd", "can_clk";
615 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
616 assigned-clock-rates = <40000000>;
617 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
631 compatible = "renesas,etheravb-r8a77980",
632 "renesas,etheravb-rcar-gen3";
659 interrupt-names = "ch0", "ch1", "ch2", "ch3",
667 clock-names = "fck";
668 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
670 phy-mode = "rgmii";
671 rx-internal-delay-ps = <0>;
672 tx-internal-delay-ps = <2000>;
674 #address-cells = <1>;
675 #size-cells = <0>;
679 pwm0: pwm@e6e30000 {
680 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
682 #pwm-cells = <2>;
684 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
689 pwm1: pwm@e6e31000 {
690 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
692 #pwm-cells = <2>;
694 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
699 pwm2: pwm@e6e32000 {
700 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
702 #pwm-cells = <2>;
704 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
709 pwm3: pwm@e6e33000 {
710 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
712 #pwm-cells = <2>;
714 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
719 pwm4: pwm@e6e34000 {
720 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
722 #pwm-cells = <2>;
724 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
730 compatible = "renesas,scif-r8a77980",
731 "renesas,rcar-gen3-scif",
738 clock-names = "fck", "brg_int", "scif_clk";
741 dma-names = "tx", "rx", "tx", "rx";
742 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
748 compatible = "renesas,scif-r8a77980",
749 "renesas,rcar-gen3-scif",
756 clock-names = "fck", "brg_int", "scif_clk";
759 dma-names = "tx", "rx", "tx", "rx";
760 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
766 compatible = "renesas,scif-r8a77980",
767 "renesas,rcar-gen3-scif",
774 clock-names = "fck", "brg_int", "scif_clk";
777 dma-names = "tx", "rx", "tx", "rx";
778 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
784 compatible = "renesas,scif-r8a77980",
785 "renesas,rcar-gen3-scif",
792 clock-names = "fck", "brg_int", "scif_clk";
795 dma-names = "tx", "rx", "tx", "rx";
796 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
801 tpu: pwm@e6e80000 {
802 compatible = "renesas,tpu-r8a77980", "renesas,tpu";
806 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
808 #pwm-cells = <3>;
813 compatible = "renesas,msiof-r8a77980",
814 "renesas,rcar-gen3-msiof";
818 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
820 #address-cells = <1>;
821 #size-cells = <0>;
826 compatible = "renesas,msiof-r8a77980",
827 "renesas,rcar-gen3-msiof";
831 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
833 #address-cells = <1>;
834 #size-cells = <0>;
839 compatible = "renesas,msiof-r8a77980",
840 "renesas,rcar-gen3-msiof";
844 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
846 #address-cells = <1>;
847 #size-cells = <0>;
852 compatible = "renesas,msiof-r8a77980",
853 "renesas,rcar-gen3-msiof";
857 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
859 #address-cells = <1>;
860 #size-cells = <0>;
865 compatible = "renesas,vin-r8a77980";
869 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
875 #address-cells = <1>;
876 #size-cells = <0>;
879 #address-cells = <1>;
880 #size-cells = <0>;
886 remote-endpoint = <&csi40vin0>;
893 compatible = "renesas,vin-r8a77980";
897 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
903 #address-cells = <1>;
904 #size-cells = <0>;
907 #address-cells = <1>;
908 #size-cells = <0>;
914 remote-endpoint = <&csi40vin1>;
921 compatible = "renesas,vin-r8a77980";
925 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
931 #address-cells = <1>;
932 #size-cells = <0>;
935 #address-cells = <1>;
936 #size-cells = <0>;
942 remote-endpoint = <&csi40vin2>;
949 compatible = "renesas,vin-r8a77980";
953 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
959 #address-cells = <1>;
960 #size-cells = <0>;
963 #address-cells = <1>;
964 #size-cells = <0>;
970 remote-endpoint = <&csi40vin3>;
977 compatible = "renesas,vin-r8a77980";
981 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
987 #address-cells = <1>;
988 #size-cells = <0>;
991 #address-cells = <1>;
992 #size-cells = <0>;
998 remote-endpoint = <&csi41vin4>;
1005 compatible = "renesas,vin-r8a77980";
1009 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1019 #address-cells = <1>;
1020 #size-cells = <0>;
1026 remote-endpoint = <&csi41vin5>;
1033 compatible = "renesas,vin-r8a77980";
1037 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1043 #address-cells = <1>;
1044 #size-cells = <0>;
1047 #address-cells = <1>;
1048 #size-cells = <0>;
1054 remote-endpoint = <&csi41vin6>;
1061 compatible = "renesas,vin-r8a77980";
1065 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1075 #address-cells = <1>;
1076 #size-cells = <0>;
1082 remote-endpoint = <&csi41vin7>;
1089 compatible = "renesas,vin-r8a77980";
1093 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1100 compatible = "renesas,vin-r8a77980";
1104 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1111 compatible = "renesas,vin-r8a77980";
1115 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1122 compatible = "renesas,vin-r8a77980";
1126 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1133 compatible = "renesas,vin-r8a77980";
1137 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1144 compatible = "renesas,vin-r8a77980";
1148 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1155 compatible = "renesas,vin-r8a77980";
1159 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1166 compatible = "renesas,vin-r8a77980";
1170 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1176 dmac1: dma-controller@e7300000 {
1177 compatible = "renesas,dmac-r8a77980",
1178 "renesas,rcar-dmac";
1197 interrupt-names = "error",
1203 clock-names = "fck";
1204 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1206 #dma-cells = <1>;
1207 dma-channels = <16>;
1218 dmac2: dma-controller@e7310000 {
1219 compatible = "renesas,dmac-r8a77980",
1220 "renesas,rcar-dmac";
1239 interrupt-names = "error",
1245 clock-names = "fck";
1246 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1248 #dma-cells = <1>;
1249 dma-channels = <16>;
1261 compatible = "renesas,gether-r8a77980";
1265 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1267 #address-cells = <1>;
1268 #size-cells = <0>;
1273 compatible = "renesas,ipmmu-r8a77980";
1275 renesas,ipmmu-main = <&ipmmu_mm 0>;
1276 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1277 #iommu-cells = <1>;
1281 compatible = "renesas,ipmmu-r8a77980";
1283 renesas,ipmmu-main = <&ipmmu_mm 3>;
1284 power-domains = <&sysc R8A77980_PD_A3IR>;
1285 #iommu-cells = <1>;
1289 compatible = "renesas,ipmmu-r8a77980";
1293 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1294 #iommu-cells = <1>;
1298 compatible = "renesas,ipmmu-r8a77980";
1300 renesas,ipmmu-main = <&ipmmu_mm 10>;
1301 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1302 #iommu-cells = <1>;
1306 compatible = "renesas,ipmmu-r8a77980";
1308 renesas,ipmmu-main = <&ipmmu_mm 12>;
1309 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1310 #iommu-cells = <1>;
1314 compatible = "renesas,ipmmu-r8a77980";
1316 renesas,ipmmu-main = <&ipmmu_mm 14>;
1317 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1318 #iommu-cells = <1>;
1322 compatible = "renesas,ipmmu-r8a77980";
1324 renesas,ipmmu-main = <&ipmmu_mm 4>;
1325 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1326 #iommu-cells = <1>;
1330 compatible = "renesas,ipmmu-r8a77980";
1332 renesas,ipmmu-main = <&ipmmu_mm 11>;
1333 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1334 #iommu-cells = <1>;
1338 compatible = "renesas,sdhi-r8a77980",
1339 "renesas,rcar-gen3-sdhi";
1343 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1345 max-frequency = <200000000>;
1351 compatible = "renesas,r8a77980-rpc-if",
1352 "renesas,rcar-gen3-rpc-if";
1356 reg-names = "regs", "dirmap", "wbuf";
1359 clock-names = "rpc";
1360 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1367 gic: interrupt-controller@f1010000 {
1368 compatible = "arm,gic-400";
1369 #interrupt-cells = <3>;
1370 #address-cells = <0>;
1371 interrupt-controller;
1379 clock-names = "clk";
1380 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1385 compatible = "renesas,pcie-r8a77980",
1386 "renesas,pcie-rcar-gen3";
1388 #address-cells = <3>;
1389 #size-cells = <2>;
1390 bus-range = <0x00 0xff>;
1396 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1400 #interrupt-cells = <1>;
1401 interrupt-map-mask = <0 0 0 0>;
1402 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1404 clock-names = "pcie", "pcie_bus";
1405 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1408 phy-names = "pcie";
1417 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1426 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1431 compatible = "renesas,r8a77980-csi2";
1435 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1440 #address-cells = <1>;
1441 #size-cells = <0>;
1448 #address-cells = <1>;
1449 #size-cells = <0>;
1455 remote-endpoint = <&vin0csi40>;
1459 remote-endpoint = <&vin1csi40>;
1463 remote-endpoint = <&vin2csi40>;
1467 remote-endpoint = <&vin3csi40>;
1474 compatible = "renesas,r8a77980-csi2";
1478 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1483 #address-cells = <1>;
1484 #size-cells = <0>;
1491 #address-cells = <1>;
1492 #size-cells = <0>;
1498 remote-endpoint = <&vin4csi41>;
1502 remote-endpoint = <&vin5csi41>;
1506 remote-endpoint = <&vin6csi41>;
1510 remote-endpoint = <&vin7csi41>;
1517 compatible = "renesas,du-r8a77980";
1521 clock-names = "du.0";
1522 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1524 reset-names = "du.0";
1530 #address-cells = <1>;
1531 #size-cells = <0>;
1542 remote-endpoint = <&lvds0_in>;
1548 lvds0: lvds-encoder@feb90000 {
1549 compatible = "renesas,r8a77980-lvds";
1552 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1557 #address-cells = <1>;
1558 #size-cells = <0>;
1563 remote-endpoint =
1582 thermal-zones {
1583 thermal-sensor-1 {
1584 polling-delay-passive = <250>;
1585 polling-delay = <1000>;
1586 thermal-sensors = <&tsc 0>;
1589 sensor1-passive {
1594 sensor1-critical {
1602 thermal-sensor-2 {
1603 polling-delay-passive = <250>;
1604 polling-delay = <1000>;
1605 thermal-sensors = <&tsc 1>;
1608 sensor2-passive {
1613 sensor2-critical {
1623 compatible = "arm,armv8-timer";
1624 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |