Lines Matching refs:gcc
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
475 gcc: clock-controller@100000 { label
476 compatible = "qcom,gcc-sm8250";
501 clocks = <&gcc GCC_PRNG_AHB_CLK>;
548 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
549 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
560 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
576 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
592 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
608 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
624 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
640 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
656 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
672 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
688 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
701 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
717 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
733 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
746 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
762 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
802 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
803 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
814 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
830 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
846 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
862 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
878 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
894 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
910 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
923 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
939 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
955 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
971 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
987 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1003 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1019 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1035 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1051 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1064 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1080 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1117 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1118 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1129 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1145 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1161 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1177 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1193 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1209 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1225 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1241 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1257 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1273 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1289 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1302 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1318 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1408 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1409 <&gcc GCC_PCIE_0_AUX_CLK>,
1410 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1411 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1412 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1413 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1414 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1415 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1429 resets = <&gcc GCC_PCIE_0_BCR>;
1432 power-domains = <&gcc PCIE_0_GDSC>;
1452 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1453 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1454 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
1455 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1458 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1461 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1471 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1507 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1508 <&gcc GCC_PCIE_1_AUX_CLK>,
1509 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1510 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1511 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1512 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1513 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1514 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1515 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1526 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1533 resets = <&gcc GCC_PCIE_1_BCR>;
1536 power-domains = <&gcc PCIE_1_GDSC>;
1556 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1557 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1558 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1559 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1562 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1565 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1577 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1613 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1614 <&gcc GCC_PCIE_2_AUX_CLK>,
1615 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1616 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1617 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
1618 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
1619 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
1620 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1621 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1632 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
1639 resets = <&gcc GCC_PCIE_2_BCR>;
1642 power-domains = <&gcc PCIE_2_GDSC>;
1662 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1663 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1664 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
1665 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
1668 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
1671 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
1683 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
1700 resets = <&gcc GCC_UFS_PHY_BCR>;
1703 power-domains = <&gcc UFS_PHY_GDSC>;
1717 <&gcc GCC_UFS_PHY_AXI_CLK>,
1718 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1719 <&gcc GCC_UFS_PHY_AHB_CLK>,
1720 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1722 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1723 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1724 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1747 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2015 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2016 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2043 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2044 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2069 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2070 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2251 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2264 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2277 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2279 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2282 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2283 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2295 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2309 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2323 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2325 <&gcc GCC_USB3_SEC_CLKREF_EN>,
2326 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2329 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2330 <&gcc GCC_USB3_PHY_SEC_BCR>;
2339 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2353 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2354 <&gcc GCC_SDCC2_APPS_CLK>,
2420 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2421 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2422 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2423 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2424 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2425 <&gcc GCC_USB3_SEC_CLKREF_EN>;
2429 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2430 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2440 power-domains = <&gcc USB30_PRIM_GDSC>;
2442 resets = <&gcc GCC_USB30_PRIM_BCR>;
2471 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2472 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2473 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2474 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2475 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2476 <&gcc GCC_USB3_SEC_CLKREF_EN>;
2480 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2481 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2491 power-domains = <&gcc USB30_SEC_GDSC>;
2493 resets = <&gcc GCC_USB30_SEC_BCR>;
2517 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
2529 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
2571 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
2593 <&gcc GCC_DISP_HF_AXI_CLK>,
2594 <&gcc GCC_DISP_SF_AXI_CLK>,
2620 <&gcc GCC_DISP_HF_AXI_CLK>,
2693 <&gcc GCC_DISP_HF_AXI_CLK>;
2766 <&gcc GCC_DISP_HF_AXI_CLK>;
4088 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4102 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;