Lines Matching +full:qcom +full:- +full:tsens
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/power/qcom-aoss-qmp.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/soc/qcom,apr.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
20 #include <dt-bindings/sound/qcom,q6afe.h>
21 #include <dt-bindings/thermal/thermal.h>
22 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
25 interrupt-parent = <&intc>;
27 #address-cells = <2>;
28 #size-cells = <2>;
76 xo_board: xo-board {
77 compatible = "fixed-clock";
78 #clock-cells = <0>;
79 clock-frequency = <38400000>;
80 clock-output-names = "xo_board";
83 sleep_clk: sleep-clk {
84 compatible = "fixed-clock";
85 clock-frequency = <32768>;
86 #clock-cells = <0>;
91 #address-cells = <2>;
92 #size-cells = <0>;
96 compatible = "qcom,kryo485";
98 enable-method = "psci";
99 capacity-dmips-mhz = <448>;
100 dynamic-power-coefficient = <205>;
101 next-level-cache = <&L2_0>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
103 #cooling-cells = <2>;
104 L2_0: l2-cache {
106 next-level-cache = <&L3_0>;
107 L3_0: l3-cache {
115 compatible = "qcom,kryo485";
117 enable-method = "psci";
118 capacity-dmips-mhz = <448>;
119 dynamic-power-coefficient = <205>;
120 next-level-cache = <&L2_100>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
122 #cooling-cells = <2>;
123 L2_100: l2-cache {
125 next-level-cache = <&L3_0>;
131 compatible = "qcom,kryo485";
133 enable-method = "psci";
134 capacity-dmips-mhz = <448>;
135 dynamic-power-coefficient = <205>;
136 next-level-cache = <&L2_200>;
137 qcom,freq-domain = <&cpufreq_hw 0>;
138 #cooling-cells = <2>;
139 L2_200: l2-cache {
141 next-level-cache = <&L3_0>;
147 compatible = "qcom,kryo485";
149 enable-method = "psci";
150 capacity-dmips-mhz = <448>;
151 dynamic-power-coefficient = <205>;
152 next-level-cache = <&L2_300>;
153 qcom,freq-domain = <&cpufreq_hw 0>;
154 #cooling-cells = <2>;
155 L2_300: l2-cache {
157 next-level-cache = <&L3_0>;
163 compatible = "qcom,kryo485";
165 enable-method = "psci";
166 capacity-dmips-mhz = <1024>;
167 dynamic-power-coefficient = <379>;
168 next-level-cache = <&L2_400>;
169 qcom,freq-domain = <&cpufreq_hw 1>;
170 #cooling-cells = <2>;
171 L2_400: l2-cache {
173 next-level-cache = <&L3_0>;
179 compatible = "qcom,kryo485";
181 enable-method = "psci";
182 capacity-dmips-mhz = <1024>;
183 dynamic-power-coefficient = <379>;
184 next-level-cache = <&L2_500>;
185 qcom,freq-domain = <&cpufreq_hw 1>;
186 #cooling-cells = <2>;
187 L2_500: l2-cache {
189 next-level-cache = <&L3_0>;
196 compatible = "qcom,kryo485";
198 enable-method = "psci";
199 capacity-dmips-mhz = <1024>;
200 dynamic-power-coefficient = <379>;
201 next-level-cache = <&L2_600>;
202 qcom,freq-domain = <&cpufreq_hw 1>;
203 #cooling-cells = <2>;
204 L2_600: l2-cache {
206 next-level-cache = <&L3_0>;
212 compatible = "qcom,kryo485";
214 enable-method = "psci";
215 capacity-dmips-mhz = <1024>;
216 dynamic-power-coefficient = <444>;
217 next-level-cache = <&L2_700>;
218 qcom,freq-domain = <&cpufreq_hw 2>;
219 #cooling-cells = <2>;
220 L2_700: l2-cache {
222 next-level-cache = <&L3_0>;
226 cpu-map {
265 compatible = "qcom,scm";
266 #reset-cells = <1>;
276 mmcx_reg: mmcx-reg {
277 compatible = "regulator-fixed-domain";
278 power-domains = <&rpmhpd SM8250_MMCX>;
279 required-opps = <&rpmhpd_opp_low_svs>;
280 regulator-name = "MMCX";
284 compatible = "arm,armv8-pmuv3";
289 compatible = "arm,psci-1.0";
293 reserved-memory {
294 #address-cells = <2>;
295 #size-cells = <2>;
300 no-map;
305 no-map;
309 compatible = "qcom,cmd-db";
311 no-map;
316 no-map;
321 no-map;
326 no-map;
331 no-map;
336 no-map;
341 no-map;
346 no-map;
351 no-map;
356 no-map;
361 no-map;
366 no-map;
371 no-map;
376 no-map;
381 no-map;
386 no-map;
391 compatible = "qcom,smem";
392 memory-region = <&smem_mem>;
396 smp2p-adsp {
397 compatible = "qcom,smp2p";
398 qcom,smem = <443>, <429>;
399 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
405 qcom,local-pid = <0>;
406 qcom,remote-pid = <2>;
408 smp2p_adsp_out: master-kernel {
409 qcom,entry-name = "master-kernel";
410 #qcom,smem-state-cells = <1>;
413 smp2p_adsp_in: slave-kernel {
414 qcom,entry-name = "slave-kernel";
415 interrupt-controller;
416 #interrupt-cells = <2>;
420 smp2p-cdsp {
421 compatible = "qcom,smp2p";
422 qcom,smem = <94>, <432>;
423 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
429 qcom,local-pid = <0>;
430 qcom,remote-pid = <5>;
432 smp2p_cdsp_out: master-kernel {
433 qcom,entry-name = "master-kernel";
434 #qcom,smem-state-cells = <1>;
437 smp2p_cdsp_in: slave-kernel {
438 qcom,entry-name = "slave-kernel";
439 interrupt-controller;
440 #interrupt-cells = <2>;
444 smp2p-slpi {
445 compatible = "qcom,smp2p";
446 qcom,smem = <481>, <430>;
447 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
453 qcom,local-pid = <0>;
454 qcom,remote-pid = <3>;
456 smp2p_slpi_out: master-kernel {
457 qcom,entry-name = "master-kernel";
458 #qcom,smem-state-cells = <1>;
461 smp2p_slpi_in: slave-kernel {
462 qcom,entry-name = "slave-kernel";
463 interrupt-controller;
464 #interrupt-cells = <2>;
469 #address-cells = <2>;
470 #size-cells = <2>;
472 dma-ranges = <0 0 0 0 0x10 0>;
473 compatible = "simple-bus";
475 gcc: clock-controller@100000 {
476 compatible = "qcom,gcc-sm8250";
478 #clock-cells = <1>;
479 #reset-cells = <1>;
480 #power-domain-cells = <1>;
481 clock-names = "bi_tcxo",
490 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
493 interrupt-controller;
494 #interrupt-cells = <3>;
495 #mbox-cells = <2>;
499 compatible = "qcom,prng-ee";
502 clock-names = "core";
505 qup_opp_table: qup-opp-table {
506 compatible = "operating-points-v2";
508 opp-50000000 {
509 opp-hz = /bits/ 64 <50000000>;
510 required-opps = <&rpmhpd_opp_min_svs>;
513 opp-75000000 {
514 opp-hz = /bits/ 64 <75000000>;
515 required-opps = <&rpmhpd_opp_low_svs>;
518 opp-120000000 {
519 opp-hz = /bits/ 64 <120000000>;
520 required-opps = <&rpmhpd_opp_svs>;
524 gpi_dma2: dma-controller@800000 {
525 compatible = "qcom,sm8250-gpi-dma";
537 dma-channels = <10>;
538 dma-channel-mask = <0x3f>;
540 #dma-cells = <3>;
545 compatible = "qcom,geni-se-qup";
547 clock-names = "m-ahb", "s-ahb";
550 #address-cells = <2>;
551 #size-cells = <2>;
557 compatible = "qcom,geni-i2c";
559 clock-names = "se";
561 pinctrl-names = "default";
562 pinctrl-0 = <&qup_i2c14_default>;
566 dma-names = "tx", "rx";
567 #address-cells = <1>;
568 #size-cells = <0>;
573 compatible = "qcom,geni-spi";
575 clock-names = "se";
580 dma-names = "tx", "rx";
581 power-domains = <&rpmhpd SM8250_CX>;
582 operating-points-v2 = <&qup_opp_table>;
583 #address-cells = <1>;
584 #size-cells = <0>;
589 compatible = "qcom,geni-i2c";
591 clock-names = "se";
593 pinctrl-names = "default";
594 pinctrl-0 = <&qup_i2c15_default>;
598 dma-names = "tx", "rx";
599 #address-cells = <1>;
600 #size-cells = <0>;
605 compatible = "qcom,geni-spi";
607 clock-names = "se";
612 dma-names = "tx", "rx";
613 power-domains = <&rpmhpd SM8250_CX>;
614 operating-points-v2 = <&qup_opp_table>;
615 #address-cells = <1>;
616 #size-cells = <0>;
621 compatible = "qcom,geni-i2c";
623 clock-names = "se";
625 pinctrl-names = "default";
626 pinctrl-0 = <&qup_i2c16_default>;
630 dma-names = "tx", "rx";
631 #address-cells = <1>;
632 #size-cells = <0>;
637 compatible = "qcom,geni-spi";
639 clock-names = "se";
644 dma-names = "tx", "rx";
645 power-domains = <&rpmhpd SM8250_CX>;
646 operating-points-v2 = <&qup_opp_table>;
647 #address-cells = <1>;
648 #size-cells = <0>;
653 compatible = "qcom,geni-i2c";
655 clock-names = "se";
657 pinctrl-names = "default";
658 pinctrl-0 = <&qup_i2c17_default>;
662 dma-names = "tx", "rx";
663 #address-cells = <1>;
664 #size-cells = <0>;
669 compatible = "qcom,geni-spi";
671 clock-names = "se";
676 dma-names = "tx", "rx";
677 power-domains = <&rpmhpd SM8250_CX>;
678 operating-points-v2 = <&qup_opp_table>;
679 #address-cells = <1>;
680 #size-cells = <0>;
685 compatible = "qcom,geni-uart";
687 clock-names = "se";
689 pinctrl-names = "default";
690 pinctrl-0 = <&qup_uart17_default>;
692 power-domains = <&rpmhpd SM8250_CX>;
693 operating-points-v2 = <&qup_opp_table>;
698 compatible = "qcom,geni-i2c";
700 clock-names = "se";
702 pinctrl-names = "default";
703 pinctrl-0 = <&qup_i2c18_default>;
707 dma-names = "tx", "rx";
708 #address-cells = <1>;
709 #size-cells = <0>;
714 compatible = "qcom,geni-spi";
716 clock-names = "se";
721 dma-names = "tx", "rx";
722 power-domains = <&rpmhpd SM8250_CX>;
723 operating-points-v2 = <&qup_opp_table>;
724 #address-cells = <1>;
725 #size-cells = <0>;
730 compatible = "qcom,geni-uart";
732 clock-names = "se";
734 pinctrl-names = "default";
735 pinctrl-0 = <&qup_uart18_default>;
737 power-domains = <&rpmhpd SM8250_CX>;
738 operating-points-v2 = <&qup_opp_table>;
743 compatible = "qcom,geni-i2c";
745 clock-names = "se";
747 pinctrl-names = "default";
748 pinctrl-0 = <&qup_i2c19_default>;
752 dma-names = "tx", "rx";
753 #address-cells = <1>;
754 #size-cells = <0>;
759 compatible = "qcom,geni-spi";
761 clock-names = "se";
766 dma-names = "tx", "rx";
767 power-domains = <&rpmhpd SM8250_CX>;
768 operating-points-v2 = <&qup_opp_table>;
769 #address-cells = <1>;
770 #size-cells = <0>;
775 gpi_dma0: dma-controller@900000 {
776 compatible = "qcom,sm8250-gpi-dma";
791 dma-channels = <15>;
792 dma-channel-mask = <0x7ff>;
794 #dma-cells = <3>;
799 compatible = "qcom,geni-se-qup";
801 clock-names = "m-ahb", "s-ahb";
804 #address-cells = <2>;
805 #size-cells = <2>;
811 compatible = "qcom,geni-i2c";
813 clock-names = "se";
815 pinctrl-names = "default";
816 pinctrl-0 = <&qup_i2c0_default>;
820 dma-names = "tx", "rx";
821 #address-cells = <1>;
822 #size-cells = <0>;
827 compatible = "qcom,geni-spi";
829 clock-names = "se";
834 dma-names = "tx", "rx";
835 power-domains = <&rpmhpd SM8250_CX>;
836 operating-points-v2 = <&qup_opp_table>;
837 #address-cells = <1>;
838 #size-cells = <0>;
843 compatible = "qcom,geni-i2c";
845 clock-names = "se";
847 pinctrl-names = "default";
848 pinctrl-0 = <&qup_i2c1_default>;
852 dma-names = "tx", "rx";
853 #address-cells = <1>;
854 #size-cells = <0>;
859 compatible = "qcom,geni-spi";
861 clock-names = "se";
866 dma-names = "tx", "rx";
867 power-domains = <&rpmhpd SM8250_CX>;
868 operating-points-v2 = <&qup_opp_table>;
869 #address-cells = <1>;
870 #size-cells = <0>;
875 compatible = "qcom,geni-i2c";
877 clock-names = "se";
879 pinctrl-names = "default";
880 pinctrl-0 = <&qup_i2c2_default>;
884 dma-names = "tx", "rx";
885 #address-cells = <1>;
886 #size-cells = <0>;
891 compatible = "qcom,geni-spi";
893 clock-names = "se";
898 dma-names = "tx", "rx";
899 power-domains = <&rpmhpd SM8250_CX>;
900 operating-points-v2 = <&qup_opp_table>;
901 #address-cells = <1>;
902 #size-cells = <0>;
907 compatible = "qcom,geni-debug-uart";
909 clock-names = "se";
911 pinctrl-names = "default";
912 pinctrl-0 = <&qup_uart2_default>;
914 power-domains = <&rpmhpd SM8250_CX>;
915 operating-points-v2 = <&qup_opp_table>;
920 compatible = "qcom,geni-i2c";
922 clock-names = "se";
924 pinctrl-names = "default";
925 pinctrl-0 = <&qup_i2c3_default>;
929 dma-names = "tx", "rx";
930 #address-cells = <1>;
931 #size-cells = <0>;
936 compatible = "qcom,geni-spi";
938 clock-names = "se";
943 dma-names = "tx", "rx";
944 power-domains = <&rpmhpd SM8250_CX>;
945 operating-points-v2 = <&qup_opp_table>;
946 #address-cells = <1>;
947 #size-cells = <0>;
952 compatible = "qcom,geni-i2c";
954 clock-names = "se";
956 pinctrl-names = "default";
957 pinctrl-0 = <&qup_i2c4_default>;
961 dma-names = "tx", "rx";
962 #address-cells = <1>;
963 #size-cells = <0>;
968 compatible = "qcom,geni-spi";
970 clock-names = "se";
975 dma-names = "tx", "rx";
976 power-domains = <&rpmhpd SM8250_CX>;
977 operating-points-v2 = <&qup_opp_table>;
978 #address-cells = <1>;
979 #size-cells = <0>;
984 compatible = "qcom,geni-i2c";
986 clock-names = "se";
988 pinctrl-names = "default";
989 pinctrl-0 = <&qup_i2c5_default>;
993 dma-names = "tx", "rx";
994 #address-cells = <1>;
995 #size-cells = <0>;
1000 compatible = "qcom,geni-spi";
1002 clock-names = "se";
1007 dma-names = "tx", "rx";
1008 power-domains = <&rpmhpd SM8250_CX>;
1009 operating-points-v2 = <&qup_opp_table>;
1010 #address-cells = <1>;
1011 #size-cells = <0>;
1016 compatible = "qcom,geni-i2c";
1018 clock-names = "se";
1020 pinctrl-names = "default";
1021 pinctrl-0 = <&qup_i2c6_default>;
1025 dma-names = "tx", "rx";
1026 #address-cells = <1>;
1027 #size-cells = <0>;
1032 compatible = "qcom,geni-spi";
1034 clock-names = "se";
1039 dma-names = "tx", "rx";
1040 power-domains = <&rpmhpd SM8250_CX>;
1041 operating-points-v2 = <&qup_opp_table>;
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1048 compatible = "qcom,geni-uart";
1050 clock-names = "se";
1052 pinctrl-names = "default";
1053 pinctrl-0 = <&qup_uart6_default>;
1055 power-domains = <&rpmhpd SM8250_CX>;
1056 operating-points-v2 = <&qup_opp_table>;
1061 compatible = "qcom,geni-i2c";
1063 clock-names = "se";
1065 pinctrl-names = "default";
1066 pinctrl-0 = <&qup_i2c7_default>;
1070 dma-names = "tx", "rx";
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1077 compatible = "qcom,geni-spi";
1079 clock-names = "se";
1084 dma-names = "tx", "rx";
1085 power-domains = <&rpmhpd SM8250_CX>;
1086 operating-points-v2 = <&qup_opp_table>;
1087 #address-cells = <1>;
1088 #size-cells = <0>;
1093 gpi_dma1: dma-controller@a00000 {
1094 compatible = "qcom,sm8250-gpi-dma";
1106 dma-channels = <10>;
1107 dma-channel-mask = <0x3f>;
1109 #dma-cells = <3>;
1114 compatible = "qcom,geni-se-qup";
1116 clock-names = "m-ahb", "s-ahb";
1119 #address-cells = <2>;
1120 #size-cells = <2>;
1126 compatible = "qcom,geni-i2c";
1128 clock-names = "se";
1130 pinctrl-names = "default";
1131 pinctrl-0 = <&qup_i2c8_default>;
1135 dma-names = "tx", "rx";
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1142 compatible = "qcom,geni-spi";
1144 clock-names = "se";
1149 dma-names = "tx", "rx";
1150 power-domains = <&rpmhpd SM8250_CX>;
1151 operating-points-v2 = <&qup_opp_table>;
1152 #address-cells = <1>;
1153 #size-cells = <0>;
1158 compatible = "qcom,geni-i2c";
1160 clock-names = "se";
1162 pinctrl-names = "default";
1163 pinctrl-0 = <&qup_i2c9_default>;
1167 dma-names = "tx", "rx";
1168 #address-cells = <1>;
1169 #size-cells = <0>;
1174 compatible = "qcom,geni-spi";
1176 clock-names = "se";
1181 dma-names = "tx", "rx";
1182 power-domains = <&rpmhpd SM8250_CX>;
1183 operating-points-v2 = <&qup_opp_table>;
1184 #address-cells = <1>;
1185 #size-cells = <0>;
1190 compatible = "qcom,geni-i2c";
1192 clock-names = "se";
1194 pinctrl-names = "default";
1195 pinctrl-0 = <&qup_i2c10_default>;
1199 dma-names = "tx", "rx";
1200 #address-cells = <1>;
1201 #size-cells = <0>;
1206 compatible = "qcom,geni-spi";
1208 clock-names = "se";
1213 dma-names = "tx", "rx";
1214 power-domains = <&rpmhpd SM8250_CX>;
1215 operating-points-v2 = <&qup_opp_table>;
1216 #address-cells = <1>;
1217 #size-cells = <0>;
1222 compatible = "qcom,geni-i2c";
1224 clock-names = "se";
1226 pinctrl-names = "default";
1227 pinctrl-0 = <&qup_i2c11_default>;
1231 dma-names = "tx", "rx";
1232 #address-cells = <1>;
1233 #size-cells = <0>;
1238 compatible = "qcom,geni-spi";
1240 clock-names = "se";
1245 dma-names = "tx", "rx";
1246 power-domains = <&rpmhpd SM8250_CX>;
1247 operating-points-v2 = <&qup_opp_table>;
1248 #address-cells = <1>;
1249 #size-cells = <0>;
1254 compatible = "qcom,geni-i2c";
1256 clock-names = "se";
1258 pinctrl-names = "default";
1259 pinctrl-0 = <&qup_i2c12_default>;
1263 dma-names = "tx", "rx";
1264 #address-cells = <1>;
1265 #size-cells = <0>;
1270 compatible = "qcom,geni-spi";
1272 clock-names = "se";
1277 dma-names = "tx", "rx";
1278 power-domains = <&rpmhpd SM8250_CX>;
1279 operating-points-v2 = <&qup_opp_table>;
1280 #address-cells = <1>;
1281 #size-cells = <0>;
1286 compatible = "qcom,geni-debug-uart";
1288 clock-names = "se";
1290 pinctrl-names = "default";
1291 pinctrl-0 = <&qup_uart12_default>;
1293 power-domains = <&rpmhpd SM8250_CX>;
1294 operating-points-v2 = <&qup_opp_table>;
1299 compatible = "qcom,geni-i2c";
1301 clock-names = "se";
1303 pinctrl-names = "default";
1304 pinctrl-0 = <&qup_i2c13_default>;
1308 dma-names = "tx", "rx";
1309 #address-cells = <1>;
1310 #size-cells = <0>;
1315 compatible = "qcom,geni-spi";
1317 clock-names = "se";
1322 dma-names = "tx", "rx";
1323 power-domains = <&rpmhpd SM8250_CX>;
1324 operating-points-v2 = <&qup_opp_table>;
1325 #address-cells = <1>;
1326 #size-cells = <0>;
1332 compatible = "qcom,sm8250-config-noc";
1334 #interconnect-cells = <1>;
1335 qcom,bcm-voters = <&apps_bcm_voter>;
1339 compatible = "qcom,sm8250-system-noc";
1341 #interconnect-cells = <1>;
1342 qcom,bcm-voters = <&apps_bcm_voter>;
1346 compatible = "qcom,sm8250-mc-virt";
1348 #interconnect-cells = <1>;
1349 qcom,bcm-voters = <&apps_bcm_voter>;
1353 compatible = "qcom,sm8250-aggre1-noc";
1355 #interconnect-cells = <1>;
1356 qcom,bcm-voters = <&apps_bcm_voter>;
1360 compatible = "qcom,sm8250-aggre2-noc";
1362 #interconnect-cells = <1>;
1363 qcom,bcm-voters = <&apps_bcm_voter>;
1367 compatible = "qcom,sm8250-compute-noc";
1369 #interconnect-cells = <1>;
1370 qcom,bcm-voters = <&apps_bcm_voter>;
1374 compatible = "qcom,sm8250-mmss-noc";
1376 #interconnect-cells = <1>;
1377 qcom,bcm-voters = <&apps_bcm_voter>;
1381 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1387 reg-names = "parf", "dbi", "elbi", "atu", "config";
1389 linux,pci-domain = <0>;
1390 bus-range = <0x00 0xff>;
1391 num-lanes = <1>;
1393 #address-cells = <3>;
1394 #size-cells = <2>;
1400 interrupt-names = "msi";
1401 #interrupt-cells = <1>;
1402 interrupt-map-mask = <0 0 0 0x7>;
1403 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1416 clock-names = "pipe",
1426 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1430 reset-names = "pci";
1432 power-domains = <&gcc PCIE_0_GDSC>;
1435 phy-names = "pciephy";
1437 perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>;
1438 enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
1440 pinctrl-names = "default";
1441 pinctrl-0 = <&pcie0_default_state>;
1447 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
1449 #address-cells = <2>;
1450 #size-cells = <2>;
1456 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1459 reset-names = "phy";
1461 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1462 assigned-clock-rates = <100000000>;
1472 clock-names = "pipe0";
1474 #phy-cells = <0>;
1475 clock-output-names = "pcie_0_pipe_clk";
1480 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1486 reg-names = "parf", "dbi", "elbi", "atu", "config";
1488 linux,pci-domain = <1>;
1489 bus-range = <0x00 0xff>;
1490 num-lanes = <2>;
1492 #address-cells = <3>;
1493 #size-cells = <2>;
1499 interrupt-names = "msi";
1500 #interrupt-cells = <1>;
1501 interrupt-map-mask = <0 0 0 0x7>;
1502 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1516 clock-names = "pipe",
1526 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1527 assigned-clock-rates = <19200000>;
1530 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1534 reset-names = "pci";
1536 power-domains = <&gcc PCIE_1_GDSC>;
1539 phy-names = "pciephy";
1541 perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>;
1542 enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>;
1544 pinctrl-names = "default";
1545 pinctrl-0 = <&pcie1_default_state>;
1551 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
1553 #address-cells = <2>;
1554 #size-cells = <2>;
1560 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1563 reset-names = "phy";
1565 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1566 assigned-clock-rates = <100000000>;
1578 clock-names = "pipe0";
1580 #phy-cells = <0>;
1581 clock-output-names = "pcie_1_pipe_clk";
1586 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1592 reg-names = "parf", "dbi", "elbi", "atu", "config";
1594 linux,pci-domain = <2>;
1595 bus-range = <0x00 0xff>;
1596 num-lanes = <2>;
1598 #address-cells = <3>;
1599 #size-cells = <2>;
1605 interrupt-names = "msi";
1606 #interrupt-cells = <1>;
1607 interrupt-map-mask = <0 0 0 0x7>;
1608 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1622 clock-names = "pipe",
1632 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
1633 assigned-clock-rates = <19200000>;
1636 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
1640 reset-names = "pci";
1642 power-domains = <&gcc PCIE_2_GDSC>;
1645 phy-names = "pciephy";
1647 perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>;
1648 enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>;
1650 pinctrl-names = "default";
1651 pinctrl-0 = <&pcie2_default_state>;
1657 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
1659 #address-cells = <2>;
1660 #size-cells = <2>;
1666 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1669 reset-names = "phy";
1671 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
1672 assigned-clock-rates = <100000000>;
1684 clock-names = "pipe0";
1686 #phy-cells = <0>;
1687 clock-output-names = "pcie_2_pipe_clk";
1692 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
1693 "jedec,ufs-2.0";
1697 phy-names = "ufsphy";
1698 lanes-per-direction = <2>;
1699 #reset-cells = <1>;
1701 reset-names = "rst";
1703 power-domains = <&gcc UFS_PHY_GDSC>;
1707 clock-names =
1725 freq-table-hz =
1739 compatible = "qcom,sm8250-qmp-ufs-phy";
1741 #address-cells = <2>;
1742 #size-cells = <2>;
1744 clock-names = "ref",
1750 reset-names = "ufsphy";
1759 #phy-cells = <0>;
1764 compatible = "qcom,sm8250-ipa-virt";
1766 #interconnect-cells = <1>;
1767 qcom,bcm-voters = <&apps_bcm_voter>;
1771 compatible = "qcom,tcsr-mutex";
1773 #hwlock-cells = <1>;
1777 compatible = "qcom,sm8250-lpass-wsa-macro";
1786 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
1788 #clock-cells = <0>;
1789 clock-frequency = <9600000>;
1790 clock-output-names = "mclk";
1791 #sound-dai-cells = <1>;
1793 pinctrl-names = "default";
1794 pinctrl-0 = <&wsa_swr_active>;
1797 swr0: soundwire-controller@3250000 {
1799 compatible = "qcom,soundwire-v1.5.1";
1802 clock-names = "iface";
1804 qcom,din-ports = <2>;
1805 qcom,dout-ports = <6>;
1807 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
1808 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
1809 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
1810 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
1812 #sound-dai-cells = <1>;
1813 #address-cells = <2>;
1814 #size-cells = <0>;
1817 audiocc: clock-controller@3300000 {
1818 compatible = "qcom,sm8250-lpass-audiocc";
1820 #clock-cells = <1>;
1824 clock-names = "core", "audio", "bus";
1828 compatible = "qcom,sm8250-lpass-va-macro";
1834 clock-names = "mclk", "macro", "dcodec";
1836 #clock-cells = <0>;
1837 clock-frequency = <9600000>;
1838 clock-output-names = "fsgen";
1839 #sound-dai-cells = <1>;
1842 aoncc: clock-controller@3380000 {
1843 compatible = "qcom,sm8250-lpass-aoncc";
1845 #clock-cells = <1>;
1849 clock-names = "core", "audio", "bus";
1853 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
1856 gpio-controller;
1857 #gpio-cells = <2>;
1858 gpio-ranges = <&lpass_tlmm 0 0 14>;
1862 clock-names = "core", "audio";
1864 wsa_swr_active: wsa-swr-active-pins {
1868 drive-strength = <2>;
1869 slew-rate = <1>;
1870 bias-disable;
1876 drive-strength = <2>;
1877 slew-rate = <1>;
1878 bias-bus-hold;
1883 wsa_swr_sleep: wsa-swr-sleep-pins {
1887 drive-strength = <2>;
1888 input-enable;
1889 bias-pull-down;
1895 drive-strength = <2>;
1896 input-enable;
1897 bias-pull-down;
1902 dmic01_active: dmic01-active-pins {
1906 drive-strength = <8>;
1907 output-high;
1912 drive-strength = <8>;
1913 input-enable;
1917 dmic01_sleep: dmic01-sleep-pins {
1921 drive-strength = <2>;
1922 bias-disable;
1923 output-low;
1929 drive-strength = <2>;
1930 pull-down;
1931 input-enable;
1937 compatible = "qcom,adreno-650.2",
1938 "qcom,adreno";
1939 #stream-id-cells = <16>;
1942 reg-names = "kgsl_3d0_reg_memory";
1948 operating-points-v2 = <&gpu_opp_table>;
1950 qcom,gmu = <&gmu>;
1954 zap-shader {
1955 memory-region = <&gpu_mem>;
1959 gpu_opp_table: opp-table {
1960 compatible = "operating-points-v2";
1962 opp-670000000 {
1963 opp-hz = /bits/ 64 <670000000>;
1964 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1967 opp-587000000 {
1968 opp-hz = /bits/ 64 <587000000>;
1969 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1972 opp-525000000 {
1973 opp-hz = /bits/ 64 <525000000>;
1974 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1977 opp-490000000 {
1978 opp-hz = /bits/ 64 <490000000>;
1979 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1982 opp-441600000 {
1983 opp-hz = /bits/ 64 <441600000>;
1984 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1987 opp-400000000 {
1988 opp-hz = /bits/ 64 <400000000>;
1989 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1992 opp-305000000 {
1993 opp-hz = /bits/ 64 <305000000>;
1994 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2000 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2006 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2010 interrupt-names = "hfi", "gmu";
2017 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2019 power-domains = <&gpucc GPU_CX_GDSC>,
2021 power-domain-names = "cx", "gx";
2025 operating-points-v2 = <&gmu_opp_table>;
2029 gmu_opp_table: opp-table {
2030 compatible = "operating-points-v2";
2032 opp-200000000 {
2033 opp-hz = /bits/ 64 <200000000>;
2034 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2039 gpucc: clock-controller@3d90000 {
2040 compatible = "qcom,sm8250-gpucc";
2045 clock-names = "bi_tcxo",
2048 #clock-cells = <1>;
2049 #reset-cells = <1>;
2050 #power-domain-cells = <1>;
2054 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
2056 #iommu-cells = <2>;
2057 #global-interrupts = <2>;
2071 clock-names = "ahb", "bus", "iface";
2073 power-domains = <&gpucc GPU_CX_GDSC>;
2077 compatible = "qcom,sm8250-slpi-pas";
2080 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2085 interrupt-names = "wdog", "fatal", "ready",
2086 "handover", "stop-ack";
2089 clock-names = "xo";
2091 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
2094 power-domain-names = "load_state", "lcx", "lmx";
2096 memory-region = <&slpi_mem>;
2098 qcom,smem-states = <&smp2p_slpi_out 0>;
2099 qcom,smem-state-names = "stop";
2103 glink-edge {
2104 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2111 qcom,remote-pid = <3>;
2114 compatible = "qcom,fastrpc";
2115 qcom,glink-channels = "fastrpcglink-apps-dsp";
2117 #address-cells = <1>;
2118 #size-cells = <0>;
2120 compute-cb@1 {
2121 compatible = "qcom,fastrpc-compute-cb";
2126 compute-cb@2 {
2127 compatible = "qcom,fastrpc-compute-cb";
2132 compute-cb@3 {
2133 compatible = "qcom,fastrpc-compute-cb";
2136 /* note: shared-cb = <4> in downstream */
2143 compatible = "qcom,sm8250-cdsp-pas";
2146 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2151 interrupt-names = "wdog", "fatal", "ready",
2152 "handover", "stop-ack";
2155 clock-names = "xo";
2157 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
2159 power-domain-names = "load_state", "cx";
2161 memory-region = <&cdsp_mem>;
2163 qcom,smem-states = <&smp2p_cdsp_out 0>;
2164 qcom,smem-state-names = "stop";
2168 glink-edge {
2169 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2176 qcom,remote-pid = <5>;
2179 compatible = "qcom,fastrpc";
2180 qcom,glink-channels = "fastrpcglink-apps-dsp";
2182 #address-cells = <1>;
2183 #size-cells = <0>;
2185 compute-cb@1 {
2186 compatible = "qcom,fastrpc-compute-cb";
2191 compute-cb@2 {
2192 compatible = "qcom,fastrpc-compute-cb";
2197 compute-cb@3 {
2198 compatible = "qcom,fastrpc-compute-cb";
2203 compute-cb@4 {
2204 compatible = "qcom,fastrpc-compute-cb";
2209 compute-cb@5 {
2210 compatible = "qcom,fastrpc-compute-cb";
2215 compute-cb@6 {
2216 compatible = "qcom,fastrpc-compute-cb";
2221 compute-cb@7 {
2222 compatible = "qcom,fastrpc-compute-cb";
2227 compute-cb@8 {
2228 compatible = "qcom,fastrpc-compute-cb";
2242 compatible = "qcom,sm8250-usb-hs-phy",
2243 "qcom,usb-snps-hs-7nm-phy";
2246 #phy-cells = <0>;
2249 clock-names = "ref";
2255 compatible = "qcom,sm8250-usb-hs-phy",
2256 "qcom,usb-snps-hs-7nm-phy";
2259 #phy-cells = <0>;
2262 clock-names = "ref";
2268 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
2273 #address-cells = <2>;
2274 #size-cells = <2>;
2280 clock-names = "aux", "ref_clk_src", "com_aux";
2284 reset-names = "phy", "common";
2286 usb_1_ssphy: usb3-phy@88e9200 {
2293 #clock-cells = <0>;
2294 #phy-cells = <0>;
2296 clock-names = "pipe0";
2297 clock-output-names = "usb3_phy_pipe_clk_src";
2300 dp_phy: dp-phy@88ea200 {
2307 #phy-cells = <0>;
2308 #clock-cells = <1>;
2310 clock-names = "pipe0";
2311 clock-output-names = "usb3_phy_pipe_clk_src";
2316 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
2319 #address-cells = <2>;
2320 #size-cells = <2>;
2327 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2331 reset-names = "phy", "common";
2337 #clock-cells = <0>;
2338 #phy-cells = <0>;
2340 clock-names = "pipe0";
2341 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2346 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
2351 interrupt-names = "hc_irq", "pwr_irq";
2356 clock-names = "iface", "core", "xo";
2358 qcom,dll-config = <0x0007642c>;
2359 qcom,ddr-config = <0x80040868>;
2360 power-domains = <&rpmhpd SM8250_CX>;
2361 operating-points-v2 = <&sdhc2_opp_table>;
2365 sdhc2_opp_table: sdhc2-opp-table {
2366 compatible = "operating-points-v2";
2368 opp-19200000 {
2369 opp-hz = /bits/ 64 <19200000>;
2370 required-opps = <&rpmhpd_opp_min_svs>;
2373 opp-50000000 {
2374 opp-hz = /bits/ 64 <50000000>;
2375 required-opps = <&rpmhpd_opp_low_svs>;
2378 opp-100000000 {
2379 opp-hz = /bits/ 64 <100000000>;
2380 required-opps = <&rpmhpd_opp_svs>;
2383 opp-202000000 {
2384 opp-hz = /bits/ 64 <202000000>;
2385 required-opps = <&rpmhpd_opp_svs_l1>;
2391 compatible = "qcom,sm8250-dc-noc";
2393 #interconnect-cells = <1>;
2394 qcom,bcm-voters = <&apps_bcm_voter>;
2398 compatible = "qcom,sm8250-gem-noc";
2400 #interconnect-cells = <1>;
2401 qcom,bcm-voters = <&apps_bcm_voter>;
2405 compatible = "qcom,sm8250-npu-noc";
2407 #interconnect-cells = <1>;
2408 qcom,bcm-voters = <&apps_bcm_voter>;
2412 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
2415 #address-cells = <2>;
2416 #size-cells = <2>;
2418 dma-ranges;
2426 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2429 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2431 assigned-clock-rates = <19200000>, <200000000>;
2433 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2437 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2440 power-domains = <&gcc USB30_PRIM_GDSC>;
2452 phy-names = "usb2-phy", "usb3-phy";
2456 system-cache-controller@9200000 {
2457 compatible = "qcom,sm8250-llcc";
2459 reg-names = "llcc_base", "llcc_broadcast_base";
2463 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
2466 #address-cells = <2>;
2467 #size-cells = <2>;
2469 dma-ranges;
2477 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2480 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2482 assigned-clock-rates = <19200000>, <200000000>;
2484 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2488 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2491 power-domains = <&gcc USB30_SEC_GDSC>;
2503 phy-names = "usb2-phy", "usb3-phy";
2507 venus: video-codec@aa00000 {
2508 compatible = "qcom,sm8250-venus";
2511 power-domains = <&videocc MVS0C_GDSC>,
2514 power-domain-names = "venus", "vcodec0", "mx";
2515 operating-points-v2 = <&venus_opp_table>;
2520 clock-names = "iface", "core", "vcodec0_core";
2524 interconnect-names = "cpu-cfg", "video-mem";
2527 memory-region = <&video_mem>;
2531 reset-names = "bus", "core";
2535 video-decoder {
2536 compatible = "venus-decoder";
2539 video-encoder {
2540 compatible = "venus-encoder";
2543 venus_opp_table: venus-opp-table {
2544 compatible = "operating-points-v2";
2546 opp-720000000 {
2547 opp-hz = /bits/ 64 <720000000>;
2548 required-opps = <&rpmhpd_opp_low_svs>;
2551 opp-1014000000 {
2552 opp-hz = /bits/ 64 <1014000000>;
2553 required-opps = <&rpmhpd_opp_svs>;
2556 opp-1098000000 {
2557 opp-hz = /bits/ 64 <1098000000>;
2558 required-opps = <&rpmhpd_opp_svs_l1>;
2561 opp-1332000000 {
2562 opp-hz = /bits/ 64 <1332000000>;
2563 required-opps = <&rpmhpd_opp_nom>;
2568 videocc: clock-controller@abf0000 {
2569 compatible = "qcom,sm8250-videocc";
2574 mmcx-supply = <&mmcx_reg>;
2575 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
2576 #clock-cells = <1>;
2577 #reset-cells = <1>;
2578 #power-domain-cells = <1>;
2582 compatible = "qcom,sm8250-mdss";
2584 reg-names = "mdss";
2588 interconnect-names = "mdp0-mem", "mdp1-mem";
2590 power-domains = <&dispcc MDSS_GDSC>;
2596 clock-names = "iface", "bus", "nrt_bus", "core";
2598 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2599 assigned-clock-rates = <460000000>;
2602 interrupt-controller;
2603 #interrupt-cells = <1>;
2609 #address-cells = <2>;
2610 #size-cells = <2>;
2614 compatible = "qcom,sm8250-dpu";
2617 reg-names = "mdp", "vbif";
2623 clock-names = "iface", "bus", "core", "vsync";
2625 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2627 assigned-clock-rates = <460000000>,
2630 operating-points-v2 = <&mdp_opp_table>;
2631 power-domains = <&rpmhpd SM8250_MMCX>;
2633 interrupt-parent = <&mdss>;
2637 #address-cells = <1>;
2638 #size-cells = <0>;
2643 remote-endpoint = <&dsi0_in>;
2650 remote-endpoint = <&dsi1_in>;
2655 mdp_opp_table: mdp-opp-table {
2656 compatible = "operating-points-v2";
2658 opp-200000000 {
2659 opp-hz = /bits/ 64 <200000000>;
2660 required-opps = <&rpmhpd_opp_low_svs>;
2663 opp-300000000 {
2664 opp-hz = /bits/ 64 <300000000>;
2665 required-opps = <&rpmhpd_opp_svs>;
2668 opp-345000000 {
2669 opp-hz = /bits/ 64 <345000000>;
2670 required-opps = <&rpmhpd_opp_svs_l1>;
2673 opp-460000000 {
2674 opp-hz = /bits/ 64 <460000000>;
2675 required-opps = <&rpmhpd_opp_nom>;
2681 compatible = "qcom,mdss-dsi-ctrl";
2683 reg-names = "dsi_ctrl";
2685 interrupt-parent = <&mdss>;
2694 clock-names = "byte",
2701 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2702 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
2704 operating-points-v2 = <&dsi_opp_table>;
2705 power-domains = <&rpmhpd SM8250_MMCX>;
2708 phy-names = "dsi";
2712 #address-cells = <1>;
2713 #size-cells = <0>;
2716 #address-cells = <1>;
2717 #size-cells = <0>;
2722 remote-endpoint = <&dpu_intf1_out>;
2734 dsi0_phy: dsi-phy@ae94400 {
2735 compatible = "qcom,dsi-phy-7nm";
2739 reg-names = "dsi_phy",
2743 #clock-cells = <1>;
2744 #phy-cells = <0>;
2748 clock-names = "iface", "ref";
2754 compatible = "qcom,mdss-dsi-ctrl";
2756 reg-names = "dsi_ctrl";
2758 interrupt-parent = <&mdss>;
2767 clock-names = "byte",
2774 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
2775 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
2777 operating-points-v2 = <&dsi_opp_table>;
2778 power-domains = <&rpmhpd SM8250_MMCX>;
2781 phy-names = "dsi";
2785 #address-cells = <1>;
2786 #size-cells = <0>;
2789 #address-cells = <1>;
2790 #size-cells = <0>;
2795 remote-endpoint = <&dpu_intf2_out>;
2807 dsi1_phy: dsi-phy@ae96400 {
2808 compatible = "qcom,dsi-phy-7nm";
2812 reg-names = "dsi_phy",
2816 #clock-cells = <1>;
2817 #phy-cells = <0>;
2821 clock-names = "iface", "ref";
2825 dsi_opp_table: dsi-opp-table {
2826 compatible = "operating-points-v2";
2828 opp-187500000 {
2829 opp-hz = /bits/ 64 <187500000>;
2830 required-opps = <&rpmhpd_opp_low_svs>;
2833 opp-300000000 {
2834 opp-hz = /bits/ 64 <300000000>;
2835 required-opps = <&rpmhpd_opp_svs>;
2838 opp-358000000 {
2839 opp-hz = /bits/ 64 <358000000>;
2840 required-opps = <&rpmhpd_opp_svs_l1>;
2846 dispcc: clock-controller@af00000 {
2847 compatible = "qcom,sm8250-dispcc";
2849 mmcx-supply = <&mmcx_reg>;
2857 clock-names = "bi_tcxo",
2864 #clock-cells = <1>;
2865 #reset-cells = <1>;
2866 #power-domain-cells = <1>;
2869 pdc: interrupt-controller@b220000 {
2870 compatible = "qcom,sm8250-pdc", "qcom,pdc";
2872 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2874 #interrupt-cells = <2>;
2875 interrupt-parent = <&intc>;
2876 interrupt-controller;
2879 tsens0: thermal-sensor@c263000 {
2880 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
2883 #qcom,sensors = <16>;
2886 interrupt-names = "uplow", "critical";
2887 #thermal-sensor-cells = <1>;
2890 tsens1: thermal-sensor@c265000 {
2891 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
2894 #qcom,sensors = <9>;
2897 interrupt-names = "uplow", "critical";
2898 #thermal-sensor-cells = <1>;
2901 aoss_qmp: power-controller@c300000 {
2902 compatible = "qcom,sm8250-aoss-qmp";
2904 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
2910 #clock-cells = <0>;
2911 #power-domain-cells = <1>;
2915 compatible = "qcom,spmi-pmic-arb";
2921 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2922 interrupt-names = "periph_irq";
2923 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2924 qcom,ee = <0>;
2925 qcom,channel = <0>;
2926 #address-cells = <2>;
2927 #size-cells = <0>;
2928 interrupt-controller;
2929 #interrupt-cells = <4>;
2933 compatible = "qcom,sm8250-pinctrl";
2937 reg-names = "west", "south", "north";
2939 gpio-controller;
2940 #gpio-cells = <2>;
2941 interrupt-controller;
2942 #interrupt-cells = <2>;
2943 gpio-ranges = <&tlmm 0 0 181>;
2944 wakeup-parent = <&pdc>;
2946 pri_mi2s_active: pri-mi2s-active {
2950 drive-strength = <8>;
2951 bias-disable;
2957 drive-strength = <8>;
2958 output-high;
2964 drive-strength = <8>;
2965 bias-disable;
2966 output-high;
2972 drive-strength = <8>;
2973 output-high;
2977 qup_i2c0_default: qup-i2c0-default {
2985 drive-strength = <2>;
2986 bias-disable;
2990 qup_i2c1_default: qup-i2c1-default {
2998 drive-strength = <2>;
2999 bias-disable;
3003 qup_i2c2_default: qup-i2c2-default {
3011 drive-strength = <2>;
3012 bias-disable;
3016 qup_i2c3_default: qup-i2c3-default {
3024 drive-strength = <2>;
3025 bias-disable;
3029 qup_i2c4_default: qup-i2c4-default {
3037 drive-strength = <2>;
3038 bias-disable;
3042 qup_i2c5_default: qup-i2c5-default {
3050 drive-strength = <2>;
3051 bias-disable;
3055 qup_i2c6_default: qup-i2c6-default {
3063 drive-strength = <2>;
3064 bias-disable;
3068 qup_i2c7_default: qup-i2c7-default {
3076 drive-strength = <2>;
3077 bias-disable;
3081 qup_i2c8_default: qup-i2c8-default {
3089 drive-strength = <2>;
3090 bias-disable;
3094 qup_i2c9_default: qup-i2c9-default {
3102 drive-strength = <2>;
3103 bias-disable;
3107 qup_i2c10_default: qup-i2c10-default {
3115 drive-strength = <2>;
3116 bias-disable;
3120 qup_i2c11_default: qup-i2c11-default {
3128 drive-strength = <2>;
3129 bias-disable;
3133 qup_i2c12_default: qup-i2c12-default {
3141 drive-strength = <2>;
3142 bias-disable;
3146 qup_i2c13_default: qup-i2c13-default {
3154 drive-strength = <2>;
3155 bias-disable;
3159 qup_i2c14_default: qup-i2c14-default {
3167 drive-strength = <2>;
3168 bias-disable;
3172 qup_i2c15_default: qup-i2c15-default {
3180 drive-strength = <2>;
3181 bias-disable;
3185 qup_i2c16_default: qup-i2c16-default {
3193 drive-strength = <2>;
3194 bias-disable;
3198 qup_i2c17_default: qup-i2c17-default {
3206 drive-strength = <2>;
3207 bias-disable;
3211 qup_i2c18_default: qup-i2c18-default {
3219 drive-strength = <2>;
3220 bias-disable;
3224 qup_i2c19_default: qup-i2c19-default {
3232 drive-strength = <2>;
3233 bias-disable;
3237 qup_spi0_cs: qup-spi0-cs {
3242 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
3247 qup_spi0_data_clk: qup-spi0-data-clk {
3253 qup_spi1_cs: qup-spi1-cs {
3258 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
3263 qup_spi1_data_clk: qup-spi1-data-clk {
3269 qup_spi2_cs: qup-spi2-cs {
3274 qup_spi2_cs_gpio: qup-spi2-cs-gpio {
3279 qup_spi2_data_clk: qup-spi2-data-clk {
3285 qup_spi3_cs: qup-spi3-cs {
3290 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
3295 qup_spi3_data_clk: qup-spi3-data-clk {
3301 qup_spi4_cs: qup-spi4-cs {
3306 qup_spi4_cs_gpio: qup-spi4-cs-gpio {
3311 qup_spi4_data_clk: qup-spi4-data-clk {
3317 qup_spi5_cs: qup-spi5-cs {
3322 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
3327 qup_spi5_data_clk: qup-spi5-data-clk {
3333 qup_spi6_cs: qup-spi6-cs {
3338 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
3343 qup_spi6_data_clk: qup-spi6-data-clk {
3349 qup_spi7_cs: qup-spi7-cs {
3354 qup_spi7_cs_gpio: qup-spi7-cs-gpio {
3359 qup_spi7_data_clk: qup-spi7-data-clk {
3365 qup_spi8_cs: qup-spi8-cs {
3370 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
3375 qup_spi8_data_clk: qup-spi8-data-clk {
3381 qup_spi9_cs: qup-spi9-cs {
3386 qup_spi9_cs_gpio: qup-spi9-cs-gpio {
3391 qup_spi9_data_clk: qup-spi9-data-clk {
3397 qup_spi10_cs: qup-spi10-cs {
3402 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
3407 qup_spi10_data_clk: qup-spi10-data-clk {
3413 qup_spi11_cs: qup-spi11-cs {
3418 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
3423 qup_spi11_data_clk: qup-spi11-data-clk {
3429 qup_spi12_cs: qup-spi12-cs {
3434 qup_spi12_cs_gpio: qup-spi12-cs-gpio {
3439 qup_spi12_data_clk: qup-spi12-data-clk {
3445 qup_spi13_cs: qup-spi13-cs {
3450 qup_spi13_cs_gpio: qup-spi13-cs-gpio {
3455 qup_spi13_data_clk: qup-spi13-data-clk {
3461 qup_spi14_cs: qup-spi14-cs {
3466 qup_spi14_cs_gpio: qup-spi14-cs-gpio {
3471 qup_spi14_data_clk: qup-spi14-data-clk {
3477 qup_spi15_cs: qup-spi15-cs {
3482 qup_spi15_cs_gpio: qup-spi15-cs-gpio {
3487 qup_spi15_data_clk: qup-spi15-data-clk {
3493 qup_spi16_cs: qup-spi16-cs {
3498 qup_spi16_cs_gpio: qup-spi16-cs-gpio {
3503 qup_spi16_data_clk: qup-spi16-data-clk {
3509 qup_spi17_cs: qup-spi17-cs {
3514 qup_spi17_cs_gpio: qup-spi17-cs-gpio {
3519 qup_spi17_data_clk: qup-spi17-data-clk {
3525 qup_spi18_cs: qup-spi18-cs {
3530 qup_spi18_cs_gpio: qup-spi18-cs-gpio {
3535 qup_spi18_data_clk: qup-spi18-data-clk {
3541 qup_spi19_cs: qup-spi19-cs {
3546 qup_spi19_cs_gpio: qup-spi19-cs-gpio {
3551 qup_spi19_data_clk: qup-spi19-data-clk {
3557 qup_uart2_default: qup-uart2-default {
3564 qup_uart6_default: qup-uart6-default {
3572 qup_uart12_default: qup-uart12-default {
3579 qup_uart17_default: qup-uart17-default {
3587 qup_uart18_default: qup-uart18-default {
3594 tert_mi2s_active: tert-mi2s-active {
3598 drive-strength = <8>;
3599 bias-disable;
3605 drive-strength = <8>;
3606 bias-disable;
3607 output-high;
3613 drive-strength = <8>;
3614 output-high;
3618 sdc2_sleep_state: sdc2-sleep {
3621 drive-strength = <2>;
3622 bias-disable;
3627 drive-strength = <2>;
3628 bias-pull-up;
3633 drive-strength = <2>;
3634 bias-pull-up;
3638 pcie0_default_state: pcie0-default {
3642 drive-strength = <2>;
3643 bias-pull-down;
3649 drive-strength = <2>;
3650 bias-pull-up;
3656 drive-strength = <2>;
3657 bias-pull-up;
3661 pcie1_default_state: pcie1-default {
3665 drive-strength = <2>;
3666 bias-pull-down;
3672 drive-strength = <2>;
3673 bias-pull-up;
3679 drive-strength = <2>;
3680 bias-pull-up;
3684 pcie2_default_state: pcie2-default {
3688 drive-strength = <2>;
3689 bias-pull-down;
3695 drive-strength = <2>;
3696 bias-pull-up;
3702 drive-strength = <2>;
3703 bias-pull-up;
3709 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
3711 #iommu-cells = <2>;
3712 #global-interrupts = <2>;
3814 compatible = "qcom,sm8250-adsp-pas";
3817 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3822 interrupt-names = "wdog", "fatal", "ready",
3823 "handover", "stop-ack";
3826 clock-names = "xo";
3828 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
3831 power-domain-names = "load_state", "lcx", "lmx";
3833 memory-region = <&adsp_mem>;
3835 qcom,smem-states = <&smp2p_adsp_out 0>;
3836 qcom,smem-state-names = "stop";
3840 glink-edge {
3841 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3848 qcom,remote-pid = <2>;
3851 compatible = "qcom,apr-v2";
3852 qcom,glink-channels = "apr_audio_svc";
3853 qcom,apr-domain = <APR_DOMAIN_ADSP>;
3854 #address-cells = <1>;
3855 #size-cells = <0>;
3857 apr-service@3 {
3859 compatible = "qcom,q6core";
3860 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3863 q6afe: apr-service@4 {
3864 compatible = "qcom,q6afe";
3866 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3868 compatible = "qcom,q6afe-dais";
3869 #address-cells = <1>;
3870 #size-cells = <0>;
3871 #sound-dai-cells = <1>;
3875 compatible = "qcom,q6afe-clocks";
3876 #clock-cells = <2>;
3880 q6asm: apr-service@7 {
3881 compatible = "qcom,q6asm";
3883 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3885 compatible = "qcom,q6asm-dais";
3886 #address-cells = <1>;
3887 #size-cells = <0>;
3888 #sound-dai-cells = <1>;
3893 q6adm: apr-service@8 {
3894 compatible = "qcom,q6adm";
3896 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3898 compatible = "qcom,q6adm-routing";
3899 #sound-dai-cells = <0>;
3905 compatible = "qcom,fastrpc";
3906 qcom,glink-channels = "fastrpcglink-apps-dsp";
3908 #address-cells = <1>;
3909 #size-cells = <0>;
3911 compute-cb@3 {
3912 compatible = "qcom,fastrpc-compute-cb";
3917 compute-cb@4 {
3918 compatible = "qcom,fastrpc-compute-cb";
3923 compute-cb@5 {
3924 compatible = "qcom,fastrpc-compute-cb";
3932 intc: interrupt-controller@17a00000 {
3933 compatible = "arm,gic-v3";
3934 #interrupt-cells = <3>;
3935 interrupt-controller;
3942 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
3949 #address-cells = <2>;
3950 #size-cells = <2>;
3952 compatible = "arm,armv7-timer-mem";
3954 clock-frequency = <19200000>;
3957 frame-number = <0>;
3965 frame-number = <1>;
3972 frame-number = <2>;
3979 frame-number = <3>;
3986 frame-number = <4>;
3993 frame-number = <5>;
4000 frame-number = <6>;
4009 compatible = "qcom,rpmh-rsc";
4013 reg-names = "drv-0", "drv-1", "drv-2";
4017 qcom,tcs-offset = <0xd00>;
4018 qcom,drv-id = <2>;
4019 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
4022 rpmhcc: clock-controller {
4023 compatible = "qcom,sm8250-rpmh-clk";
4024 #clock-cells = <1>;
4025 clock-names = "xo";
4029 rpmhpd: power-controller {
4030 compatible = "qcom,sm8250-rpmhpd";
4031 #power-domain-cells = <1>;
4032 operating-points-v2 = <&rpmhpd_opp_table>;
4034 rpmhpd_opp_table: opp-table {
4035 compatible = "operating-points-v2";
4038 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4042 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4046 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4050 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4054 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4058 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4062 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4066 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4070 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4074 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4080 compatible = "qcom,bcm-voter";
4085 compatible = "qcom,sm8250-epss-l3";
4089 clock-names = "xo", "alternate";
4091 #interconnect-cells = <1>;
4095 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
4099 reg-names = "freq-domain0", "freq-domain1",
4100 "freq-domain2";
4103 clock-names = "xo", "alternate";
4105 #freq-domain-cells = <1>;
4110 compatible = "arm,armv8-timer";
4121 thermal-zones {
4122 cpu0-thermal {
4123 polling-delay-passive = <250>;
4124 polling-delay = <1000>;
4126 thermal-sensors = <&tsens0 1>;
4129 cpu0_alert0: trip-point0 {
4135 cpu0_alert1: trip-point1 {
4148 cooling-maps {
4151 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4158 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4166 cpu1-thermal {
4167 polling-delay-passive = <250>;
4168 polling-delay = <1000>;
4170 thermal-sensors = <&tsens0 2>;
4173 cpu1_alert0: trip-point0 {
4179 cpu1_alert1: trip-point1 {
4192 cooling-maps {
4195 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4202 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4210 cpu2-thermal {
4211 polling-delay-passive = <250>;
4212 polling-delay = <1000>;
4214 thermal-sensors = <&tsens0 3>;
4217 cpu2_alert0: trip-point0 {
4223 cpu2_alert1: trip-point1 {
4236 cooling-maps {
4239 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4246 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4254 cpu3-thermal {
4255 polling-delay-passive = <250>;
4256 polling-delay = <1000>;
4258 thermal-sensors = <&tsens0 4>;
4261 cpu3_alert0: trip-point0 {
4267 cpu3_alert1: trip-point1 {
4280 cooling-maps {
4283 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4290 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4298 cpu4-top-thermal {
4299 polling-delay-passive = <250>;
4300 polling-delay = <1000>;
4302 thermal-sensors = <&tsens0 7>;
4305 cpu4_top_alert0: trip-point0 {
4311 cpu4_top_alert1: trip-point1 {
4324 cooling-maps {
4327 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4334 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4342 cpu5-top-thermal {
4343 polling-delay-passive = <250>;
4344 polling-delay = <1000>;
4346 thermal-sensors = <&tsens0 8>;
4349 cpu5_top_alert0: trip-point0 {
4355 cpu5_top_alert1: trip-point1 {
4368 cooling-maps {
4371 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4378 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4386 cpu6-top-thermal {
4387 polling-delay-passive = <250>;
4388 polling-delay = <1000>;
4390 thermal-sensors = <&tsens0 9>;
4393 cpu6_top_alert0: trip-point0 {
4399 cpu6_top_alert1: trip-point1 {
4412 cooling-maps {
4415 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4422 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4430 cpu7-top-thermal {
4431 polling-delay-passive = <250>;
4432 polling-delay = <1000>;
4434 thermal-sensors = <&tsens0 10>;
4437 cpu7_top_alert0: trip-point0 {
4443 cpu7_top_alert1: trip-point1 {
4456 cooling-maps {
4459 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4466 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4474 cpu4-bottom-thermal {
4475 polling-delay-passive = <250>;
4476 polling-delay = <1000>;
4478 thermal-sensors = <&tsens0 11>;
4481 cpu4_bottom_alert0: trip-point0 {
4487 cpu4_bottom_alert1: trip-point1 {
4500 cooling-maps {
4503 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4510 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4518 cpu5-bottom-thermal {
4519 polling-delay-passive = <250>;
4520 polling-delay = <1000>;
4522 thermal-sensors = <&tsens0 12>;
4525 cpu5_bottom_alert0: trip-point0 {
4531 cpu5_bottom_alert1: trip-point1 {
4544 cooling-maps {
4547 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4554 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4562 cpu6-bottom-thermal {
4563 polling-delay-passive = <250>;
4564 polling-delay = <1000>;
4566 thermal-sensors = <&tsens0 13>;
4569 cpu6_bottom_alert0: trip-point0 {
4575 cpu6_bottom_alert1: trip-point1 {
4588 cooling-maps {
4591 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4598 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4606 cpu7-bottom-thermal {
4607 polling-delay-passive = <250>;
4608 polling-delay = <1000>;
4610 thermal-sensors = <&tsens0 14>;
4613 cpu7_bottom_alert0: trip-point0 {
4619 cpu7_bottom_alert1: trip-point1 {
4632 cooling-maps {
4635 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4642 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4650 aoss0-thermal {
4651 polling-delay-passive = <250>;
4652 polling-delay = <1000>;
4654 thermal-sensors = <&tsens0 0>;
4657 aoss0_alert0: trip-point0 {
4665 cluster0-thermal {
4666 polling-delay-passive = <250>;
4667 polling-delay = <1000>;
4669 thermal-sensors = <&tsens0 5>;
4672 cluster0_alert0: trip-point0 {
4685 cluster1-thermal {
4686 polling-delay-passive = <250>;
4687 polling-delay = <1000>;
4689 thermal-sensors = <&tsens0 6>;
4692 cluster1_alert0: trip-point0 {
4705 gpu-thermal-top {
4706 polling-delay-passive = <250>;
4707 polling-delay = <1000>;
4709 thermal-sensors = <&tsens0 15>;
4712 gpu1_alert0: trip-point0 {
4720 aoss1-thermal {
4721 polling-delay-passive = <250>;
4722 polling-delay = <1000>;
4724 thermal-sensors = <&tsens1 0>;
4727 aoss1_alert0: trip-point0 {
4735 wlan-thermal {
4736 polling-delay-passive = <250>;
4737 polling-delay = <1000>;
4739 thermal-sensors = <&tsens1 1>;
4742 wlan_alert0: trip-point0 {
4750 video-thermal {
4751 polling-delay-passive = <250>;
4752 polling-delay = <1000>;
4754 thermal-sensors = <&tsens1 2>;
4757 video_alert0: trip-point0 {
4765 mem-thermal {
4766 polling-delay-passive = <250>;
4767 polling-delay = <1000>;
4769 thermal-sensors = <&tsens1 3>;
4772 mem_alert0: trip-point0 {
4780 q6-hvx-thermal {
4781 polling-delay-passive = <250>;
4782 polling-delay = <1000>;
4784 thermal-sensors = <&tsens1 4>;
4787 q6_hvx_alert0: trip-point0 {
4795 camera-thermal {
4796 polling-delay-passive = <250>;
4797 polling-delay = <1000>;
4799 thermal-sensors = <&tsens1 5>;
4802 camera_alert0: trip-point0 {
4810 compute-thermal {
4811 polling-delay-passive = <250>;
4812 polling-delay = <1000>;
4814 thermal-sensors = <&tsens1 6>;
4817 compute_alert0: trip-point0 {
4825 npu-thermal {
4826 polling-delay-passive = <250>;
4827 polling-delay = <1000>;
4829 thermal-sensors = <&tsens1 7>;
4832 npu_alert0: trip-point0 {
4840 gpu-thermal-bottom {
4841 polling-delay-passive = <250>;
4842 polling-delay = <1000>;
4844 thermal-sensors = <&tsens1 8>;
4847 gpu2_alert0: trip-point0 {