Lines Matching +full:phy +full:- +full:qcom +full:- +full:qusb2
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
13 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
20 xo_board: xo-board {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <19200000>;
24 clock-output-names = "xo_board";
27 sleep_clk: sleep-clk {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <32000>;
31 clock-output-names = "sleep_clk";
36 #address-cells = <2>;
37 #size-cells = <0>;
41 compatible = "qcom,kryo260";
43 enable-method = "psci";
44 capacity-dmips-mhz = <1024>;
45 next-level-cache = <&L2_0>;
46 L2_0: l2-cache {
53 compatible = "qcom,kryo260";
55 enable-method = "psci";
56 capacity-dmips-mhz = <1024>;
57 next-level-cache = <&L2_0>;
62 compatible = "qcom,kryo260";
64 enable-method = "psci";
65 capacity-dmips-mhz = <1024>;
66 next-level-cache = <&L2_0>;
71 compatible = "qcom,kryo260";
73 enable-method = "psci";
74 capacity-dmips-mhz = <1024>;
75 next-level-cache = <&L2_0>;
80 compatible = "qcom,kryo260";
82 enable-method = "psci";
83 capacity-dmips-mhz = <1638>;
84 next-level-cache = <&L2_1>;
85 L2_1: l2-cache {
92 compatible = "qcom,kryo260";
94 enable-method = "psci";
95 capacity-dmips-mhz = <1638>;
96 next-level-cache = <&L2_1>;
101 compatible = "qcom,kryo260";
103 enable-method = "psci";
104 capacity-dmips-mhz = <1638>;
105 next-level-cache = <&L2_1>;
110 compatible = "qcom,kryo260";
112 enable-method = "psci";
113 capacity-dmips-mhz = <1638>;
114 next-level-cache = <&L2_1>;
117 cpu-map {
158 compatible = "qcom,scm-sm6125", "qcom,scm";
159 #reset-cells = <1>;
170 compatible = "arm,armv8-pmuv3";
175 compatible = "arm,psci-1.0";
179 reserved_memory: reserved-memory {
180 #address-cells = <2>;
181 #size-cells = <2>;
186 no-map;
191 no-map;
196 no-map;
201 no-map;
206 no-map;
211 no-map;
216 no-map;
221 no-map;
226 no-map;
231 no-map;
236 no-map;
241 no-map;
246 no-map;
251 no-map;
256 no-map;
261 no-map;
266 no-map;
271 no-map;
276 no-map;
281 no-map;
286 no-map;
290 rpm-glink {
291 compatible = "qcom,glink-rpm";
294 qcom,rpm-msg-ram = <&rpm_msg_ram>;
297 rpm_requests: rpm-requests {
298 compatible = "qcom,rpm-sm6125";
299 qcom,glink-channels = "rpm_requests";
301 rpmcc: clock-controller {
302 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc";
303 #clock-cells = <1>;
309 compatible = "qcom,smem";
310 memory-region = <&smem_mem>;
315 #address-cells = <1>;
316 #size-cells = <1>;
318 compatible = "simple-bus";
321 compatible = "qcom,tcsr-mutex";
323 #hwlock-cells = <1>;
327 compatible = "qcom,sm6125-tlmm";
331 reg-names = "west", "south", "east";
333 gpio-controller;
334 gpio-ranges = <&tlmm 0 0 134>;
335 #gpio-cells = <2>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
339 sdc2_state_off: sdc2-off {
342 bias-disable;
343 drive-strength = <2>;
348 bias-pull-up;
349 drive-strength = <2>;
354 bias-pull-up;
355 drive-strength = <2>;
360 gcc: clock-controller@1400000 {
361 compatible = "qcom,gcc-sm6125";
363 #clock-cells = <1>;
364 #reset-cells = <1>;
365 #power-domain-cells = <1>;
366 clock-names = "bi_tcxo", "sleep_clk";
370 hsusb_phy1: phy@1613000 {
371 compatible = "qcom,msm8996-qusb2-phy";
373 #phy-cells = <0>;
377 clock-names = "ref", "cfg_ahb";
384 compatible = "qcom,rpm-msg-ram";
389 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
391 reg-names = "hc", "core";
395 interrupt-names = "hc_irq", "pwr_irq";
400 clock-names = "iface", "core", "xo";
401 bus-width = <8>;
402 non-removable;
407 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
409 reg-names = "hc";
413 interrupt-names = "hc_irq", "pwr_irq";
418 clock-names = "iface", "core", "xo";
420 pinctrl-0 = <&sdc2_state_on>;
421 pinctrl-1 = <&sdc2_state_off>;
422 pinctrl-names = "default", "sleep";
424 bus-width = <4>;
429 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
431 #address-cells = <1>;
432 #size-cells = <1>;
442 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
444 assigned-clock-rates = <19200000>, <66666667>;
446 power-domains = <&gcc USB30_PRIM_GDSC>;
447 qcom,select-utmi-as-pipe-clk;
455 phy-names = "usb2-phy";
458 maximum-speed = "high-speed";
464 compatible = "qcom,spmi-pmic-arb";
470 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
471 interrupt-names = "periph_irq";
473 qcom,ee = <0>;
474 qcom,channel = <0>;
475 #address-cells = <2>;
476 #size-cells = <0>;
477 interrupt-controller;
478 #interrupt-cells = <4>;
479 cell-index = <0>;
483 compatible = "qcom,sm6125-apcs-hmss-global";
486 #mbox-cells = <1>;
490 compatible = "arm,armv7-timer-mem";
491 #address-cells = <1>;
492 #size-cells = <1>;
495 clock-frequency = <19200000>;
498 frame-number = <0>;
506 frame-number = <1>;
513 frame-number = <2>;
520 frame-number = <3>;
527 frame-number = <4>;
534 frame-number = <5>;
541 frame-number = <6>;
548 intc: interrupt-controller@f200000 {
549 compatible = "arm,gic-v3";
552 #interrupt-cells = <3>;
553 interrupt-controller;
559 compatible = "arm,armv8-timer";
564 clock-frequency = <19200000>;