Lines Matching refs:gcc
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
24 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
1061 gcc: clock-controller@100000 { label
1062 compatible = "qcom,gcc-sdm845";
1099 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1131 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1132 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1145 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1164 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1180 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1196 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1215 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1231 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1247 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1266 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1282 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1298 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1317 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1333 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1349 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1368 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1384 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1400 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1419 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1435 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1451 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1470 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1486 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1502 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1517 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1533 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1550 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1551 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1564 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1583 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1599 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1615 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1634 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1650 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1666 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1685 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1701 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1717 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1736 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1752 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1768 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1787 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1803 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1819 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1838 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1854 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1870 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1889 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1905 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1921 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1940 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1956 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2003 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2004 <&gcc GCC_PCIE_0_AUX_CLK>,
2005 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2006 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2007 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2008 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2009 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2036 resets = <&gcc GCC_PCIE_0_BCR>;
2039 power-domains = <&gcc PCIE_0_GDSC>;
2053 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2054 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2055 <&gcc GCC_PCIE_0_CLKREF_CLK>,
2056 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2059 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2062 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2072 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
2108 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2109 <&gcc GCC_PCIE_1_AUX_CLK>,
2110 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2111 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2112 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2113 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2114 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2115 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2125 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2146 resets = <&gcc GCC_PCIE_1_BCR>;
2149 power-domains = <&gcc PCIE_1_GDSC>;
2163 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2164 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2165 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2166 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2169 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2172 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2181 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2249 power-domains = <&gcc UFS_PHY_GDSC>;
2251 resets = <&gcc GCC_UFS_PHY_BCR>;
2267 <&gcc GCC_UFS_PHY_AXI_CLK>,
2268 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2269 <&gcc GCC_UFS_PHY_AHB_CLK>,
2270 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2272 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2273 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2274 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2275 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2298 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2299 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2333 clocks = <&gcc GCC_CE1_AHB_CLK>,
2334 <&gcc GCC_CE1_AHB_CLK>,
2976 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2977 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
2978 <&gcc GCC_BOOT_ROM_AHB_CLK>,
2979 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
2980 <&gcc GCC_MSS_SNOC_AXI_CLK>,
2981 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
2982 <&gcc GCC_PRNG_AHB_CLK>,
3025 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3026 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3499 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3500 <&gcc GCC_SDCC2_APPS_CLK>;
3563 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3564 <&gcc GCC_QSPI_CORE_CLK>;
3658 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3662 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3673 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3677 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3692 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3693 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3694 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3695 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3698 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3699 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3711 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3725 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3726 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3727 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3728 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3731 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3732 <&gcc GCC_USB3_PHY_SEC_BCR>;
3742 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3757 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3758 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3759 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3760 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3761 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
3765 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3766 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3776 power-domains = <&gcc USB30_PRIM_GDSC>;
3778 resets = <&gcc GCC_USB30_PRIM_BCR>;
3805 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3806 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3807 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3808 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3809 <&gcc GCC_USB30_SEC_SLEEP_CLK>;
3813 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3814 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3824 power-domains = <&gcc USB30_SEC_GDSC>;
3826 resets = <&gcc GCC_USB30_SEC_BCR>;
3994 <&gcc GCC_CAMERA_AHB_CLK>,
3995 <&gcc GCC_CAMERA_AXI_CLK>,
4150 clocks = <&gcc GCC_DISP_AHB_CLK>,
4180 clocks = <&gcc GCC_DISP_AXI_CLK>,
4185 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4467 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4468 <&gcc GCC_GPU_CFG_AHB_CLK>;
4488 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4489 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4519 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4520 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4909 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4920 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;