Lines Matching +full:phy +full:- +full:qcom +full:- +full:qusb2
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sdm845.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/phy/phy-qcom-qusb2.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
22 #include <dt-bindings/soc/qcom,apr.h>
23 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
24 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
25 #include <dt-bindings/thermal/thermal.h>
28 interrupt-parent = <&intc>;
30 #address-cells = <2>;
31 #size-cells = <2>;
76 reserved-memory {
77 #address-cells = <2>;
78 #size-cells = <2>;
83 no-map;
88 no-map;
93 no-map;
97 compatible = "qcom,cmd-db";
99 no-map;
104 no-map;
109 no-map;
113 compatible = "qcom,rmtfs-mem";
115 no-map;
117 qcom,client-id = <1>;
118 qcom,vmid = <15>;
123 no-map;
128 no-map;
133 no-map;
138 no-map;
143 no-map;
148 no-map;
153 no-map;
158 no-map;
163 no-map;
168 no-map;
173 no-map;
178 no-map;
183 no-map;
188 #address-cells = <2>;
189 #size-cells = <0>;
193 compatible = "qcom,kryo385";
195 enable-method = "psci";
196 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
199 capacity-dmips-mhz = <607>;
200 dynamic-power-coefficient = <100>;
201 qcom,freq-domain = <&cpufreq_hw 0>;
202 operating-points-v2 = <&cpu0_opp_table>;
205 #cooling-cells = <2>;
206 next-level-cache = <&L2_0>;
207 L2_0: l2-cache {
209 next-level-cache = <&L3_0>;
210 L3_0: l3-cache {
218 compatible = "qcom,kryo385";
220 enable-method = "psci";
221 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
224 capacity-dmips-mhz = <607>;
225 dynamic-power-coefficient = <100>;
226 qcom,freq-domain = <&cpufreq_hw 0>;
227 operating-points-v2 = <&cpu0_opp_table>;
230 #cooling-cells = <2>;
231 next-level-cache = <&L2_100>;
232 L2_100: l2-cache {
234 next-level-cache = <&L3_0>;
240 compatible = "qcom,kryo385";
242 enable-method = "psci";
243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
246 capacity-dmips-mhz = <607>;
247 dynamic-power-coefficient = <100>;
248 qcom,freq-domain = <&cpufreq_hw 0>;
249 operating-points-v2 = <&cpu0_opp_table>;
252 #cooling-cells = <2>;
253 next-level-cache = <&L2_200>;
254 L2_200: l2-cache {
256 next-level-cache = <&L3_0>;
262 compatible = "qcom,kryo385";
264 enable-method = "psci";
265 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
268 capacity-dmips-mhz = <607>;
269 dynamic-power-coefficient = <100>;
270 qcom,freq-domain = <&cpufreq_hw 0>;
271 operating-points-v2 = <&cpu0_opp_table>;
274 #cooling-cells = <2>;
275 next-level-cache = <&L2_300>;
276 L2_300: l2-cache {
278 next-level-cache = <&L3_0>;
284 compatible = "qcom,kryo385";
286 enable-method = "psci";
287 capacity-dmips-mhz = <1024>;
288 cpu-idle-states = <&BIG_CPU_SLEEP_0
291 dynamic-power-coefficient = <396>;
292 qcom,freq-domain = <&cpufreq_hw 1>;
293 operating-points-v2 = <&cpu4_opp_table>;
296 #cooling-cells = <2>;
297 next-level-cache = <&L2_400>;
298 L2_400: l2-cache {
300 next-level-cache = <&L3_0>;
306 compatible = "qcom,kryo385";
308 enable-method = "psci";
309 capacity-dmips-mhz = <1024>;
310 cpu-idle-states = <&BIG_CPU_SLEEP_0
313 dynamic-power-coefficient = <396>;
314 qcom,freq-domain = <&cpufreq_hw 1>;
315 operating-points-v2 = <&cpu4_opp_table>;
318 #cooling-cells = <2>;
319 next-level-cache = <&L2_500>;
320 L2_500: l2-cache {
322 next-level-cache = <&L3_0>;
328 compatible = "qcom,kryo385";
330 enable-method = "psci";
331 capacity-dmips-mhz = <1024>;
332 cpu-idle-states = <&BIG_CPU_SLEEP_0
335 dynamic-power-coefficient = <396>;
336 qcom,freq-domain = <&cpufreq_hw 1>;
337 operating-points-v2 = <&cpu4_opp_table>;
340 #cooling-cells = <2>;
341 next-level-cache = <&L2_600>;
342 L2_600: l2-cache {
344 next-level-cache = <&L3_0>;
350 compatible = "qcom,kryo385";
352 enable-method = "psci";
353 capacity-dmips-mhz = <1024>;
354 cpu-idle-states = <&BIG_CPU_SLEEP_0
357 dynamic-power-coefficient = <396>;
358 qcom,freq-domain = <&cpufreq_hw 1>;
359 operating-points-v2 = <&cpu4_opp_table>;
362 #cooling-cells = <2>;
363 next-level-cache = <&L2_700>;
364 L2_700: l2-cache {
366 next-level-cache = <&L3_0>;
370 cpu-map {
406 idle-states {
407 entry-method = "psci";
409 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
410 compatible = "arm,idle-state";
411 idle-state-name = "little-power-down";
412 arm,psci-suspend-param = <0x40000003>;
413 entry-latency-us = <350>;
414 exit-latency-us = <461>;
415 min-residency-us = <1890>;
416 local-timer-stop;
419 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
420 compatible = "arm,idle-state";
421 idle-state-name = "little-rail-power-down";
422 arm,psci-suspend-param = <0x40000004>;
423 entry-latency-us = <360>;
424 exit-latency-us = <531>;
425 min-residency-us = <3934>;
426 local-timer-stop;
429 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
430 compatible = "arm,idle-state";
431 idle-state-name = "big-power-down";
432 arm,psci-suspend-param = <0x40000003>;
433 entry-latency-us = <264>;
434 exit-latency-us = <621>;
435 min-residency-us = <952>;
436 local-timer-stop;
439 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
440 compatible = "arm,idle-state";
441 idle-state-name = "big-rail-power-down";
442 arm,psci-suspend-param = <0x40000004>;
443 entry-latency-us = <702>;
444 exit-latency-us = <1061>;
445 min-residency-us = <4488>;
446 local-timer-stop;
449 CLUSTER_SLEEP_0: cluster-sleep-0 {
450 compatible = "arm,idle-state";
451 idle-state-name = "cluster-power-down";
452 arm,psci-suspend-param = <0x400000F4>;
453 entry-latency-us = <3263>;
454 exit-latency-us = <6562>;
455 min-residency-us = <9987>;
456 local-timer-stop;
462 compatible = "operating-points-v2";
463 opp-shared;
465 cpu0_opp1: opp-300000000 {
466 opp-hz = /bits/ 64 <300000000>;
467 opp-peak-kBps = <800000 4800000>;
470 cpu0_opp2: opp-403200000 {
471 opp-hz = /bits/ 64 <403200000>;
472 opp-peak-kBps = <800000 4800000>;
475 cpu0_opp3: opp-480000000 {
476 opp-hz = /bits/ 64 <480000000>;
477 opp-peak-kBps = <800000 6451200>;
480 cpu0_opp4: opp-576000000 {
481 opp-hz = /bits/ 64 <576000000>;
482 opp-peak-kBps = <800000 6451200>;
485 cpu0_opp5: opp-652800000 {
486 opp-hz = /bits/ 64 <652800000>;
487 opp-peak-kBps = <800000 7680000>;
490 cpu0_opp6: opp-748800000 {
491 opp-hz = /bits/ 64 <748800000>;
492 opp-peak-kBps = <1804000 9216000>;
495 cpu0_opp7: opp-825600000 {
496 opp-hz = /bits/ 64 <825600000>;
497 opp-peak-kBps = <1804000 9216000>;
500 cpu0_opp8: opp-902400000 {
501 opp-hz = /bits/ 64 <902400000>;
502 opp-peak-kBps = <1804000 10444800>;
505 cpu0_opp9: opp-979200000 {
506 opp-hz = /bits/ 64 <979200000>;
507 opp-peak-kBps = <1804000 11980800>;
510 cpu0_opp10: opp-1056000000 {
511 opp-hz = /bits/ 64 <1056000000>;
512 opp-peak-kBps = <1804000 11980800>;
515 cpu0_opp11: opp-1132800000 {
516 opp-hz = /bits/ 64 <1132800000>;
517 opp-peak-kBps = <2188000 13516800>;
520 cpu0_opp12: opp-1228800000 {
521 opp-hz = /bits/ 64 <1228800000>;
522 opp-peak-kBps = <2188000 15052800>;
525 cpu0_opp13: opp-1324800000 {
526 opp-hz = /bits/ 64 <1324800000>;
527 opp-peak-kBps = <2188000 16588800>;
530 cpu0_opp14: opp-1420800000 {
531 opp-hz = /bits/ 64 <1420800000>;
532 opp-peak-kBps = <3072000 18124800>;
535 cpu0_opp15: opp-1516800000 {
536 opp-hz = /bits/ 64 <1516800000>;
537 opp-peak-kBps = <3072000 19353600>;
540 cpu0_opp16: opp-1612800000 {
541 opp-hz = /bits/ 64 <1612800000>;
542 opp-peak-kBps = <4068000 19353600>;
545 cpu0_opp17: opp-1689600000 {
546 opp-hz = /bits/ 64 <1689600000>;
547 opp-peak-kBps = <4068000 20889600>;
550 cpu0_opp18: opp-1766400000 {
551 opp-hz = /bits/ 64 <1766400000>;
552 opp-peak-kBps = <4068000 22425600>;
557 compatible = "operating-points-v2";
558 opp-shared;
560 cpu4_opp1: opp-300000000 {
561 opp-hz = /bits/ 64 <300000000>;
562 opp-peak-kBps = <800000 4800000>;
565 cpu4_opp2: opp-403200000 {
566 opp-hz = /bits/ 64 <403200000>;
567 opp-peak-kBps = <800000 4800000>;
570 cpu4_opp3: opp-480000000 {
571 opp-hz = /bits/ 64 <480000000>;
572 opp-peak-kBps = <1804000 4800000>;
575 cpu4_opp4: opp-576000000 {
576 opp-hz = /bits/ 64 <576000000>;
577 opp-peak-kBps = <1804000 4800000>;
580 cpu4_opp5: opp-652800000 {
581 opp-hz = /bits/ 64 <652800000>;
582 opp-peak-kBps = <1804000 4800000>;
585 cpu4_opp6: opp-748800000 {
586 opp-hz = /bits/ 64 <748800000>;
587 opp-peak-kBps = <1804000 4800000>;
590 cpu4_opp7: opp-825600000 {
591 opp-hz = /bits/ 64 <825600000>;
592 opp-peak-kBps = <2188000 9216000>;
595 cpu4_opp8: opp-902400000 {
596 opp-hz = /bits/ 64 <902400000>;
597 opp-peak-kBps = <2188000 9216000>;
600 cpu4_opp9: opp-979200000 {
601 opp-hz = /bits/ 64 <979200000>;
602 opp-peak-kBps = <2188000 9216000>;
605 cpu4_opp10: opp-1056000000 {
606 opp-hz = /bits/ 64 <1056000000>;
607 opp-peak-kBps = <3072000 9216000>;
610 cpu4_opp11: opp-1132800000 {
611 opp-hz = /bits/ 64 <1132800000>;
612 opp-peak-kBps = <3072000 11980800>;
615 cpu4_opp12: opp-1209600000 {
616 opp-hz = /bits/ 64 <1209600000>;
617 opp-peak-kBps = <4068000 11980800>;
620 cpu4_opp13: opp-1286400000 {
621 opp-hz = /bits/ 64 <1286400000>;
622 opp-peak-kBps = <4068000 11980800>;
625 cpu4_opp14: opp-1363200000 {
626 opp-hz = /bits/ 64 <1363200000>;
627 opp-peak-kBps = <4068000 15052800>;
630 cpu4_opp15: opp-1459200000 {
631 opp-hz = /bits/ 64 <1459200000>;
632 opp-peak-kBps = <4068000 15052800>;
635 cpu4_opp16: opp-1536000000 {
636 opp-hz = /bits/ 64 <1536000000>;
637 opp-peak-kBps = <5412000 15052800>;
640 cpu4_opp17: opp-1612800000 {
641 opp-hz = /bits/ 64 <1612800000>;
642 opp-peak-kBps = <5412000 15052800>;
645 cpu4_opp18: opp-1689600000 {
646 opp-hz = /bits/ 64 <1689600000>;
647 opp-peak-kBps = <5412000 19353600>;
650 cpu4_opp19: opp-1766400000 {
651 opp-hz = /bits/ 64 <1766400000>;
652 opp-peak-kBps = <6220000 19353600>;
655 cpu4_opp20: opp-1843200000 {
656 opp-hz = /bits/ 64 <1843200000>;
657 opp-peak-kBps = <6220000 19353600>;
660 cpu4_opp21: opp-1920000000 {
661 opp-hz = /bits/ 64 <1920000000>;
662 opp-peak-kBps = <7216000 19353600>;
665 cpu4_opp22: opp-1996800000 {
666 opp-hz = /bits/ 64 <1996800000>;
667 opp-peak-kBps = <7216000 20889600>;
670 cpu4_opp23: opp-2092800000 {
671 opp-hz = /bits/ 64 <2092800000>;
672 opp-peak-kBps = <7216000 20889600>;
675 cpu4_opp24: opp-2169600000 {
676 opp-hz = /bits/ 64 <2169600000>;
677 opp-peak-kBps = <7216000 20889600>;
680 cpu4_opp25: opp-2246400000 {
681 opp-hz = /bits/ 64 <2246400000>;
682 opp-peak-kBps = <7216000 20889600>;
685 cpu4_opp26: opp-2323200000 {
686 opp-hz = /bits/ 64 <2323200000>;
687 opp-peak-kBps = <7216000 20889600>;
690 cpu4_opp27: opp-2400000000 {
691 opp-hz = /bits/ 64 <2400000000>;
692 opp-peak-kBps = <7216000 22425600>;
695 cpu4_opp28: opp-2476800000 {
696 opp-hz = /bits/ 64 <2476800000>;
697 opp-peak-kBps = <7216000 22425600>;
700 cpu4_opp29: opp-2553600000 {
701 opp-hz = /bits/ 64 <2553600000>;
702 opp-peak-kBps = <7216000 22425600>;
705 cpu4_opp30: opp-2649600000 {
706 opp-hz = /bits/ 64 <2649600000>;
707 opp-peak-kBps = <7216000 22425600>;
710 cpu4_opp31: opp-2745600000 {
711 opp-hz = /bits/ 64 <2745600000>;
712 opp-peak-kBps = <7216000 25497600>;
715 cpu4_opp32: opp-2803200000 {
716 opp-hz = /bits/ 64 <2803200000>;
717 opp-peak-kBps = <7216000 25497600>;
722 compatible = "arm,armv8-pmuv3";
727 compatible = "arm,armv8-timer";
735 xo_board: xo-board {
736 compatible = "fixed-clock";
737 #clock-cells = <0>;
738 clock-frequency = <38400000>;
739 clock-output-names = "xo_board";
742 sleep_clk: sleep-clk {
743 compatible = "fixed-clock";
744 #clock-cells = <0>;
745 clock-frequency = <32764>;
751 compatible = "qcom,scm-sdm845", "qcom,scm";
755 adsp_pas: remoteproc-adsp {
756 compatible = "qcom,sdm845-adsp-pas";
758 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
763 interrupt-names = "wdog", "fatal", "ready",
764 "handover", "stop-ack";
767 clock-names = "xo";
769 memory-region = <&adsp_mem>;
771 qcom,smem-states = <&adsp_smp2p_out 0>;
772 qcom,smem-state-names = "stop";
776 glink-edge {
779 qcom,remote-pid = <2>;
783 compatible = "qcom,apr-v2";
784 qcom,glink-channels = "apr_audio_svc";
785 qcom,apr-domain = <APR_DOMAIN_ADSP>;
786 #address-cells = <1>;
787 #size-cells = <0>;
788 qcom,intents = <512 20>;
790 apr-service@3 {
792 compatible = "qcom,q6core";
793 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
796 q6afe: apr-service@4 {
797 compatible = "qcom,q6afe";
799 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
801 compatible = "qcom,q6afe-dais";
802 #address-cells = <1>;
803 #size-cells = <0>;
804 #sound-dai-cells = <1>;
808 q6asm: apr-service@7 {
809 compatible = "qcom,q6asm";
811 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
813 compatible = "qcom,q6asm-dais";
814 #address-cells = <1>;
815 #size-cells = <0>;
816 #sound-dai-cells = <1>;
821 q6adm: apr-service@8 {
822 compatible = "qcom,q6adm";
824 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
826 compatible = "qcom,q6adm-routing";
827 #sound-dai-cells = <0>;
833 compatible = "qcom,fastrpc";
834 qcom,glink-channels = "fastrpcglink-apps-dsp";
836 #address-cells = <1>;
837 #size-cells = <0>;
839 compute-cb@3 {
840 compatible = "qcom,fastrpc-compute-cb";
845 compute-cb@4 {
846 compatible = "qcom,fastrpc-compute-cb";
854 cdsp_pas: remoteproc-cdsp {
855 compatible = "qcom,sdm845-cdsp-pas";
857 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
862 interrupt-names = "wdog", "fatal", "ready",
863 "handover", "stop-ack";
866 clock-names = "xo";
868 memory-region = <&cdsp_mem>;
870 qcom,smem-states = <&cdsp_smp2p_out 0>;
871 qcom,smem-state-names = "stop";
875 glink-edge {
878 qcom,remote-pid = <5>;
881 compatible = "qcom,fastrpc";
882 qcom,glink-channels = "fastrpcglink-apps-dsp";
884 #address-cells = <1>;
885 #size-cells = <0>;
887 compute-cb@1 {
888 compatible = "qcom,fastrpc-compute-cb";
893 compute-cb@2 {
894 compatible = "qcom,fastrpc-compute-cb";
899 compute-cb@3 {
900 compatible = "qcom,fastrpc-compute-cb";
905 compute-cb@4 {
906 compatible = "qcom,fastrpc-compute-cb";
911 compute-cb@5 {
912 compatible = "qcom,fastrpc-compute-cb";
917 compute-cb@6 {
918 compatible = "qcom,fastrpc-compute-cb";
923 compute-cb@7 {
924 compatible = "qcom,fastrpc-compute-cb";
929 compute-cb@8 {
930 compatible = "qcom,fastrpc-compute-cb";
939 compatible = "qcom,tcsr-mutex";
941 #hwlock-cells = <1>;
945 compatible = "qcom,smem";
946 memory-region = <&smem_mem>;
950 smp2p-cdsp {
951 compatible = "qcom,smp2p";
952 qcom,smem = <94>, <432>;
958 qcom,local-pid = <0>;
959 qcom,remote-pid = <5>;
961 cdsp_smp2p_out: master-kernel {
962 qcom,entry-name = "master-kernel";
963 #qcom,smem-state-cells = <1>;
966 cdsp_smp2p_in: slave-kernel {
967 qcom,entry-name = "slave-kernel";
969 interrupt-controller;
970 #interrupt-cells = <2>;
974 smp2p-lpass {
975 compatible = "qcom,smp2p";
976 qcom,smem = <443>, <429>;
982 qcom,local-pid = <0>;
983 qcom,remote-pid = <2>;
985 adsp_smp2p_out: master-kernel {
986 qcom,entry-name = "master-kernel";
987 #qcom,smem-state-cells = <1>;
990 adsp_smp2p_in: slave-kernel {
991 qcom,entry-name = "slave-kernel";
993 interrupt-controller;
994 #interrupt-cells = <2>;
998 smp2p-mpss {
999 compatible = "qcom,smp2p";
1000 qcom,smem = <435>, <428>;
1003 qcom,local-pid = <0>;
1004 qcom,remote-pid = <1>;
1006 modem_smp2p_out: master-kernel {
1007 qcom,entry-name = "master-kernel";
1008 #qcom,smem-state-cells = <1>;
1011 modem_smp2p_in: slave-kernel {
1012 qcom,entry-name = "slave-kernel";
1013 interrupt-controller;
1014 #interrupt-cells = <2>;
1017 ipa_smp2p_out: ipa-ap-to-modem {
1018 qcom,entry-name = "ipa";
1019 #qcom,smem-state-cells = <1>;
1022 ipa_smp2p_in: ipa-modem-to-ap {
1023 qcom,entry-name = "ipa";
1024 interrupt-controller;
1025 #interrupt-cells = <2>;
1029 smp2p-slpi {
1030 compatible = "qcom,smp2p";
1031 qcom,smem = <481>, <430>;
1034 qcom,local-pid = <0>;
1035 qcom,remote-pid = <3>;
1037 slpi_smp2p_out: master-kernel {
1038 qcom,entry-name = "master-kernel";
1039 #qcom,smem-state-cells = <1>;
1042 slpi_smp2p_in: slave-kernel {
1043 qcom,entry-name = "slave-kernel";
1044 interrupt-controller;
1045 #interrupt-cells = <2>;
1050 compatible = "arm,psci-1.0";
1055 #address-cells = <2>;
1056 #size-cells = <2>;
1058 dma-ranges = <0 0 0 0 0x10 0>;
1059 compatible = "simple-bus";
1061 gcc: clock-controller@100000 {
1062 compatible = "qcom,gcc-sdm845";
1069 clock-names = "bi_tcxo",
1074 #clock-cells = <1>;
1075 #reset-cells = <1>;
1076 #power-domain-cells = <1>;
1080 compatible = "qcom,qfprom";
1082 #address-cells = <1>;
1083 #size-cells = <1>;
1085 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1090 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1097 compatible = "qcom,prng-ee";
1100 clock-names = "core";
1103 qup_opp_table: qup-opp-table {
1104 compatible = "operating-points-v2";
1106 opp-50000000 {
1107 opp-hz = /bits/ 64 <50000000>;
1108 required-opps = <&rpmhpd_opp_min_svs>;
1111 opp-75000000 {
1112 opp-hz = /bits/ 64 <75000000>;
1113 required-opps = <&rpmhpd_opp_low_svs>;
1116 opp-100000000 {
1117 opp-hz = /bits/ 64 <100000000>;
1118 required-opps = <&rpmhpd_opp_svs>;
1121 opp-128000000 {
1122 opp-hz = /bits/ 64 <128000000>;
1123 required-opps = <&rpmhpd_opp_nom>;
1128 compatible = "qcom,geni-se-qup";
1130 clock-names = "m-ahb", "s-ahb";
1134 #address-cells = <2>;
1135 #size-cells = <2>;
1138 interconnect-names = "qup-core";
1142 compatible = "qcom,geni-i2c";
1144 clock-names = "se";
1146 pinctrl-names = "default";
1147 pinctrl-0 = <&qup_i2c0_default>;
1149 #address-cells = <1>;
1150 #size-cells = <0>;
1151 power-domains = <&rpmhpd SDM845_CX>;
1152 operating-points-v2 = <&qup_opp_table>;
1156 interconnect-names = "qup-core", "qup-config", "qup-memory";
1161 compatible = "qcom,geni-spi";
1163 clock-names = "se";
1165 pinctrl-names = "default";
1166 pinctrl-0 = <&qup_spi0_default>;
1168 #address-cells = <1>;
1169 #size-cells = <0>;
1172 interconnect-names = "qup-core", "qup-config";
1177 compatible = "qcom,geni-uart";
1179 clock-names = "se";
1181 pinctrl-names = "default";
1182 pinctrl-0 = <&qup_uart0_default>;
1184 power-domains = <&rpmhpd SDM845_CX>;
1185 operating-points-v2 = <&qup_opp_table>;
1188 interconnect-names = "qup-core", "qup-config";
1193 compatible = "qcom,geni-i2c";
1195 clock-names = "se";
1197 pinctrl-names = "default";
1198 pinctrl-0 = <&qup_i2c1_default>;
1200 #address-cells = <1>;
1201 #size-cells = <0>;
1202 power-domains = <&rpmhpd SDM845_CX>;
1203 operating-points-v2 = <&qup_opp_table>;
1207 interconnect-names = "qup-core", "qup-config", "qup-memory";
1212 compatible = "qcom,geni-spi";
1214 clock-names = "se";
1216 pinctrl-names = "default";
1217 pinctrl-0 = <&qup_spi1_default>;
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1223 interconnect-names = "qup-core", "qup-config";
1228 compatible = "qcom,geni-uart";
1230 clock-names = "se";
1232 pinctrl-names = "default";
1233 pinctrl-0 = <&qup_uart1_default>;
1235 power-domains = <&rpmhpd SDM845_CX>;
1236 operating-points-v2 = <&qup_opp_table>;
1239 interconnect-names = "qup-core", "qup-config";
1244 compatible = "qcom,geni-i2c";
1246 clock-names = "se";
1248 pinctrl-names = "default";
1249 pinctrl-0 = <&qup_i2c2_default>;
1251 #address-cells = <1>;
1252 #size-cells = <0>;
1253 power-domains = <&rpmhpd SDM845_CX>;
1254 operating-points-v2 = <&qup_opp_table>;
1258 interconnect-names = "qup-core", "qup-config", "qup-memory";
1263 compatible = "qcom,geni-spi";
1265 clock-names = "se";
1267 pinctrl-names = "default";
1268 pinctrl-0 = <&qup_spi2_default>;
1270 #address-cells = <1>;
1271 #size-cells = <0>;
1274 interconnect-names = "qup-core", "qup-config";
1279 compatible = "qcom,geni-uart";
1281 clock-names = "se";
1283 pinctrl-names = "default";
1284 pinctrl-0 = <&qup_uart2_default>;
1286 power-domains = <&rpmhpd SDM845_CX>;
1287 operating-points-v2 = <&qup_opp_table>;
1290 interconnect-names = "qup-core", "qup-config";
1295 compatible = "qcom,geni-i2c";
1297 clock-names = "se";
1299 pinctrl-names = "default";
1300 pinctrl-0 = <&qup_i2c3_default>;
1302 #address-cells = <1>;
1303 #size-cells = <0>;
1304 power-domains = <&rpmhpd SDM845_CX>;
1305 operating-points-v2 = <&qup_opp_table>;
1309 interconnect-names = "qup-core", "qup-config", "qup-memory";
1314 compatible = "qcom,geni-spi";
1316 clock-names = "se";
1318 pinctrl-names = "default";
1319 pinctrl-0 = <&qup_spi3_default>;
1321 #address-cells = <1>;
1322 #size-cells = <0>;
1325 interconnect-names = "qup-core", "qup-config";
1330 compatible = "qcom,geni-uart";
1332 clock-names = "se";
1334 pinctrl-names = "default";
1335 pinctrl-0 = <&qup_uart3_default>;
1337 power-domains = <&rpmhpd SDM845_CX>;
1338 operating-points-v2 = <&qup_opp_table>;
1341 interconnect-names = "qup-core", "qup-config";
1346 compatible = "qcom,geni-i2c";
1348 clock-names = "se";
1350 pinctrl-names = "default";
1351 pinctrl-0 = <&qup_i2c4_default>;
1353 #address-cells = <1>;
1354 #size-cells = <0>;
1355 power-domains = <&rpmhpd SDM845_CX>;
1356 operating-points-v2 = <&qup_opp_table>;
1360 interconnect-names = "qup-core", "qup-config", "qup-memory";
1365 compatible = "qcom,geni-spi";
1367 clock-names = "se";
1369 pinctrl-names = "default";
1370 pinctrl-0 = <&qup_spi4_default>;
1372 #address-cells = <1>;
1373 #size-cells = <0>;
1376 interconnect-names = "qup-core", "qup-config";
1381 compatible = "qcom,geni-uart";
1383 clock-names = "se";
1385 pinctrl-names = "default";
1386 pinctrl-0 = <&qup_uart4_default>;
1388 power-domains = <&rpmhpd SDM845_CX>;
1389 operating-points-v2 = <&qup_opp_table>;
1392 interconnect-names = "qup-core", "qup-config";
1397 compatible = "qcom,geni-i2c";
1399 clock-names = "se";
1401 pinctrl-names = "default";
1402 pinctrl-0 = <&qup_i2c5_default>;
1404 #address-cells = <1>;
1405 #size-cells = <0>;
1406 power-domains = <&rpmhpd SDM845_CX>;
1407 operating-points-v2 = <&qup_opp_table>;
1411 interconnect-names = "qup-core", "qup-config", "qup-memory";
1416 compatible = "qcom,geni-spi";
1418 clock-names = "se";
1420 pinctrl-names = "default";
1421 pinctrl-0 = <&qup_spi5_default>;
1423 #address-cells = <1>;
1424 #size-cells = <0>;
1427 interconnect-names = "qup-core", "qup-config";
1432 compatible = "qcom,geni-uart";
1434 clock-names = "se";
1436 pinctrl-names = "default";
1437 pinctrl-0 = <&qup_uart5_default>;
1439 power-domains = <&rpmhpd SDM845_CX>;
1440 operating-points-v2 = <&qup_opp_table>;
1443 interconnect-names = "qup-core", "qup-config";
1448 compatible = "qcom,geni-i2c";
1450 clock-names = "se";
1452 pinctrl-names = "default";
1453 pinctrl-0 = <&qup_i2c6_default>;
1455 #address-cells = <1>;
1456 #size-cells = <0>;
1457 power-domains = <&rpmhpd SDM845_CX>;
1458 operating-points-v2 = <&qup_opp_table>;
1462 interconnect-names = "qup-core", "qup-config", "qup-memory";
1467 compatible = "qcom,geni-spi";
1469 clock-names = "se";
1471 pinctrl-names = "default";
1472 pinctrl-0 = <&qup_spi6_default>;
1474 #address-cells = <1>;
1475 #size-cells = <0>;
1478 interconnect-names = "qup-core", "qup-config";
1483 compatible = "qcom,geni-uart";
1485 clock-names = "se";
1487 pinctrl-names = "default";
1488 pinctrl-0 = <&qup_uart6_default>;
1490 power-domains = <&rpmhpd SDM845_CX>;
1491 operating-points-v2 = <&qup_opp_table>;
1494 interconnect-names = "qup-core", "qup-config";
1499 compatible = "qcom,geni-i2c";
1501 clock-names = "se";
1503 pinctrl-names = "default";
1504 pinctrl-0 = <&qup_i2c7_default>;
1506 #address-cells = <1>;
1507 #size-cells = <0>;
1508 power-domains = <&rpmhpd SDM845_CX>;
1509 operating-points-v2 = <&qup_opp_table>;
1514 compatible = "qcom,geni-spi";
1516 clock-names = "se";
1518 pinctrl-names = "default";
1519 pinctrl-0 = <&qup_spi7_default>;
1521 #address-cells = <1>;
1522 #size-cells = <0>;
1525 interconnect-names = "qup-core", "qup-config";
1530 compatible = "qcom,geni-uart";
1532 clock-names = "se";
1534 pinctrl-names = "default";
1535 pinctrl-0 = <&qup_uart7_default>;
1537 power-domains = <&rpmhpd SDM845_CX>;
1538 operating-points-v2 = <&qup_opp_table>;
1541 interconnect-names = "qup-core", "qup-config";
1547 compatible = "qcom,geni-se-qup";
1549 clock-names = "m-ahb", "s-ahb";
1553 #address-cells = <2>;
1554 #size-cells = <2>;
1557 interconnect-names = "qup-core";
1561 compatible = "qcom,geni-i2c";
1563 clock-names = "se";
1565 pinctrl-names = "default";
1566 pinctrl-0 = <&qup_i2c8_default>;
1568 #address-cells = <1>;
1569 #size-cells = <0>;
1570 power-domains = <&rpmhpd SDM845_CX>;
1571 operating-points-v2 = <&qup_opp_table>;
1575 interconnect-names = "qup-core", "qup-config", "qup-memory";
1580 compatible = "qcom,geni-spi";
1582 clock-names = "se";
1584 pinctrl-names = "default";
1585 pinctrl-0 = <&qup_spi8_default>;
1587 #address-cells = <1>;
1588 #size-cells = <0>;
1591 interconnect-names = "qup-core", "qup-config";
1596 compatible = "qcom,geni-uart";
1598 clock-names = "se";
1600 pinctrl-names = "default";
1601 pinctrl-0 = <&qup_uart8_default>;
1603 power-domains = <&rpmhpd SDM845_CX>;
1604 operating-points-v2 = <&qup_opp_table>;
1607 interconnect-names = "qup-core", "qup-config";
1612 compatible = "qcom,geni-i2c";
1614 clock-names = "se";
1616 pinctrl-names = "default";
1617 pinctrl-0 = <&qup_i2c9_default>;
1619 #address-cells = <1>;
1620 #size-cells = <0>;
1621 power-domains = <&rpmhpd SDM845_CX>;
1622 operating-points-v2 = <&qup_opp_table>;
1626 interconnect-names = "qup-core", "qup-config", "qup-memory";
1631 compatible = "qcom,geni-spi";
1633 clock-names = "se";
1635 pinctrl-names = "default";
1636 pinctrl-0 = <&qup_spi9_default>;
1638 #address-cells = <1>;
1639 #size-cells = <0>;
1642 interconnect-names = "qup-core", "qup-config";
1647 compatible = "qcom,geni-debug-uart";
1649 clock-names = "se";
1651 pinctrl-names = "default";
1652 pinctrl-0 = <&qup_uart9_default>;
1654 power-domains = <&rpmhpd SDM845_CX>;
1655 operating-points-v2 = <&qup_opp_table>;
1658 interconnect-names = "qup-core", "qup-config";
1663 compatible = "qcom,geni-i2c";
1665 clock-names = "se";
1667 pinctrl-names = "default";
1668 pinctrl-0 = <&qup_i2c10_default>;
1670 #address-cells = <1>;
1671 #size-cells = <0>;
1672 power-domains = <&rpmhpd SDM845_CX>;
1673 operating-points-v2 = <&qup_opp_table>;
1677 interconnect-names = "qup-core", "qup-config", "qup-memory";
1682 compatible = "qcom,geni-spi";
1684 clock-names = "se";
1686 pinctrl-names = "default";
1687 pinctrl-0 = <&qup_spi10_default>;
1689 #address-cells = <1>;
1690 #size-cells = <0>;
1693 interconnect-names = "qup-core", "qup-config";
1698 compatible = "qcom,geni-uart";
1700 clock-names = "se";
1702 pinctrl-names = "default";
1703 pinctrl-0 = <&qup_uart10_default>;
1705 power-domains = <&rpmhpd SDM845_CX>;
1706 operating-points-v2 = <&qup_opp_table>;
1709 interconnect-names = "qup-core", "qup-config";
1714 compatible = "qcom,geni-i2c";
1716 clock-names = "se";
1718 pinctrl-names = "default";
1719 pinctrl-0 = <&qup_i2c11_default>;
1721 #address-cells = <1>;
1722 #size-cells = <0>;
1723 power-domains = <&rpmhpd SDM845_CX>;
1724 operating-points-v2 = <&qup_opp_table>;
1728 interconnect-names = "qup-core", "qup-config", "qup-memory";
1733 compatible = "qcom,geni-spi";
1735 clock-names = "se";
1737 pinctrl-names = "default";
1738 pinctrl-0 = <&qup_spi11_default>;
1740 #address-cells = <1>;
1741 #size-cells = <0>;
1744 interconnect-names = "qup-core", "qup-config";
1749 compatible = "qcom,geni-uart";
1751 clock-names = "se";
1753 pinctrl-names = "default";
1754 pinctrl-0 = <&qup_uart11_default>;
1756 power-domains = <&rpmhpd SDM845_CX>;
1757 operating-points-v2 = <&qup_opp_table>;
1760 interconnect-names = "qup-core", "qup-config";
1765 compatible = "qcom,geni-i2c";
1767 clock-names = "se";
1769 pinctrl-names = "default";
1770 pinctrl-0 = <&qup_i2c12_default>;
1772 #address-cells = <1>;
1773 #size-cells = <0>;
1774 power-domains = <&rpmhpd SDM845_CX>;
1775 operating-points-v2 = <&qup_opp_table>;
1779 interconnect-names = "qup-core", "qup-config", "qup-memory";
1784 compatible = "qcom,geni-spi";
1786 clock-names = "se";
1788 pinctrl-names = "default";
1789 pinctrl-0 = <&qup_spi12_default>;
1791 #address-cells = <1>;
1792 #size-cells = <0>;
1795 interconnect-names = "qup-core", "qup-config";
1800 compatible = "qcom,geni-uart";
1802 clock-names = "se";
1804 pinctrl-names = "default";
1805 pinctrl-0 = <&qup_uart12_default>;
1807 power-domains = <&rpmhpd SDM845_CX>;
1808 operating-points-v2 = <&qup_opp_table>;
1811 interconnect-names = "qup-core", "qup-config";
1816 compatible = "qcom,geni-i2c";
1818 clock-names = "se";
1820 pinctrl-names = "default";
1821 pinctrl-0 = <&qup_i2c13_default>;
1823 #address-cells = <1>;
1824 #size-cells = <0>;
1825 power-domains = <&rpmhpd SDM845_CX>;
1826 operating-points-v2 = <&qup_opp_table>;
1830 interconnect-names = "qup-core", "qup-config", "qup-memory";
1835 compatible = "qcom,geni-spi";
1837 clock-names = "se";
1839 pinctrl-names = "default";
1840 pinctrl-0 = <&qup_spi13_default>;
1842 #address-cells = <1>;
1843 #size-cells = <0>;
1846 interconnect-names = "qup-core", "qup-config";
1851 compatible = "qcom,geni-uart";
1853 clock-names = "se";
1855 pinctrl-names = "default";
1856 pinctrl-0 = <&qup_uart13_default>;
1858 power-domains = <&rpmhpd SDM845_CX>;
1859 operating-points-v2 = <&qup_opp_table>;
1862 interconnect-names = "qup-core", "qup-config";
1867 compatible = "qcom,geni-i2c";
1869 clock-names = "se";
1871 pinctrl-names = "default";
1872 pinctrl-0 = <&qup_i2c14_default>;
1874 #address-cells = <1>;
1875 #size-cells = <0>;
1876 power-domains = <&rpmhpd SDM845_CX>;
1877 operating-points-v2 = <&qup_opp_table>;
1881 interconnect-names = "qup-core", "qup-config", "qup-memory";
1886 compatible = "qcom,geni-spi";
1888 clock-names = "se";
1890 pinctrl-names = "default";
1891 pinctrl-0 = <&qup_spi14_default>;
1893 #address-cells = <1>;
1894 #size-cells = <0>;
1897 interconnect-names = "qup-core", "qup-config";
1902 compatible = "qcom,geni-uart";
1904 clock-names = "se";
1906 pinctrl-names = "default";
1907 pinctrl-0 = <&qup_uart14_default>;
1909 power-domains = <&rpmhpd SDM845_CX>;
1910 operating-points-v2 = <&qup_opp_table>;
1913 interconnect-names = "qup-core", "qup-config";
1918 compatible = "qcom,geni-i2c";
1920 clock-names = "se";
1922 pinctrl-names = "default";
1923 pinctrl-0 = <&qup_i2c15_default>;
1925 #address-cells = <1>;
1926 #size-cells = <0>;
1927 power-domains = <&rpmhpd SDM845_CX>;
1928 operating-points-v2 = <&qup_opp_table>;
1933 interconnect-names = "qup-core", "qup-config", "qup-memory";
1937 compatible = "qcom,geni-spi";
1939 clock-names = "se";
1941 pinctrl-names = "default";
1942 pinctrl-0 = <&qup_spi15_default>;
1944 #address-cells = <1>;
1945 #size-cells = <0>;
1948 interconnect-names = "qup-core", "qup-config";
1953 compatible = "qcom,geni-uart";
1955 clock-names = "se";
1957 pinctrl-names = "default";
1958 pinctrl-0 = <&qup_uart15_default>;
1960 power-domains = <&rpmhpd SDM845_CX>;
1961 operating-points-v2 = <&qup_opp_table>;
1964 interconnect-names = "qup-core", "qup-config";
1969 system-cache-controller@1100000 {
1970 compatible = "qcom,sdm845-llcc";
1972 reg-names = "llcc_base", "llcc_broadcast_base";
1977 compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
1982 reg-names = "parf", "dbi", "elbi", "config";
1984 linux,pci-domain = <0>;
1985 bus-range = <0x00 0xff>;
1986 num-lanes = <1>;
1988 #address-cells = <3>;
1989 #size-cells = <2>;
1995 interrupt-names = "msi";
1996 #interrupt-cells = <1>;
1997 interrupt-map-mask = <0 0 0 0x7>;
1998 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2010 clock-names = "pipe",
2019 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2037 reset-names = "pci";
2039 power-domains = <&gcc PCIE_0_GDSC>;
2042 phy-names = "pciephy";
2047 pcie0_phy: phy@1c06000 {
2048 compatible = "qcom,sdm845-qmp-pcie-phy";
2050 #address-cells = <2>;
2051 #size-cells = <2>;
2057 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2060 reset-names = "phy";
2062 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2063 assigned-clock-rates = <100000000>;
2073 clock-names = "pipe0";
2075 #clock-cells = <0>;
2076 #phy-cells = <0>;
2077 clock-output-names = "pcie_0_pipe_clk";
2082 compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
2087 reg-names = "parf", "dbi", "elbi", "config";
2089 linux,pci-domain = <1>;
2090 bus-range = <0x00 0xff>;
2091 num-lanes = <1>;
2093 #address-cells = <3>;
2094 #size-cells = <2>;
2100 interrupt-names = "msi";
2101 #interrupt-cells = <1>;
2102 interrupt-map-mask = <0 0 0 0x7>;
2103 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2116 clock-names = "pipe",
2125 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2126 assigned-clock-rates = <19200000>;
2129 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2147 reset-names = "pci";
2149 power-domains = <&gcc PCIE_1_GDSC>;
2152 phy-names = "pciephy";
2157 pcie1_phy: phy@1c0a000 {
2158 compatible = "qcom,sdm845-qhp-pcie-phy";
2160 #address-cells = <2>;
2161 #size-cells = <2>;
2167 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2170 reset-names = "phy";
2172 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2173 assigned-clock-rates = <100000000>;
2182 clock-names = "pipe0";
2184 #clock-cells = <0>;
2185 #phy-cells = <0>;
2186 clock-output-names = "pcie_1_pipe_clk";
2191 compatible = "qcom,sdm845-mem-noc";
2193 #interconnect-cells = <2>;
2194 qcom,bcm-voters = <&apps_bcm_voter>;
2198 compatible = "qcom,sdm845-dc-noc";
2200 #interconnect-cells = <2>;
2201 qcom,bcm-voters = <&apps_bcm_voter>;
2205 compatible = "qcom,sdm845-config-noc";
2207 #interconnect-cells = <2>;
2208 qcom,bcm-voters = <&apps_bcm_voter>;
2212 compatible = "qcom,sdm845-system-noc";
2214 #interconnect-cells = <2>;
2215 qcom,bcm-voters = <&apps_bcm_voter>;
2219 compatible = "qcom,sdm845-aggre1-noc";
2221 #interconnect-cells = <2>;
2222 qcom,bcm-voters = <&apps_bcm_voter>;
2226 compatible = "qcom,sdm845-aggre2-noc";
2228 #interconnect-cells = <2>;
2229 qcom,bcm-voters = <&apps_bcm_voter>;
2233 compatible = "qcom,sdm845-mmss-noc";
2235 #interconnect-cells = <2>;
2236 qcom,bcm-voters = <&apps_bcm_voter>;
2240 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2241 "jedec,ufs-2.0";
2244 reg-names = "std", "ice";
2247 phy-names = "ufsphy";
2248 lanes-per-direction = <2>;
2249 power-domains = <&gcc UFS_PHY_GDSC>;
2250 #reset-cells = <1>;
2252 reset-names = "rst";
2256 clock-names =
2276 freq-table-hz =
2290 ufs_mem_phy: phy@1d87000 {
2291 compatible = "qcom,sdm845-qmp-ufs-phy";
2293 #address-cells = <2>;
2294 #size-cells = <2>;
2296 clock-names = "ref",
2302 reset-names = "ufsphy";
2311 #phy-cells = <0>;
2316 compatible = "qcom,bam-v1.7.0";
2320 clock-names = "bam_clk";
2321 #dma-cells = <1>;
2322 qcom,ee = <0>;
2323 qcom,controlled-remotely = <1>;
2331 compatible = "qcom,crypto-v5.4";
2336 clock-names = "iface", "bus", "core";
2338 dma-names = "rx", "tx";
2346 compatible = "qcom,sdm845-ipa";
2353 reg-names = "ipa-reg",
2354 "ipa-shared",
2357 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2361 interrupt-names = "ipa",
2363 "ipa-clock-query",
2364 "ipa-setup-ready";
2367 clock-names = "core";
2372 interconnect-names = "memory",
2376 qcom,smem-states = <&ipa_smp2p_out 0>,
2378 qcom,smem-state-names = "ipa-clock-enabled-valid",
2379 "ipa-clock-enabled";
2390 compatible = "qcom,sdm845-pinctrl";
2393 gpio-controller;
2394 #gpio-cells = <2>;
2395 interrupt-controller;
2396 #interrupt-cells = <2>;
2397 gpio-ranges = <&tlmm 0 0 151>;
2398 wakeup-parent = <&pdc_intc>;
2400 cci0_default: cci0-default {
2405 bias-pull-up;
2406 drive-strength = <2>; /* 2 mA */
2409 cci0_sleep: cci0-sleep {
2414 drive-strength = <2>; /* 2 mA */
2415 bias-pull-down;
2418 cci1_default: cci1-default {
2423 bias-pull-up;
2424 drive-strength = <2>; /* 2 mA */
2427 cci1_sleep: cci1-sleep {
2432 drive-strength = <2>; /* 2 mA */
2433 bias-pull-down;
2436 qspi_clk: qspi-clk {
2443 qspi_cs0: qspi-cs0 {
2450 qspi_cs1: qspi-cs1 {
2457 qspi_data01: qspi-data01 {
2458 pinmux-data {
2464 qspi_data12: qspi-data12 {
2465 pinmux-data {
2471 qup_i2c0_default: qup-i2c0-default {
2478 qup_i2c1_default: qup-i2c1-default {
2485 qup_i2c2_default: qup-i2c2-default {
2492 qup_i2c3_default: qup-i2c3-default {
2499 qup_i2c4_default: qup-i2c4-default {
2506 qup_i2c5_default: qup-i2c5-default {
2513 qup_i2c6_default: qup-i2c6-default {
2520 qup_i2c7_default: qup-i2c7-default {
2527 qup_i2c8_default: qup-i2c8-default {
2534 qup_i2c9_default: qup-i2c9-default {
2541 qup_i2c10_default: qup-i2c10-default {
2548 qup_i2c11_default: qup-i2c11-default {
2555 qup_i2c12_default: qup-i2c12-default {
2562 qup_i2c13_default: qup-i2c13-default {
2569 qup_i2c14_default: qup-i2c14-default {
2576 qup_i2c15_default: qup-i2c15-default {
2583 qup_spi0_default: qup-spi0-default {
2591 qup_spi1_default: qup-spi1-default {
2599 qup_spi2_default: qup-spi2-default {
2607 qup_spi3_default: qup-spi3-default {
2615 qup_spi4_default: qup-spi4-default {
2623 qup_spi5_default: qup-spi5-default {
2631 qup_spi6_default: qup-spi6-default {
2639 qup_spi7_default: qup-spi7-default {
2647 qup_spi8_default: qup-spi8-default {
2655 qup_spi9_default: qup-spi9-default {
2663 qup_spi10_default: qup-spi10-default {
2671 qup_spi11_default: qup-spi11-default {
2679 qup_spi12_default: qup-spi12-default {
2687 qup_spi13_default: qup-spi13-default {
2695 qup_spi14_default: qup-spi14-default {
2703 qup_spi15_default: qup-spi15-default {
2711 qup_uart0_default: qup-uart0-default {
2718 qup_uart1_default: qup-uart1-default {
2725 qup_uart2_default: qup-uart2-default {
2732 qup_uart3_default: qup-uart3-default {
2739 qup_uart4_default: qup-uart4-default {
2746 qup_uart5_default: qup-uart5-default {
2753 qup_uart6_default: qup-uart6-default {
2760 qup_uart7_default: qup-uart7-default {
2767 qup_uart8_default: qup-uart8-default {
2774 qup_uart9_default: qup-uart9-default {
2781 qup_uart10_default: qup-uart10-default {
2788 qup_uart11_default: qup-uart11-default {
2795 qup_uart12_default: qup-uart12-default {
2802 qup_uart13_default: qup-uart13-default {
2809 qup_uart14_default: qup-uart14-default {
2816 qup_uart15_default: qup-uart15-default {
2831 drive-strength = <2>;
2832 bias-pull-down;
2833 input-enable;
2845 drive-strength = <8>;
2846 bias-disable;
2847 output-high;
2859 drive-strength = <2>;
2860 bias-pull-down;
2861 input-enable;
2873 drive-strength = <8>;
2874 bias-disable;
2886 drive-strength = <2>;
2887 bias-pull-down;
2888 input-enable;
2900 drive-strength = <8>;
2901 bias-disable;
2913 drive-strength = <2>;
2914 bias-pull-down;
2915 input-enable;
2927 drive-strength = <8>;
2928 bias-disable;
2940 drive-strength = <2>;
2941 bias-pull-down;
2942 input-enable;
2954 drive-strength = <8>;
2955 bias-disable;
2961 compatible = "qcom,sdm845-mss-pil";
2963 reg-names = "qdsp6", "rmb";
2965 interrupts-extended =
2972 interrupt-names = "wdog", "fatal", "ready",
2973 "handover", "stop-ack",
2974 "shutdown-ack";
2984 clock-names = "iface", "bus", "mem", "gpll0_mss",
2987 qcom,smem-states = <&modem_smp2p_out 0>;
2988 qcom,smem-state-names = "stop";
2992 reset-names = "mss_restart", "pdc_reset";
2994 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
2996 power-domains = <&aoss_qmp 2>,
3000 power-domain-names = "load_state", "cx", "mx", "mss";
3003 memory-region = <&mba_region>;
3007 memory-region = <&mpss_region>;
3010 glink-edge {
3013 qcom,remote-pid = <1>;
3018 gpucc: clock-controller@5090000 {
3019 compatible = "qcom,sdm845-gpucc";
3021 #clock-cells = <1>;
3022 #reset-cells = <1>;
3023 #power-domain-cells = <1>;
3027 clock-names = "bi_tcxo",
3033 compatible = "arm,coresight-stm", "arm,primecell";
3036 reg-names = "stm-base", "stm-stimulus-base";
3039 clock-names = "apb_pclk";
3041 out-ports {
3044 remote-endpoint =
3052 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3056 clock-names = "apb_pclk";
3058 out-ports {
3061 remote-endpoint =
3067 in-ports {
3068 #address-cells = <1>;
3069 #size-cells = <0>;
3074 remote-endpoint = <&stm_out>;
3081 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3085 clock-names = "apb_pclk";
3087 out-ports {
3090 remote-endpoint =
3096 in-ports {
3097 #address-cells = <1>;
3098 #size-cells = <0>;
3103 remote-endpoint =
3111 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3115 clock-names = "apb_pclk";
3117 out-ports {
3120 remote-endpoint = <&etf_in>;
3125 in-ports {
3126 #address-cells = <1>;
3127 #size-cells = <0>;
3132 remote-endpoint =
3140 remote-endpoint =
3148 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3152 clock-names = "apb_pclk";
3154 out-ports {
3157 remote-endpoint = <&etr_in>;
3162 in-ports {
3165 remote-endpoint = <&etf_out>;
3172 compatible = "arm,coresight-tmc", "arm,primecell";
3176 clock-names = "apb_pclk";
3178 out-ports {
3181 remote-endpoint =
3187 in-ports {
3188 #address-cells = <1>;
3189 #size-cells = <0>;
3194 remote-endpoint =
3202 compatible = "arm,coresight-tmc", "arm,primecell";
3206 clock-names = "apb_pclk";
3207 arm,scatter-gather;
3209 in-ports {
3212 remote-endpoint =
3220 compatible = "arm,coresight-etm4x", "arm,primecell";
3226 clock-names = "apb_pclk";
3227 arm,coresight-loses-context-with-cpu;
3229 out-ports {
3232 remote-endpoint =
3240 compatible = "arm,coresight-etm4x", "arm,primecell";
3246 clock-names = "apb_pclk";
3247 arm,coresight-loses-context-with-cpu;
3249 out-ports {
3252 remote-endpoint =
3260 compatible = "arm,coresight-etm4x", "arm,primecell";
3266 clock-names = "apb_pclk";
3267 arm,coresight-loses-context-with-cpu;
3269 out-ports {
3272 remote-endpoint =
3280 compatible = "arm,coresight-etm4x", "arm,primecell";
3286 clock-names = "apb_pclk";
3287 arm,coresight-loses-context-with-cpu;
3289 out-ports {
3292 remote-endpoint =
3300 compatible = "arm,coresight-etm4x", "arm,primecell";
3306 clock-names = "apb_pclk";
3307 arm,coresight-loses-context-with-cpu;
3309 out-ports {
3312 remote-endpoint =
3320 compatible = "arm,coresight-etm4x", "arm,primecell";
3326 clock-names = "apb_pclk";
3327 arm,coresight-loses-context-with-cpu;
3329 out-ports {
3332 remote-endpoint =
3340 compatible = "arm,coresight-etm4x", "arm,primecell";
3346 clock-names = "apb_pclk";
3347 arm,coresight-loses-context-with-cpu;
3349 out-ports {
3352 remote-endpoint =
3360 compatible = "arm,coresight-etm4x", "arm,primecell";
3366 clock-names = "apb_pclk";
3367 arm,coresight-loses-context-with-cpu;
3369 out-ports {
3372 remote-endpoint =
3380 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3384 clock-names = "apb_pclk";
3386 out-ports {
3389 remote-endpoint =
3395 in-ports {
3396 #address-cells = <1>;
3397 #size-cells = <0>;
3402 remote-endpoint =
3410 remote-endpoint =
3418 remote-endpoint =
3426 remote-endpoint =
3434 remote-endpoint =
3442 remote-endpoint =
3450 remote-endpoint =
3458 remote-endpoint =
3466 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3470 clock-names = "apb_pclk";
3472 out-ports {
3475 remote-endpoint =
3481 in-ports {
3484 remote-endpoint =
3492 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3497 interrupt-names = "hc_irq", "pwr_irq";
3501 clock-names = "iface", "core";
3503 power-domains = <&rpmhpd SDM845_CX>;
3504 operating-points-v2 = <&sdhc2_opp_table>;
3508 sdhc2_opp_table: sdhc2-opp-table {
3509 compatible = "operating-points-v2";
3511 opp-9600000 {
3512 opp-hz = /bits/ 64 <9600000>;
3513 required-opps = <&rpmhpd_opp_min_svs>;
3516 opp-19200000 {
3517 opp-hz = /bits/ 64 <19200000>;
3518 required-opps = <&rpmhpd_opp_low_svs>;
3521 opp-100000000 {
3522 opp-hz = /bits/ 64 <100000000>;
3523 required-opps = <&rpmhpd_opp_svs>;
3526 opp-201500000 {
3527 opp-hz = /bits/ 64 <201500000>;
3528 required-opps = <&rpmhpd_opp_svs_l1>;
3533 qspi_opp_table: qspi-opp-table {
3534 compatible = "operating-points-v2";
3536 opp-19200000 {
3537 opp-hz = /bits/ 64 <19200000>;
3538 required-opps = <&rpmhpd_opp_min_svs>;
3541 opp-100000000 {
3542 opp-hz = /bits/ 64 <100000000>;
3543 required-opps = <&rpmhpd_opp_low_svs>;
3546 opp-150000000 {
3547 opp-hz = /bits/ 64 <150000000>;
3548 required-opps = <&rpmhpd_opp_svs>;
3551 opp-300000000 {
3552 opp-hz = /bits/ 64 <300000000>;
3553 required-opps = <&rpmhpd_opp_nom>;
3558 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3560 #address-cells = <1>;
3561 #size-cells = <0>;
3565 clock-names = "iface", "core";
3566 power-domains = <&rpmhpd SDM845_CX>;
3567 operating-points-v2 = <&qspi_opp_table>;
3572 compatible = "qcom,slim-ngd-v2.1.0";
3576 qcom,apps-ch-pipes = <0x780000>;
3577 qcom,ea-pc = <0x270>;
3581 dma-names = "rx", "tx", "tx2", "rx2";
3584 #address-cells = <1>;
3585 #size-cells = <0>;
3589 #address-cells = <2>;
3590 #size-cells = <0>;
3600 slim-ifc-dev = <&wcd9340_ifd>;
3602 #sound-dai-cells = <1>;
3604 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
3605 interrupt-controller;
3606 #interrupt-cells = <1>;
3608 #clock-cells = <0>;
3609 clock-frequency = <9600000>;
3610 clock-output-names = "mclk";
3611 qcom,micbias1-millivolt = <1800>;
3612 qcom,micbias2-millivolt = <1800>;
3613 qcom,micbias3-millivolt = <1800>;
3614 qcom,micbias4-millivolt = <1800>;
3616 #address-cells = <1>;
3617 #size-cells = <1>;
3619 wcdgpio: gpio-controller@42 {
3620 compatible = "qcom,wcd9340-gpio";
3621 gpio-controller;
3622 #gpio-cells = <2>;
3627 compatible = "qcom,soundwire-v1.3.0";
3629 interrupts-extended = <&wcd9340 20>;
3631 qcom,dout-ports = <6>;
3632 qcom,din-ports = <2>;
3633 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
3634 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
3635 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
3637 #sound-dai-cells = <1>;
3639 clock-names = "iface";
3640 #address-cells = <2>;
3641 #size-cells = <0>;
3652 usb_1_hsphy: phy@88e2000 {
3653 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3656 #phy-cells = <0>;
3660 clock-names = "cfg_ahb", "ref";
3664 nvmem-cells = <&qusb2p_hstx_trim>;
3667 usb_2_hsphy: phy@88e3000 {
3668 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3671 #phy-cells = <0>;
3675 clock-names = "cfg_ahb", "ref";
3679 nvmem-cells = <&qusb2s_hstx_trim>;
3682 usb_1_qmpphy: phy@88e9000 {
3683 compatible = "qcom,sdm845-qmp-usb3-phy";
3686 reg-names = "reg-base", "dp_com";
3688 #address-cells = <2>;
3689 #size-cells = <2>;
3696 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3700 reset-names = "phy", "common";
3709 #clock-cells = <0>;
3710 #phy-cells = <0>;
3712 clock-names = "pipe0";
3713 clock-output-names = "usb3_phy_pipe_clk_src";
3717 usb_2_qmpphy: phy@88eb000 {
3718 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
3721 #address-cells = <2>;
3722 #size-cells = <2>;
3729 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3733 reset-names = "phy", "common";
3740 #clock-cells = <0>;
3741 #phy-cells = <0>;
3743 clock-names = "pipe0";
3744 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3749 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3752 #address-cells = <2>;
3753 #size-cells = <2>;
3755 dma-ranges;
3762 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3765 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3767 assigned-clock-rates = <19200000>, <150000000>;
3773 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3776 power-domains = <&gcc USB30_PRIM_GDSC>;
3782 interconnect-names = "usb-ddr", "apps-usb";
3792 phy-names = "usb2-phy", "usb3-phy";
3797 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3800 #address-cells = <2>;
3801 #size-cells = <2>;
3803 dma-ranges;
3810 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3813 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3815 assigned-clock-rates = <19200000>, <150000000>;
3821 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3824 power-domains = <&gcc USB30_SEC_GDSC>;
3830 interconnect-names = "usb-ddr", "apps-usb";
3840 phy-names = "usb2-phy", "usb3-phy";
3844 venus: video-codec@aa00000 {
3845 compatible = "qcom,sdm845-venus-v2";
3848 power-domains = <&videocc VENUS_GDSC>,
3852 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
3853 operating-points-v2 = <&venus_opp_table>;
3861 clock-names = "core", "iface", "bus",
3866 memory-region = <&venus_mem>;
3869 interconnect-names = "video-mem", "cpu-cfg";
3871 video-core0 {
3872 compatible = "venus-decoder";
3875 video-core1 {
3876 compatible = "venus-encoder";
3879 venus_opp_table: venus-opp-table {
3880 compatible = "operating-points-v2";
3882 opp-100000000 {
3883 opp-hz = /bits/ 64 <100000000>;
3884 required-opps = <&rpmhpd_opp_min_svs>;
3887 opp-200000000 {
3888 opp-hz = /bits/ 64 <200000000>;
3889 required-opps = <&rpmhpd_opp_low_svs>;
3892 opp-320000000 {
3893 opp-hz = /bits/ 64 <320000000>;
3894 required-opps = <&rpmhpd_opp_svs>;
3897 opp-380000000 {
3898 opp-hz = /bits/ 64 <380000000>;
3899 required-opps = <&rpmhpd_opp_svs_l1>;
3902 opp-444000000 {
3903 opp-hz = /bits/ 64 <444000000>;
3904 required-opps = <&rpmhpd_opp_nom>;
3907 opp-533000097 {
3908 opp-hz = /bits/ 64 <533000097>;
3909 required-opps = <&rpmhpd_opp_turbo>;
3914 videocc: clock-controller@ab00000 {
3915 compatible = "qcom,sdm845-videocc";
3918 clock-names = "bi_tcxo";
3919 #clock-cells = <1>;
3920 #power-domain-cells = <1>;
3921 #reset-cells = <1>;
3925 compatible = "qcom,sdm845-camss";
3937 reg-names = "csid0",
3958 interrupt-names = "csid0",
3969 power-domains = <&clock_camcc IFE_0_GDSC>,
4009 clock-names = "camnoc_axi",
4054 #address-cells = <1>;
4055 #size-cells = <0>;
4060 compatible = "qcom,sdm845-cci";
4061 #address-cells = <1>;
4062 #size-cells = <0>;
4066 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4074 clock-names = "camnoc_axi",
4081 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4083 assigned-clock-rates = <80000000>, <37500000>;
4085 pinctrl-names = "default", "sleep";
4086 pinctrl-0 = <&cci0_default &cci1_default>;
4087 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4091 cci_i2c0: i2c-bus@0 {
4093 clock-frequency = <1000000>;
4094 #address-cells = <1>;
4095 #size-cells = <0>;
4098 cci_i2c1: i2c-bus@1 {
4100 clock-frequency = <1000000>;
4101 #address-cells = <1>;
4102 #size-cells = <0>;
4106 clock_camcc: clock-controller@ad00000 {
4107 compatible = "qcom,sdm845-camcc";
4109 #clock-cells = <1>;
4110 #reset-cells = <1>;
4111 #power-domain-cells = <1>;
4114 dsi_opp_table: dsi-opp-table {
4115 compatible = "operating-points-v2";
4117 opp-19200000 {
4118 opp-hz = /bits/ 64 <19200000>;
4119 required-opps = <&rpmhpd_opp_min_svs>;
4122 opp-180000000 {
4123 opp-hz = /bits/ 64 <180000000>;
4124 required-opps = <&rpmhpd_opp_low_svs>;
4127 opp-275000000 {
4128 opp-hz = /bits/ 64 <275000000>;
4129 required-opps = <&rpmhpd_opp_svs>;
4132 opp-328580000 {
4133 opp-hz = /bits/ 64 <328580000>;
4134 required-opps = <&rpmhpd_opp_svs_l1>;
4137 opp-358000000 {
4138 opp-hz = /bits/ 64 <358000000>;
4139 required-opps = <&rpmhpd_opp_nom>;
4144 compatible = "qcom,sdm845-mdss";
4146 reg-names = "mdss";
4148 power-domains = <&dispcc MDSS_GDSC>;
4152 clock-names = "iface", "core";
4154 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
4155 assigned-clock-rates = <300000000>;
4158 interrupt-controller;
4159 #interrupt-cells = <1>;
4163 interconnect-names = "mdp0-mem", "mdp1-mem";
4170 #address-cells = <2>;
4171 #size-cells = <2>;
4175 compatible = "qcom,sdm845-dpu";
4178 reg-names = "mdp", "vbif";
4185 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4187 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4189 assigned-clock-rates = <300000000>,
4191 operating-points-v2 = <&mdp_opp_table>;
4192 power-domains = <&rpmhpd SDM845_CX>;
4194 interrupt-parent = <&mdss>;
4200 #address-cells = <1>;
4201 #size-cells = <0>;
4206 remote-endpoint = <&dsi0_in>;
4213 remote-endpoint = <&dsi1_in>;
4218 mdp_opp_table: mdp-opp-table {
4219 compatible = "operating-points-v2";
4221 opp-19200000 {
4222 opp-hz = /bits/ 64 <19200000>;
4223 required-opps = <&rpmhpd_opp_min_svs>;
4226 opp-171428571 {
4227 opp-hz = /bits/ 64 <171428571>;
4228 required-opps = <&rpmhpd_opp_low_svs>;
4231 opp-344000000 {
4232 opp-hz = /bits/ 64 <344000000>;
4233 required-opps = <&rpmhpd_opp_svs_l1>;
4236 opp-430000000 {
4237 opp-hz = /bits/ 64 <430000000>;
4238 required-opps = <&rpmhpd_opp_nom>;
4244 compatible = "qcom,mdss-dsi-ctrl";
4246 reg-names = "dsi_ctrl";
4248 interrupt-parent = <&mdss>;
4257 clock-names = "byte",
4263 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4264 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4266 operating-points-v2 = <&dsi_opp_table>;
4267 power-domains = <&rpmhpd SDM845_CX>;
4270 phy-names = "dsi";
4275 #address-cells = <1>;
4276 #size-cells = <0>;
4281 remote-endpoint = <&dpu_intf1_out>;
4293 dsi0_phy: dsi-phy@ae94400 {
4294 compatible = "qcom,dsi-phy-10nm";
4298 reg-names = "dsi_phy",
4302 #clock-cells = <1>;
4303 #phy-cells = <0>;
4307 clock-names = "iface", "ref";
4313 compatible = "qcom,mdss-dsi-ctrl";
4315 reg-names = "dsi_ctrl";
4317 interrupt-parent = <&mdss>;
4326 clock-names = "byte",
4332 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4333 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4335 operating-points-v2 = <&dsi_opp_table>;
4336 power-domains = <&rpmhpd SDM845_CX>;
4339 phy-names = "dsi";
4344 #address-cells = <1>;
4345 #size-cells = <0>;
4350 remote-endpoint = <&dpu_intf2_out>;
4362 dsi1_phy: dsi-phy@ae96400 {
4363 compatible = "qcom,dsi-phy-10nm";
4367 reg-names = "dsi_phy",
4371 #clock-cells = <1>;
4372 #phy-cells = <0>;
4376 clock-names = "iface", "ref";
4383 compatible = "qcom,adreno-630.2", "qcom,adreno";
4384 #stream-id-cells = <16>;
4387 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4398 operating-points-v2 = <&gpu_opp_table>;
4400 qcom,gmu = <&gmu>;
4403 interconnect-names = "gfx-mem";
4405 gpu_opp_table: opp-table {
4406 compatible = "operating-points-v2";
4408 opp-710000000 {
4409 opp-hz = /bits/ 64 <710000000>;
4410 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4411 opp-peak-kBps = <7216000>;
4414 opp-675000000 {
4415 opp-hz = /bits/ 64 <675000000>;
4416 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4417 opp-peak-kBps = <7216000>;
4420 opp-596000000 {
4421 opp-hz = /bits/ 64 <596000000>;
4422 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4423 opp-peak-kBps = <6220000>;
4426 opp-520000000 {
4427 opp-hz = /bits/ 64 <520000000>;
4428 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4429 opp-peak-kBps = <6220000>;
4432 opp-414000000 {
4433 opp-hz = /bits/ 64 <414000000>;
4434 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4435 opp-peak-kBps = <4068000>;
4438 opp-342000000 {
4439 opp-hz = /bits/ 64 <342000000>;
4440 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4441 opp-peak-kBps = <2724000>;
4444 opp-257000000 {
4445 opp-hz = /bits/ 64 <257000000>;
4446 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4447 opp-peak-kBps = <1648000>;
4453 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4455 #iommu-cells = <1>;
4456 #global-interrupts = <2>;
4469 clock-names = "bus", "iface";
4471 power-domains = <&gpucc GPU_CX_GDSC>;
4475 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4480 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4484 interrupt-names = "hfi", "gmu";
4490 clock-names = "gmu", "cxo", "axi", "memnoc";
4492 power-domains = <&gpucc GPU_CX_GDSC>,
4494 power-domain-names = "cx", "gx";
4498 operating-points-v2 = <&gmu_opp_table>;
4500 gmu_opp_table: opp-table {
4501 compatible = "operating-points-v2";
4503 opp-400000000 {
4504 opp-hz = /bits/ 64 <400000000>;
4505 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4508 opp-200000000 {
4509 opp-hz = /bits/ 64 <200000000>;
4510 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4515 dispcc: clock-controller@af00000 {
4516 compatible = "qcom,sdm845-dispcc";
4527 clock-names = "bi_tcxo",
4536 #clock-cells = <1>;
4537 #reset-cells = <1>;
4538 #power-domain-cells = <1>;
4541 pdc_intc: interrupt-controller@b220000 {
4542 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4544 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4545 #interrupt-cells = <2>;
4546 interrupt-parent = <&intc>;
4547 interrupt-controller;
4550 pdc_reset: reset-controller@b2e0000 {
4551 compatible = "qcom,sdm845-pdc-global";
4553 #reset-cells = <1>;
4556 tsens0: thermal-sensor@c263000 {
4557 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4560 #qcom,sensors = <13>;
4563 interrupt-names = "uplow", "critical";
4564 #thermal-sensor-cells = <1>;
4567 tsens1: thermal-sensor@c265000 {
4568 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4571 #qcom,sensors = <8>;
4574 interrupt-names = "uplow", "critical";
4575 #thermal-sensor-cells = <1>;
4578 aoss_reset: reset-controller@c2a0000 {
4579 compatible = "qcom,sdm845-aoss-cc";
4581 #reset-cells = <1>;
4584 aoss_qmp: power-controller@c300000 {
4585 compatible = "qcom,sdm845-aoss-qmp";
4590 #clock-cells = <0>;
4591 #power-domain-cells = <1>;
4594 #cooling-cells = <2>;
4598 #cooling-cells = <2>;
4603 compatible = "qcom,spmi-pmic-arb";
4609 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4610 interrupt-names = "periph_irq";
4612 qcom,ee = <0>;
4613 qcom,channel = <0>;
4614 #address-cells = <2>;
4615 #size-cells = <0>;
4616 interrupt-controller;
4617 #interrupt-cells = <4>;
4618 cell-index = <0>;
4622 compatible = "simple-mfd";
4625 #address-cells = <1>;
4626 #size-cells = <1>;
4630 pil-reloc@94c {
4631 compatible = "qcom,pil-reloc-info";
4637 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
4639 #iommu-cells = <2>;
4640 #global-interrupts = <1>;
4708 lpasscc: clock-controller@17014000 {
4709 compatible = "qcom,sdm845-lpasscc";
4711 reg-names = "cc", "qdsp6ss";
4712 #clock-cells = <1>;
4717 compatible = "qcom,sdm845-gladiator-noc";
4719 #interconnect-cells = <2>;
4720 qcom,bcm-voters = <&apps_bcm_voter>;
4724 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
4731 compatible = "qcom,sdm845-apss-shared";
4733 #mbox-cells = <1>;
4738 compatible = "qcom,rpmh-rsc";
4742 reg-names = "drv-0", "drv-1", "drv-2";
4746 qcom,tcs-offset = <0xd00>;
4747 qcom,drv-id = <2>;
4748 qcom,tcs-config = <ACTIVE_TCS 2>,
4753 apps_bcm_voter: bcm-voter {
4754 compatible = "qcom,bcm-voter";
4757 rpmhcc: clock-controller {
4758 compatible = "qcom,sdm845-rpmh-clk";
4759 #clock-cells = <1>;
4760 clock-names = "xo";
4764 rpmhpd: power-controller {
4765 compatible = "qcom,sdm845-rpmhpd";
4766 #power-domain-cells = <1>;
4767 operating-points-v2 = <&rpmhpd_opp_table>;
4769 rpmhpd_opp_table: opp-table {
4770 compatible = "operating-points-v2";
4773 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4777 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4781 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4785 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4789 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4793 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4797 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4801 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4805 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4809 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4815 intc: interrupt-controller@17a00000 {
4816 compatible = "arm,gic-v3";
4817 #address-cells = <2>;
4818 #size-cells = <2>;
4820 #interrupt-cells = <3>;
4821 interrupt-controller;
4826 msi-controller@17a40000 {
4827 compatible = "arm,gic-v3-its";
4828 msi-controller;
4829 #msi-cells = <1>;
4835 slimbam: dma-controller@17184000 {
4836 compatible = "qcom,bam-v1.7.0";
4837 qcom,controlled-remotely;
4839 num-channels = <31>;
4841 #dma-cells = <1>;
4842 qcom,ee = <1>;
4843 qcom,num-ees = <2>;
4848 #address-cells = <2>;
4849 #size-cells = <2>;
4851 compatible = "arm,armv7-timer-mem";
4855 frame-number = <0>;
4863 frame-number = <1>;
4870 frame-number = <2>;
4877 frame-number = <3>;
4884 frame-number = <4>;
4891 frame-number = <5>;
4898 frame-number = <6>;
4906 compatible = "qcom,sdm845-osm-l3";
4910 clock-names = "xo", "alternate";
4912 #interconnect-cells = <1>;
4916 compatible = "qcom,cpufreq-hw";
4918 reg-names = "freq-domain0", "freq-domain1";
4921 clock-names = "xo", "alternate";
4923 #freq-domain-cells = <1>;
4927 compatible = "qcom,wcn3990-wifi";
4930 reg-names = "membase";
4931 memory-region = <&wlan_msa_mem>;
4932 clock-names = "cxo_ref_clk_pin";
4951 thermal-zones {
4952 cpu0-thermal {
4953 polling-delay-passive = <250>;
4954 polling-delay = <1000>;
4956 thermal-sensors = <&tsens0 1>;
4959 cpu0_alert0: trip-point0 {
4965 cpu0_alert1: trip-point1 {
4978 cooling-maps {
4981 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4988 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4996 cpu1-thermal {
4997 polling-delay-passive = <250>;
4998 polling-delay = <1000>;
5000 thermal-sensors = <&tsens0 2>;
5003 cpu1_alert0: trip-point0 {
5009 cpu1_alert1: trip-point1 {
5022 cooling-maps {
5025 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5032 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5040 cpu2-thermal {
5041 polling-delay-passive = <250>;
5042 polling-delay = <1000>;
5044 thermal-sensors = <&tsens0 3>;
5047 cpu2_alert0: trip-point0 {
5053 cpu2_alert1: trip-point1 {
5066 cooling-maps {
5069 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5076 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5084 cpu3-thermal {
5085 polling-delay-passive = <250>;
5086 polling-delay = <1000>;
5088 thermal-sensors = <&tsens0 4>;
5091 cpu3_alert0: trip-point0 {
5097 cpu3_alert1: trip-point1 {
5110 cooling-maps {
5113 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5120 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5128 cpu4-thermal {
5129 polling-delay-passive = <250>;
5130 polling-delay = <1000>;
5132 thermal-sensors = <&tsens0 7>;
5135 cpu4_alert0: trip-point0 {
5141 cpu4_alert1: trip-point1 {
5154 cooling-maps {
5157 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5164 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5172 cpu5-thermal {
5173 polling-delay-passive = <250>;
5174 polling-delay = <1000>;
5176 thermal-sensors = <&tsens0 8>;
5179 cpu5_alert0: trip-point0 {
5185 cpu5_alert1: trip-point1 {
5198 cooling-maps {
5201 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5208 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5216 cpu6-thermal {
5217 polling-delay-passive = <250>;
5218 polling-delay = <1000>;
5220 thermal-sensors = <&tsens0 9>;
5223 cpu6_alert0: trip-point0 {
5229 cpu6_alert1: trip-point1 {
5242 cooling-maps {
5245 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5252 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5260 cpu7-thermal {
5261 polling-delay-passive = <250>;
5262 polling-delay = <1000>;
5264 thermal-sensors = <&tsens0 10>;
5267 cpu7_alert0: trip-point0 {
5273 cpu7_alert1: trip-point1 {
5286 cooling-maps {
5289 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5296 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5304 aoss0-thermal {
5305 polling-delay-passive = <250>;
5306 polling-delay = <1000>;
5308 thermal-sensors = <&tsens0 0>;
5311 aoss0_alert0: trip-point0 {
5319 cluster0-thermal {
5320 polling-delay-passive = <250>;
5321 polling-delay = <1000>;
5323 thermal-sensors = <&tsens0 5>;
5326 cluster0_alert0: trip-point0 {
5339 cluster1-thermal {
5340 polling-delay-passive = <250>;
5341 polling-delay = <1000>;
5343 thermal-sensors = <&tsens0 6>;
5346 cluster1_alert0: trip-point0 {
5359 gpu-thermal-top {
5360 polling-delay-passive = <250>;
5361 polling-delay = <1000>;
5363 thermal-sensors = <&tsens0 11>;
5366 gpu1_alert0: trip-point0 {
5374 gpu-thermal-bottom {
5375 polling-delay-passive = <250>;
5376 polling-delay = <1000>;
5378 thermal-sensors = <&tsens0 12>;
5381 gpu2_alert0: trip-point0 {
5389 aoss1-thermal {
5390 polling-delay-passive = <250>;
5391 polling-delay = <1000>;
5393 thermal-sensors = <&tsens1 0>;
5396 aoss1_alert0: trip-point0 {
5404 q6-modem-thermal {
5405 polling-delay-passive = <250>;
5406 polling-delay = <1000>;
5408 thermal-sensors = <&tsens1 1>;
5411 q6_modem_alert0: trip-point0 {
5419 mem-thermal {
5420 polling-delay-passive = <250>;
5421 polling-delay = <1000>;
5423 thermal-sensors = <&tsens1 2>;
5426 mem_alert0: trip-point0 {
5434 wlan-thermal {
5435 polling-delay-passive = <250>;
5436 polling-delay = <1000>;
5438 thermal-sensors = <&tsens1 3>;
5441 wlan_alert0: trip-point0 {
5449 q6-hvx-thermal {
5450 polling-delay-passive = <250>;
5451 polling-delay = <1000>;
5453 thermal-sensors = <&tsens1 4>;
5456 q6_hvx_alert0: trip-point0 {
5464 camera-thermal {
5465 polling-delay-passive = <250>;
5466 polling-delay = <1000>;
5468 thermal-sensors = <&tsens1 5>;
5471 camera_alert0: trip-point0 {
5479 video-thermal {
5480 polling-delay-passive = <250>;
5481 polling-delay = <1000>;
5483 thermal-sensors = <&tsens1 6>;
5486 video_alert0: trip-point0 {
5494 modem-thermal {
5495 polling-delay-passive = <250>;
5496 polling-delay = <1000>;
5498 thermal-sensors = <&tsens1 7>;
5501 modem_alert0: trip-point0 {