Lines Matching +full:0 +full:x008c0000
73 reg = <0 0x80000000 0 0>;
82 reg = <0 0x85700000 0 0x600000>;
87 reg = <0 0x85e00000 0 0x100000>;
92 reg = <0 0x85fc0000 0 0x20000>;
98 reg = <0x0 0x85fe0000 0 0x20000>;
103 reg = <0x0 0x86000000 0 0x200000>;
108 reg = <0 0x86200000 0 0x2d00000>;
114 reg = <0 0x88f00000 0 0x200000>;
122 reg = <0 0x8ab00000 0 0x1400000>;
127 reg = <0 0x8bf00000 0 0x500000>;
132 reg = <0 0x8c400000 0 0x10000>;
137 reg = <0 0x8c410000 0 0x5000>;
142 reg = <0 0x8c415000 0 0x2000>;
147 reg = <0 0x8c500000 0 0x1a00000>;
152 reg = <0 0x8df00000 0 0x100000>;
157 reg = <0 0x8e000000 0 0x7800000>;
162 reg = <0 0x95800000 0 0x500000>;
167 reg = <0 0x95d00000 0 0x800000>;
172 reg = <0 0x96500000 0 0x200000>;
177 reg = <0 0x96700000 0 0x1400000>;
182 reg = <0 0x97b00000 0 0x100000>;
189 #size-cells = <0>;
191 CPU0: cpu@0 {
194 reg = <0x0 0x0>;
201 qcom,freq-domain = <&cpufreq_hw 0>;
219 reg = <0x0 0x100>;
226 qcom,freq-domain = <&cpufreq_hw 0>;
241 reg = <0x0 0x200>;
248 qcom,freq-domain = <&cpufreq_hw 0>;
263 reg = <0x0 0x300>;
270 qcom,freq-domain = <&cpufreq_hw 0>;
285 reg = <0x0 0x400>;
307 reg = <0x0 0x500>;
329 reg = <0x0 0x600>;
351 reg = <0x0 0x700>;
409 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
412 arm,psci-suspend-param = <0x40000003>;
419 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
422 arm,psci-suspend-param = <0x40000004>;
429 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
432 arm,psci-suspend-param = <0x40000003>;
442 arm,psci-suspend-param = <0x40000004>;
449 CLUSTER_SLEEP_0: cluster-sleep-0 {
452 arm,psci-suspend-param = <0x400000F4>;
731 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
737 #clock-cells = <0>;
744 #clock-cells = <0>;
759 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
771 qcom,smem-states = <&adsp_smp2p_out 0>;
787 #size-cells = <0>;
803 #size-cells = <0>;
815 #size-cells = <0>;
817 iommus = <&apps_smmu 0x1821 0x0>;
827 #sound-dai-cells = <0>;
837 #size-cells = <0>;
842 iommus = <&apps_smmu 0x1823 0x0>;
848 iommus = <&apps_smmu 0x1824 0x0>;
858 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
870 qcom,smem-states = <&cdsp_smp2p_out 0>;
885 #size-cells = <0>;
890 iommus = <&apps_smmu 0x1401 0x30>;
896 iommus = <&apps_smmu 0x1402 0x30>;
902 iommus = <&apps_smmu 0x1403 0x30>;
908 iommus = <&apps_smmu 0x1404 0x30>;
914 iommus = <&apps_smmu 0x1405 0x30>;
920 iommus = <&apps_smmu 0x1406 0x30>;
926 iommus = <&apps_smmu 0x1407 0x30>;
932 iommus = <&apps_smmu 0x1408 0x30>;
940 syscon = <&tcsr_mutex_regs 0 0x1000>;
958 qcom,local-pid = <0>;
982 qcom,local-pid = <0>;
1003 qcom,local-pid = <0>;
1034 qcom,local-pid = <0>;
1054 soc: soc@0 {
1057 ranges = <0 0 0 0 0x10 0>;
1058 dma-ranges = <0 0 0 0 0x10 0>;
1063 reg = <0 0x00100000 0 0x1f0000>;
1081 reg = <0 0x00784000 0 0x8ff>;
1086 reg = <0x1eb 0x1>;
1091 reg = <0x1eb 0x2>;
1098 reg = <0 0x00793000 0 0x1000>;
1129 reg = <0 0x008c0000 0 0x6000>;
1133 iommus = <&apps_smmu 0x3 0x0>;
1137 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1143 reg = <0 0x00880000 0 0x4000>;
1147 pinctrl-0 = <&qup_i2c0_default>;
1150 #size-cells = <0>;
1153 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1154 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1155 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1162 reg = <0 0x00880000 0 0x4000>;
1166 pinctrl-0 = <&qup_spi0_default>;
1169 #size-cells = <0>;
1170 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1171 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1178 reg = <0 0x00880000 0 0x4000>;
1182 pinctrl-0 = <&qup_uart0_default>;
1186 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1187 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1194 reg = <0 0x00884000 0 0x4000>;
1198 pinctrl-0 = <&qup_i2c1_default>;
1201 #size-cells = <0>;
1204 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1205 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1206 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1213 reg = <0 0x00884000 0 0x4000>;
1217 pinctrl-0 = <&qup_spi1_default>;
1220 #size-cells = <0>;
1221 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1222 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1229 reg = <0 0x00884000 0 0x4000>;
1233 pinctrl-0 = <&qup_uart1_default>;
1237 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1238 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1245 reg = <0 0x00888000 0 0x4000>;
1249 pinctrl-0 = <&qup_i2c2_default>;
1252 #size-cells = <0>;
1255 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1256 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1257 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1264 reg = <0 0x00888000 0 0x4000>;
1268 pinctrl-0 = <&qup_spi2_default>;
1271 #size-cells = <0>;
1272 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1273 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1280 reg = <0 0x00888000 0 0x4000>;
1284 pinctrl-0 = <&qup_uart2_default>;
1288 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1289 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1296 reg = <0 0x0088c000 0 0x4000>;
1300 pinctrl-0 = <&qup_i2c3_default>;
1303 #size-cells = <0>;
1306 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1307 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1308 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1315 reg = <0 0x0088c000 0 0x4000>;
1319 pinctrl-0 = <&qup_spi3_default>;
1322 #size-cells = <0>;
1323 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1324 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1331 reg = <0 0x0088c000 0 0x4000>;
1335 pinctrl-0 = <&qup_uart3_default>;
1339 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1340 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1347 reg = <0 0x00890000 0 0x4000>;
1351 pinctrl-0 = <&qup_i2c4_default>;
1354 #size-cells = <0>;
1357 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1358 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1359 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1366 reg = <0 0x00890000 0 0x4000>;
1370 pinctrl-0 = <&qup_spi4_default>;
1373 #size-cells = <0>;
1374 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1375 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1382 reg = <0 0x00890000 0 0x4000>;
1386 pinctrl-0 = <&qup_uart4_default>;
1390 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1391 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1398 reg = <0 0x00894000 0 0x4000>;
1402 pinctrl-0 = <&qup_i2c5_default>;
1405 #size-cells = <0>;
1408 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1409 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1410 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1417 reg = <0 0x00894000 0 0x4000>;
1421 pinctrl-0 = <&qup_spi5_default>;
1424 #size-cells = <0>;
1425 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1426 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1433 reg = <0 0x00894000 0 0x4000>;
1437 pinctrl-0 = <&qup_uart5_default>;
1441 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1442 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1449 reg = <0 0x00898000 0 0x4000>;
1453 pinctrl-0 = <&qup_i2c6_default>;
1456 #size-cells = <0>;
1459 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1460 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1461 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1468 reg = <0 0x00898000 0 0x4000>;
1472 pinctrl-0 = <&qup_spi6_default>;
1475 #size-cells = <0>;
1476 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1477 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1484 reg = <0 0x00898000 0 0x4000>;
1488 pinctrl-0 = <&qup_uart6_default>;
1492 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1493 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1500 reg = <0 0x0089c000 0 0x4000>;
1504 pinctrl-0 = <&qup_i2c7_default>;
1507 #size-cells = <0>;
1515 reg = <0 0x0089c000 0 0x4000>;
1519 pinctrl-0 = <&qup_spi7_default>;
1522 #size-cells = <0>;
1523 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1524 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1531 reg = <0 0x0089c000 0 0x4000>;
1535 pinctrl-0 = <&qup_uart7_default>;
1539 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1540 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1548 reg = <0 0x00ac0000 0 0x6000>;
1552 iommus = <&apps_smmu 0x6c3 0x0>;
1556 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1562 reg = <0 0x00a80000 0 0x4000>;
1566 pinctrl-0 = <&qup_i2c8_default>;
1569 #size-cells = <0>;
1572 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1573 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1574 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1581 reg = <0 0x00a80000 0 0x4000>;
1585 pinctrl-0 = <&qup_spi8_default>;
1588 #size-cells = <0>;
1589 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1590 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1597 reg = <0 0x00a80000 0 0x4000>;
1601 pinctrl-0 = <&qup_uart8_default>;
1605 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1606 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1613 reg = <0 0x00a84000 0 0x4000>;
1617 pinctrl-0 = <&qup_i2c9_default>;
1620 #size-cells = <0>;
1623 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1624 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1625 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1632 reg = <0 0x00a84000 0 0x4000>;
1636 pinctrl-0 = <&qup_spi9_default>;
1639 #size-cells = <0>;
1640 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1641 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1648 reg = <0 0x00a84000 0 0x4000>;
1652 pinctrl-0 = <&qup_uart9_default>;
1656 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1657 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1664 reg = <0 0x00a88000 0 0x4000>;
1668 pinctrl-0 = <&qup_i2c10_default>;
1671 #size-cells = <0>;
1674 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1675 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1676 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1683 reg = <0 0x00a88000 0 0x4000>;
1687 pinctrl-0 = <&qup_spi10_default>;
1690 #size-cells = <0>;
1691 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1692 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1699 reg = <0 0x00a88000 0 0x4000>;
1703 pinctrl-0 = <&qup_uart10_default>;
1707 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1708 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1715 reg = <0 0x00a8c000 0 0x4000>;
1719 pinctrl-0 = <&qup_i2c11_default>;
1722 #size-cells = <0>;
1725 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1726 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1727 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1734 reg = <0 0x00a8c000 0 0x4000>;
1738 pinctrl-0 = <&qup_spi11_default>;
1741 #size-cells = <0>;
1742 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1743 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1750 reg = <0 0x00a8c000 0 0x4000>;
1754 pinctrl-0 = <&qup_uart11_default>;
1758 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1759 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1766 reg = <0 0x00a90000 0 0x4000>;
1770 pinctrl-0 = <&qup_i2c12_default>;
1773 #size-cells = <0>;
1776 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1777 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1778 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1785 reg = <0 0x00a90000 0 0x4000>;
1789 pinctrl-0 = <&qup_spi12_default>;
1792 #size-cells = <0>;
1793 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1794 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1801 reg = <0 0x00a90000 0 0x4000>;
1805 pinctrl-0 = <&qup_uart12_default>;
1809 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1810 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1817 reg = <0 0x00a94000 0 0x4000>;
1821 pinctrl-0 = <&qup_i2c13_default>;
1824 #size-cells = <0>;
1827 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1828 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1829 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1836 reg = <0 0x00a94000 0 0x4000>;
1840 pinctrl-0 = <&qup_spi13_default>;
1843 #size-cells = <0>;
1844 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1845 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1852 reg = <0 0x00a94000 0 0x4000>;
1856 pinctrl-0 = <&qup_uart13_default>;
1860 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1861 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1868 reg = <0 0x00a98000 0 0x4000>;
1872 pinctrl-0 = <&qup_i2c14_default>;
1875 #size-cells = <0>;
1878 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1879 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1880 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1887 reg = <0 0x00a98000 0 0x4000>;
1891 pinctrl-0 = <&qup_spi14_default>;
1894 #size-cells = <0>;
1895 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1896 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1903 reg = <0 0x00a98000 0 0x4000>;
1907 pinctrl-0 = <&qup_uart14_default>;
1911 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1912 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1919 reg = <0 0x00a9c000 0 0x4000>;
1923 pinctrl-0 = <&qup_i2c15_default>;
1926 #size-cells = <0>;
1930 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1931 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1932 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1938 reg = <0 0x00a9c000 0 0x4000>;
1942 pinctrl-0 = <&qup_spi15_default>;
1945 #size-cells = <0>;
1946 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1947 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1954 reg = <0 0x00a9c000 0 0x4000>;
1958 pinctrl-0 = <&qup_uart15_default>;
1962 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1963 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1971 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
1978 reg = <0 0x01c00000 0 0x2000>,
1979 <0 0x60000000 0 0xf1d>,
1980 <0 0x60000f20 0 0xa8>,
1981 <0 0x60100000 0 0x100000>;
1984 linux,pci-domain = <0>;
1985 bus-range = <0x00 0xff>;
1991 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1992 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
1997 interrupt-map-mask = <0 0 0 0x7>;
1998 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1999 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2000 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2001 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2018 iommus = <&apps_smmu 0x1c10 0xf>;
2019 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2020 <0x100 &apps_smmu 0x1c11 0x1>,
2021 <0x200 &apps_smmu 0x1c12 0x1>,
2022 <0x300 &apps_smmu 0x1c13 0x1>,
2023 <0x400 &apps_smmu 0x1c14 0x1>,
2024 <0x500 &apps_smmu 0x1c15 0x1>,
2025 <0x600 &apps_smmu 0x1c16 0x1>,
2026 <0x700 &apps_smmu 0x1c17 0x1>,
2027 <0x800 &apps_smmu 0x1c18 0x1>,
2028 <0x900 &apps_smmu 0x1c19 0x1>,
2029 <0xa00 &apps_smmu 0x1c1a 0x1>,
2030 <0xb00 &apps_smmu 0x1c1b 0x1>,
2031 <0xc00 &apps_smmu 0x1c1c 0x1>,
2032 <0xd00 &apps_smmu 0x1c1d 0x1>,
2033 <0xe00 &apps_smmu 0x1c1e 0x1>,
2034 <0xf00 &apps_smmu 0x1c1f 0x1>;
2049 reg = <0 0x01c06000 0 0x18c>;
2068 reg = <0 0x01c06200 0 0x128>,
2069 <0 0x01c06400 0 0x1fc>,
2070 <0 0x01c06800 0 0x218>,
2071 <0 0x01c06600 0 0x70>;
2075 #clock-cells = <0>;
2076 #phy-cells = <0>;
2083 reg = <0 0x01c08000 0 0x2000>,
2084 <0 0x40000000 0 0xf1d>,
2085 <0 0x40000f20 0 0xa8>,
2086 <0 0x40100000 0 0x100000>;
2090 bus-range = <0x00 0xff>;
2096 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2097 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2102 interrupt-map-mask = <0 0 0 0x7>;
2103 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2104 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2105 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2106 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2128 iommus = <&apps_smmu 0x1c00 0xf>;
2129 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2130 <0x100 &apps_smmu 0x1c01 0x1>,
2131 <0x200 &apps_smmu 0x1c02 0x1>,
2132 <0x300 &apps_smmu 0x1c03 0x1>,
2133 <0x400 &apps_smmu 0x1c04 0x1>,
2134 <0x500 &apps_smmu 0x1c05 0x1>,
2135 <0x600 &apps_smmu 0x1c06 0x1>,
2136 <0x700 &apps_smmu 0x1c07 0x1>,
2137 <0x800 &apps_smmu 0x1c08 0x1>,
2138 <0x900 &apps_smmu 0x1c09 0x1>,
2139 <0xa00 &apps_smmu 0x1c0a 0x1>,
2140 <0xb00 &apps_smmu 0x1c0b 0x1>,
2141 <0xc00 &apps_smmu 0x1c0c 0x1>,
2142 <0xd00 &apps_smmu 0x1c0d 0x1>,
2143 <0xe00 &apps_smmu 0x1c0e 0x1>,
2144 <0xf00 &apps_smmu 0x1c0f 0x1>;
2159 reg = <0 0x01c0a000 0 0x800>;
2178 reg = <0 0x01c0a800 0 0x800>,
2179 <0 0x01c0a800 0 0x800>,
2180 <0 0x01c0b800 0 0x400>;
2184 #clock-cells = <0>;
2185 #phy-cells = <0>;
2192 reg = <0 0x01380000 0 0x27200>;
2199 reg = <0 0x014e0000 0 0x400>;
2206 reg = <0 0x01500000 0 0x5080>;
2213 reg = <0 0x01620000 0 0x18080>;
2220 reg = <0 0x016e0000 0 0x15080>;
2227 reg = <0 0x01700000 0 0x1f300>;
2234 reg = <0 0x01740000 0 0x1c100>;
2242 reg = <0 0x01d84000 0 0x2500>,
2243 <0 0x01d90000 0 0x8000>;
2254 iommus = <&apps_smmu 0x100 0xf>;
2278 <0 0>,
2279 <0 0>,
2281 <0 0>,
2282 <0 0>,
2283 <0 0>,
2284 <0 0>,
2285 <0 300000000>;
2292 reg = <0 0x01d87000 0 0x18c>;
2301 resets = <&ufs_mem_hc 0>;
2306 reg = <0 0x01d87400 0 0x108>,
2307 <0 0x01d87600 0 0x1e0>,
2308 <0 0x01d87c00 0 0x1dc>,
2309 <0 0x01d87800 0 0x108>,
2310 <0 0x01d87a00 0 0x1e0>;
2311 #phy-cells = <0>;
2317 reg = <0 0x01dc4000 0 0x24000>;
2322 qcom,ee = <0>;
2324 iommus = <&apps_smmu 0x704 0x1>,
2325 <&apps_smmu 0x706 0x1>,
2326 <&apps_smmu 0x714 0x1>,
2327 <&apps_smmu 0x716 0x1>;
2332 reg = <0 0x01dfa000 0 0x6000>;
2339 iommus = <&apps_smmu 0x704 0x1>,
2340 <&apps_smmu 0x706 0x1>,
2341 <&apps_smmu 0x714 0x1>,
2342 <&apps_smmu 0x716 0x1>;
2348 iommus = <&apps_smmu 0x720 0x0>,
2349 <&apps_smmu 0x722 0x0>;
2350 reg = <0 0x1e40000 0 0x7000>,
2351 <0 0x1e47000 0 0x2000>,
2352 <0 0x1e04000 0 0x2c000>;
2359 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2369 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2370 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2371 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2376 qcom,smem-states = <&ipa_smp2p_out 0>,
2386 reg = <0 0x01f40000 0 0x40000>;
2391 reg = <0 0x03400000 0 0xc00000>;
2397 gpio-ranges = <&tlmm 0 0 151>;
2962 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
2967 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2987 qcom,smem-states = <&modem_smp2p_out 0>;
2994 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
3020 reg = <0 0x05090000 0 0x9000>;
3034 reg = <0 0x06002000 0 0x1000>,
3035 <0 0x16280000 0 0x180000>;
3053 reg = <0 0x06041000 0 0x1000>;
3069 #size-cells = <0>;
3082 reg = <0 0x06043000 0 0x1000>;
3098 #size-cells = <0>;
3112 reg = <0 0x06045000 0 0x1000>;
3127 #size-cells = <0>;
3129 port@0 {
3130 reg = <0>;
3149 reg = <0 0x06046000 0 0x1000>;
3173 reg = <0 0x06047000 0 0x1000>;
3189 #size-cells = <0>;
3203 reg = <0 0x06048000 0 0x1000>;
3221 reg = <0 0x07040000 0 0x1000>;
3241 reg = <0 0x07140000 0 0x1000>;
3261 reg = <0 0x07240000 0 0x1000>;
3281 reg = <0 0x07340000 0 0x1000>;
3301 reg = <0 0x07440000 0 0x1000>;
3321 reg = <0 0x07540000 0 0x1000>;
3341 reg = <0 0x07640000 0 0x1000>;
3361 reg = <0 0x07740000 0 0x1000>;
3381 reg = <0 0x07800000 0 0x1000>;
3397 #size-cells = <0>;
3399 port@0 {
3400 reg = <0>;
3467 reg = <0 0x07810000 0 0x1000>;
3493 reg = <0 0x08804000 0 0x1000>;
3502 iommus = <&apps_smmu 0xa0 0xf>;
3559 reg = <0 0x088df000 0 0x600>;
3561 #size-cells = <0>;
3573 reg = <0 0x171c0000 0 0x2c000>;
3576 qcom,apps-ch-pipes = <0x780000>;
3577 qcom,ea-pc = <0x270>;
3583 iommus = <&apps_smmu 0x1806 0x0>;
3585 #size-cells = <0>;
3590 #size-cells = <0>;
3592 wcd9340_ifd: ifd@0{
3594 reg = <0 0>;
3599 reg = <1 0>;
3608 #clock-cells = <0>;
3623 reg = <0x42 0x2>;
3628 reg = <0xc85 0x40>;
3633 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
3634 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
3635 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
3641 #size-cells = <0>;
3654 reg = <0 0x088e2000 0 0x400>;
3656 #phy-cells = <0>;
3669 reg = <0 0x088e3000 0 0x400>;
3671 #phy-cells = <0>;
3684 reg = <0 0x088e9000 0 0x18c>,
3685 <0 0x088e8000 0 0x10>;
3703 reg = <0 0x088e9200 0 0x128>,
3704 <0 0x088e9400 0 0x200>,
3705 <0 0x088e9c00 0 0x218>,
3706 <0 0x088e9600 0 0x128>,
3707 <0 0x088e9800 0 0x200>,
3708 <0 0x088e9a00 0 0x100>;
3709 #clock-cells = <0>;
3710 #phy-cells = <0>;
3719 reg = <0 0x088eb000 0 0x18c>;
3736 reg = <0 0x088eb200 0 0x128>,
3737 <0 0x088eb400 0 0x1fc>,
3738 <0 0x088eb800 0 0x218>,
3739 <0 0x088eb600 0 0x70>;
3740 #clock-cells = <0>;
3741 #phy-cells = <0>;
3750 reg = <0 0x0a6f8800 0 0x400>;
3780 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
3781 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3786 reg = <0 0x0a600000 0 0xcd00>;
3788 iommus = <&apps_smmu 0x740 0>;
3798 reg = <0 0x0a8f8800 0 0x400>;
3828 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
3829 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3834 reg = <0 0x0a800000 0 0xcd00>;
3836 iommus = <&apps_smmu 0x760 0>;
3846 reg = <0 0x0aa00000 0 0xff000>;
3864 iommus = <&apps_smmu 0x10a0 0x8>,
3865 <&apps_smmu 0x10b0 0x0>;
3867 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
3868 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3916 reg = <0 0x0ab00000 0 0x10000>;
3927 reg = <0 0xacb3000 0 0x1000>,
3928 <0 0xacba000 0 0x1000>,
3929 <0 0xacc8000 0 0x1000>,
3930 <0 0xac65000 0 0x1000>,
3931 <0 0xac66000 0 0x1000>,
3932 <0 0xac67000 0 0x1000>,
3933 <0 0xac68000 0 0x1000>,
3934 <0 0xacaf000 0 0x4000>,
3935 <0 0xacb6000 0 0x4000>,
3936 <0 0xacc4000 0 0x4000>;
4046 iommus = <&apps_smmu 0x0808 0x0>,
4047 <&apps_smmu 0x0810 0x8>,
4048 <&apps_smmu 0x0c08 0x0>,
4049 <&apps_smmu 0x0c10 0x8>;
4055 #size-cells = <0>;
4062 #size-cells = <0>;
4064 reg = <0 0x0ac4a000 0 0x4000>;
4086 pinctrl-0 = <&cci0_default &cci1_default>;
4091 cci_i2c0: i2c-bus@0 {
4092 reg = <0>;
4095 #size-cells = <0>;
4102 #size-cells = <0>;
4108 reg = <0 0x0ad00000 0 0x10000>;
4145 reg = <0 0x0ae00000 0 0x1000>;
4161 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4162 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4165 iommus = <&apps_smmu 0x880 0x8>,
4166 <&apps_smmu 0xc80 0x8>;
4176 reg = <0 0x0ae01000 0 0x8f000>,
4177 <0 0x0aeb0000 0 0x2008>;
4195 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
4201 #size-cells = <0>;
4203 port@0 {
4204 reg = <0>;
4245 reg = <0 0x0ae94000 0 0x400>;
4264 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4276 #size-cells = <0>;
4278 port@0 {
4279 reg = <0>;
4295 reg = <0 0x0ae94400 0 0x200>,
4296 <0 0x0ae94600 0 0x280>,
4297 <0 0x0ae94a00 0 0x1e0>;
4303 #phy-cells = <0>;
4314 reg = <0 0x0ae96000 0 0x400>;
4333 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4345 #size-cells = <0>;
4347 port@0 {
4348 reg = <0>;
4364 reg = <0 0x0ae96400 0 0x200>,
4365 <0 0x0ae96600 0 0x280>,
4366 <0 0x0ae96a00 0 0x10e>;
4372 #phy-cells = <0>;
4386 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4396 iommus = <&adreno_smmu 0>;
4402 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4454 reg = <0 0x5040000 0 0x10000>;
4477 reg = <0 0x506a000 0 0x30000>,
4478 <0 0xb280000 0 0x10000>,
4479 <0 0xb480000 0 0x10000>;
4517 reg = <0 0x0af00000 0 0x10000>;
4521 <&dsi0_phy 0>,
4523 <&dsi1_phy 0>,
4525 <0>,
4526 <0>;
4543 reg = <0 0x0b220000 0 0x30000>;
4544 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4552 reg = <0 0x0b2e0000 0 0x20000>;
4558 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4559 <0 0x0c222000 0 0x1ff>; /* SROT */
4569 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4570 <0 0x0c223000 0 0x1ff>; /* SROT */
4580 reg = <0 0x0c2a0000 0 0x31000>;
4586 reg = <0 0x0c300000 0 0x100000>;
4588 mboxes = <&apss_shared 0>;
4590 #clock-cells = <0>;
4604 reg = <0 0x0c440000 0 0x1100>,
4605 <0 0x0c600000 0 0x2000000>,
4606 <0 0x0e600000 0 0x100000>,
4607 <0 0x0e700000 0 0xa0000>,
4608 <0 0x0c40a000 0 0x26000>;
4612 qcom,ee = <0>;
4613 qcom,channel = <0>;
4615 #size-cells = <0>;
4618 cell-index = <0>;
4623 reg = <0 0x146bf000 0 0x1000>;
4628 ranges = <0 0 0x146bf000 0x1000>;
4632 reg = <0x94c 0xc8>;
4638 reg = <0 0x15000000 0 0x80000>;
4710 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
4718 reg = <0 0x17900000 0 0xd080>;
4725 reg = <0 0x17980000 0 0x1000>;
4727 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4732 reg = <0 0x17990000 0 0x1000>;
4739 reg = <0 0x179c0000 0 0x10000>,
4740 <0 0x179d0000 0 0x10000>,
4741 <0 0x179e0000 0 0x10000>;
4742 reg-names = "drv-0", "drv-1", "drv-2";
4746 qcom,tcs-offset = <0xd00>;
4822 reg = <0 0x17a00000 0 0x10000>, /* GICD */
4823 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
4830 reg = <0 0x17a40000 0 0x20000>;
4838 reg = <0 0x17184000 0 0x2a000>;
4844 iommus = <&apps_smmu 0x1806 0x0>;
4852 reg = <0 0x17c90000 0 0x1000>;
4855 frame-number = <0>;
4858 reg = <0 0x17ca0000 0 0x1000>,
4859 <0 0x17cb0000 0 0x1000>;
4865 reg = <0 0x17cc0000 0 0x1000>;
4872 reg = <0 0x17cd0000 0 0x1000>;
4879 reg = <0 0x17ce0000 0 0x1000>;
4886 reg = <0 0x17cf0000 0 0x1000>;
4893 reg = <0 0x17d00000 0 0x1000>;
4900 reg = <0 0x17d10000 0 0x1000>;
4907 reg = <0 0x17d41000 0 0x1400>;
4917 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
4929 reg = <0 0x18800000 0 0x800000>;
4947 iommus = <&apps_smmu 0x0040 0x1>;
5308 thermal-sensors = <&tsens0 0>;
5393 thermal-sensors = <&tsens1 0>;