Lines Matching +full:phy +full:- +full:qcom +full:- +full:qusb2
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
8 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/soc/qcom,apr.h>
17 interrupt-parent = <&intc>;
19 #address-cells = <2>;
20 #size-cells = <2>;
25 xo_board: xo-board {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <19200000>;
29 clock-output-names = "xo_board";
32 sleep_clk: sleep-clk {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <32764>;
36 clock-output-names = "sleep_clk";
41 #address-cells = <2>;
42 #size-cells = <0>;
46 compatible = "arm,cortex-a53";
48 enable-method = "psci";
49 cpu-idle-states = <&PERF_CPU_SLEEP_0
54 capacity-dmips-mhz = <1126>;
55 #cooling-cells = <2>;
56 next-level-cache = <&L2_1>;
57 L2_1: l2-cache {
59 cache-level = <2>;
65 compatible = "arm,cortex-a53";
67 enable-method = "psci";
68 cpu-idle-states = <&PERF_CPU_SLEEP_0
73 capacity-dmips-mhz = <1126>;
74 #cooling-cells = <2>;
75 next-level-cache = <&L2_1>;
80 compatible = "arm,cortex-a53";
82 enable-method = "psci";
83 cpu-idle-states = <&PERF_CPU_SLEEP_0
88 capacity-dmips-mhz = <1126>;
89 #cooling-cells = <2>;
90 next-level-cache = <&L2_1>;
95 compatible = "arm,cortex-a53";
97 enable-method = "psci";
98 cpu-idle-states = <&PERF_CPU_SLEEP_0
103 capacity-dmips-mhz = <1126>;
104 #cooling-cells = <2>;
105 next-level-cache = <&L2_1>;
110 compatible = "arm,cortex-a53";
112 enable-method = "psci";
113 cpu-idle-states = <&PWR_CPU_SLEEP_0
118 capacity-dmips-mhz = <1024>;
119 #cooling-cells = <2>;
120 next-level-cache = <&L2_0>;
121 L2_0: l2-cache {
123 cache-level = <2>;
129 compatible = "arm,cortex-a53";
131 enable-method = "psci";
132 cpu-idle-states = <&PWR_CPU_SLEEP_0
137 capacity-dmips-mhz = <1024>;
138 #cooling-cells = <2>;
139 next-level-cache = <&L2_0>;
144 compatible = "arm,cortex-a53";
146 enable-method = "psci";
147 cpu-idle-states = <&PWR_CPU_SLEEP_0
152 capacity-dmips-mhz = <1024>;
153 #cooling-cells = <2>;
154 next-level-cache = <&L2_0>;
159 compatible = "arm,cortex-a53";
161 enable-method = "psci";
162 cpu-idle-states = <&PWR_CPU_SLEEP_0
167 capacity-dmips-mhz = <1024>;
168 #cooling-cells = <2>;
169 next-level-cache = <&L2_0>;
172 cpu-map {
210 idle-states {
211 entry-method = "psci";
213 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
214 compatible = "arm,idle-state";
215 idle-state-name = "pwr-retention";
216 arm,psci-suspend-param = <0x40000002>;
217 entry-latency-us = <338>;
218 exit-latency-us = <423>;
219 min-residency-us = <200>;
222 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
223 compatible = "arm,idle-state";
224 idle-state-name = "pwr-power-collapse";
225 arm,psci-suspend-param = <0x40000003>;
226 entry-latency-us = <515>;
227 exit-latency-us = <1821>;
228 min-residency-us = <1000>;
229 local-timer-stop;
232 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
233 compatible = "arm,idle-state";
234 idle-state-name = "perf-retention";
235 arm,psci-suspend-param = <0x40000002>;
236 entry-latency-us = <154>;
237 exit-latency-us = <87>;
238 min-residency-us = <200>;
241 PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
242 compatible = "arm,idle-state";
243 idle-state-name = "perf-power-collapse";
244 arm,psci-suspend-param = <0x40000003>;
245 entry-latency-us = <262>;
246 exit-latency-us = <301>;
247 min-residency-us = <1000>;
248 local-timer-stop;
251 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
252 compatible = "arm,idle-state";
253 idle-state-name = "pwr-cluster-dynamic-retention";
254 arm,psci-suspend-param = <0x400000F2>;
255 entry-latency-us = <284>;
256 exit-latency-us = <384>;
257 min-residency-us = <9987>;
258 local-timer-stop;
261 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
262 compatible = "arm,idle-state";
263 idle-state-name = "pwr-cluster-retention";
264 arm,psci-suspend-param = <0x400000F3>;
265 entry-latency-us = <338>;
266 exit-latency-us = <423>;
267 min-residency-us = <9987>;
268 local-timer-stop;
271 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
272 compatible = "arm,idle-state";
273 idle-state-name = "pwr-cluster-retention";
274 arm,psci-suspend-param = <0x400000F4>;
275 entry-latency-us = <515>;
276 exit-latency-us = <1821>;
277 min-residency-us = <9987>;
278 local-timer-stop;
281 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
282 compatible = "arm,idle-state";
283 idle-state-name = "perf-cluster-dynamic-retention";
284 arm,psci-suspend-param = <0x400000F2>;
285 entry-latency-us = <272>;
286 exit-latency-us = <329>;
287 min-residency-us = <9987>;
288 local-timer-stop;
291 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
292 compatible = "arm,idle-state";
293 idle-state-name = "perf-cluster-retention";
294 arm,psci-suspend-param = <0x400000F3>;
295 entry-latency-us = <332>;
296 exit-latency-us = <368>;
297 min-residency-us = <9987>;
298 local-timer-stop;
301 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
302 compatible = "arm,idle-state";
303 idle-state-name = "perf-cluster-retention";
304 arm,psci-suspend-param = <0x400000F4>;
305 entry-latency-us = <545>;
306 exit-latency-us = <1609>;
307 min-residency-us = <9987>;
308 local-timer-stop;
315 compatible = "qcom,scm-msm8998", "qcom,scm";
326 compatible = "arm,armv8-pmuv3";
331 compatible = "arm,psci-1.0";
335 reserved-memory {
336 #address-cells = <2>;
337 #size-cells = <2>;
340 wlan_msa_guard: wlan-msa-guard@85600000 {
342 no-map;
345 wlan_msa_mem: wlan-msa-mem@85700000 {
347 no-map;
350 qhee_code: qhee-code@85800000 {
352 no-map;
356 compatible = "qcom,rmtfs-mem";
358 no-map;
360 qcom,client-id = <1>;
361 qcom,vmid = <15>;
364 smem_region: smem-mem@86000000 {
366 no-map;
371 no-map;
376 no-map;
381 no-map;
386 no-map;
391 no-map;
396 no-map;
399 adsp_mem: adsp-region@f6000000 {
401 no-map;
404 qseecom_mem: qseecom-region@f6800000 {
406 no-map;
410 compatible = "shared-dma-pool";
412 no-map;
416 rpm-glink {
417 compatible = "qcom,glink-rpm";
420 qcom,rpm-msg-ram = <&rpm_msg_ram>;
423 rpm_requests: rpm-requests {
424 compatible = "qcom,rpm-sdm660";
425 qcom,glink-channels = "rpm_requests";
427 rpmcc: clock-controller {
428 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
429 #clock-cells = <1>;
432 rpmpd: power-controller {
433 compatible = "qcom,sdm660-rpmpd";
434 #power-domain-cells = <1>;
435 operating-points-v2 = <&rpmpd_opp_table>;
437 rpmpd_opp_table: opp-table {
438 compatible = "operating-points-v2";
441 opp-level = <RPM_SMD_LEVEL_RETENTION>;
445 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
449 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
453 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
457 opp-level = <RPM_SMD_LEVEL_SVS>;
461 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
465 opp-level = <RPM_SMD_LEVEL_NOM>;
469 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
473 opp-level = <RPM_SMD_LEVEL_TURBO>;
481 compatible = "qcom,smem";
482 memory-region = <&smem_region>;
486 smp2p-adsp {
487 compatible = "qcom,smp2p";
488 qcom,smem = <443>, <429>;
491 qcom,local-pid = <0>;
492 qcom,remote-pid = <2>;
494 adsp_smp2p_out: master-kernel {
495 qcom,entry-name = "master-kernel";
496 #qcom,smem-state-cells = <1>;
499 adsp_smp2p_in: slave-kernel {
500 qcom,entry-name = "slave-kernel";
501 interrupt-controller;
502 #interrupt-cells = <2>;
506 smp2p-mpss {
507 compatible = "qcom,smp2p";
508 qcom,smem = <435>, <428>;
511 qcom,local-pid = <0>;
512 qcom,remote-pid = <1>;
514 modem_smp2p_out: master-kernel {
515 qcom,entry-name = "master-kernel";
516 #qcom,smem-state-cells = <1>;
519 modem_smp2p_in: slave-kernel {
520 qcom,entry-name = "slave-kernel";
521 interrupt-controller;
522 #interrupt-cells = <2>;
527 #address-cells = <1>;
528 #size-cells = <1>;
530 compatible = "simple-bus";
532 gcc: clock-controller@100000 {
533 compatible = "qcom,gcc-sdm630";
534 #clock-cells = <1>;
535 #reset-cells = <1>;
536 #power-domain-cells = <1>;
539 clock-names = "xo", "sleep_clk";
545 compatible = "qcom,rpm-msg-ram";
550 compatible = "qcom,qfprom";
552 #address-cells = <1>;
553 #size-cells = <1>;
555 qusb2_hstx_trim: hstx-trim@240 {
560 gpu_speed_bin: gpu-speed-bin@41a0 {
567 compatible = "qcom,prng-ee";
570 clock-names = "core";
574 compatible = "qcom,sdm660-bimc";
576 #interconnect-cells = <1>;
577 clock-names = "bus", "bus_a";
583 compatible = "qcom,pshold";
588 compatible = "qcom,sdm660-cnoc";
590 #interconnect-cells = <1>;
591 clock-names = "bus", "bus_a";
597 compatible = "qcom,sdm660-snoc";
599 #interconnect-cells = <1>;
600 clock-names = "bus", "bus_a";
606 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
609 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
610 assigned-clock-rates = <1000>;
612 clock-names = "bus";
613 #global-interrupts = <2>;
614 #iommu-cells = <1>;
654 compatible = "qcom,sdm660-a2noc";
656 #interconnect-cells = <1>;
657 clock-names = "bus",
674 compatible = "qcom,sdm660-mnoc";
676 #interconnect-cells = <1>;
677 clock-names = "bus", "bus_a", "iface";
683 tsens: thermal-sensor@10ae000 {
684 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2";
687 #qcom,sensors = <12>;
690 interrupt-names = "uplow", "critical";
691 #thermal-sensor-cells = <1>;
700 compatible = "qcom,sdm630-pinctrl";
704 reg-names = "south", "center", "north";
706 gpio-controller;
707 gpio-ranges = <&tlmm 0 0 114>;
708 #gpio-cells = <2>;
709 interrupt-controller;
710 #interrupt-cells = <2>;
712 blsp1_uart1_default: blsp1-uart1-default {
714 drive-strength = <2>;
715 bias-disable;
718 blsp1_uart1_sleep: blsp1-uart1-sleep {
720 drive-strength = <2>;
721 bias-disable;
724 blsp1_uart2_default: blsp1-uart2-default {
726 drive-strength = <2>;
727 bias-disable;
730 blsp2_uart1_default: blsp2-uart1-active {
731 tx-rts {
734 drive-strength = <2>;
735 bias-disable;
745 drive-strength = <2>;
746 bias-pull-up;
753 drive-strength = <2>;
754 bias-pull-down;
758 blsp2_uart1_sleep: blsp2-uart1-sleep {
762 drive-strength = <2>;
763 bias-pull-up;
766 rx-cts-rts {
769 drive-strength = <2>;
770 bias-no-pull;
774 i2c1_default: i2c1-default {
777 drive-strength = <2>;
778 bias-disable;
781 i2c1_sleep: i2c1-sleep {
784 drive-strength = <2>;
785 bias-pull-up;
788 i2c2_default: i2c2-default {
791 drive-strength = <2>;
792 bias-disable;
795 i2c2_sleep: i2c2-sleep {
798 drive-strength = <2>;
799 bias-pull-up;
802 i2c3_default: i2c3-default {
805 drive-strength = <2>;
806 bias-disable;
809 i2c3_sleep: i2c3-sleep {
812 drive-strength = <2>;
813 bias-pull-up;
816 i2c4_default: i2c4-default {
819 drive-strength = <2>;
820 bias-disable;
823 i2c4_sleep: i2c4-sleep {
826 drive-strength = <2>;
827 bias-pull-up;
830 i2c5_default: i2c5-default {
833 drive-strength = <2>;
834 bias-disable;
837 i2c5_sleep: i2c5-sleep {
840 drive-strength = <2>;
841 bias-pull-up;
844 i2c6_default: i2c6-default {
847 drive-strength = <2>;
848 bias-disable;
851 i2c6_sleep: i2c6-sleep {
854 drive-strength = <2>;
855 bias-pull-up;
858 i2c7_default: i2c7-default {
861 drive-strength = <2>;
862 bias-disable;
865 i2c7_sleep: i2c7-sleep {
868 drive-strength = <2>;
869 bias-pull-up;
872 i2c8_default: i2c8-default {
875 drive-strength = <2>;
876 bias-disable;
879 i2c8_sleep: i2c8-sleep {
882 drive-strength = <2>;
883 bias-pull-up;
894 bias-pull-up;
895 drive-strength = <2>;
907 bias-pull-up;
908 drive-strength = <2>;
912 sdc1_state_on: sdc1-on {
915 bias-disable;
916 drive-strength = <16>;
921 bias-pull-up;
922 drive-strength = <10>;
927 bias-pull-up;
928 drive-strength = <10>;
933 bias-pull-down;
937 sdc1_state_off: sdc1-off {
940 bias-disable;
941 drive-strength = <2>;
946 bias-pull-up;
947 drive-strength = <2>;
952 bias-pull-up;
953 drive-strength = <2>;
958 bias-pull-down;
962 sdc2_state_on: sdc2-on {
965 bias-disable;
966 drive-strength = <16>;
971 bias-pull-up;
972 drive-strength = <10>;
977 bias-pull-up;
978 drive-strength = <10>;
981 sd-cd {
983 bias-pull-up;
984 drive-strength = <2>;
988 sdc2_state_off: sdc2-off {
991 bias-disable;
992 drive-strength = <2>;
997 bias-pull-up;
998 drive-strength = <2>;
1003 bias-pull-up;
1004 drive-strength = <2>;
1007 sd-cd {
1009 bias-disable;
1010 drive-strength = <2>;
1016 compatible = "qcom,adreno-508.0", "qcom,adreno";
1017 #stream-id-cells = <16>;
1020 reg-names = "kgsl_3d0_reg_memory";
1031 clock-names = "iface",
1038 power-domains = <&rpmpd SDM660_VDDMX>;
1041 nvmem-cells = <&gpu_speed_bin>;
1042 nvmem-cell-names = "speed_bin";
1045 interconnect-names = "gfx-mem";
1047 operating-points-v2 = <&gpu_sdm630_opp_table>;
1049 gpu_sdm630_opp_table: opp-table {
1050 compatible = "operating-points-v2";
1051 opp-775000000 {
1052 opp-hz = /bits/ 64 <775000000>;
1053 opp-level = <RPM_SMD_LEVEL_TURBO>;
1054 opp-peak-kBps = <5412000>;
1055 opp-supported-hw = <0xA2>;
1057 opp-647000000 {
1058 opp-hz = /bits/ 64 <647000000>;
1059 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1060 opp-peak-kBps = <4068000>;
1061 opp-supported-hw = <0xFF>;
1063 opp-588000000 {
1064 opp-hz = /bits/ 64 <588000000>;
1065 opp-level = <RPM_SMD_LEVEL_NOM>;
1066 opp-peak-kBps = <3072000>;
1067 opp-supported-hw = <0xFF>;
1069 opp-465000000 {
1070 opp-hz = /bits/ 64 <465000000>;
1071 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1072 opp-peak-kBps = <2724000>;
1073 opp-supported-hw = <0xFF>;
1075 opp-370000000 {
1076 opp-hz = /bits/ 64 <370000000>;
1077 opp-level = <RPM_SMD_LEVEL_SVS>;
1078 opp-peak-kBps = <2188000>;
1079 opp-supported-hw = <0xFF>;
1081 opp-240000000 {
1082 opp-hz = /bits/ 64 <240000000>;
1083 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1084 opp-peak-kBps = <1648000>;
1085 opp-supported-hw = <0xFF>;
1087 opp-160000000 {
1088 opp-hz = /bits/ 64 <160000000>;
1089 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1090 opp-peak-kBps = <1200000>;
1091 opp-supported-hw = <0xFF>;
1097 compatible = "qcom,sdm630-smmu-v2",
1098 "qcom,adreno-smmu", "qcom,smmu-v2";
1108 power-domains = <&gpucc GPU_GX_GDSC>;
1112 clock-names = "iface", "mem", "mem_iface";
1113 #global-interrupts = <2>;
1114 #iommu-cells = <1>;
1132 gpucc: clock-controller@5065000 {
1133 compatible = "qcom,gpucc-sdm630";
1134 #clock-cells = <1>;
1135 #reset-cells = <1>;
1136 #power-domain-cells = <1>;
1142 clock-names = "xo",
1149 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1151 #iommu-cells = <1>;
1153 #global-interrupts = <2>;
1180 compatible = "qcom,spmi-pmic-arb";
1186 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1187 interrupt-names = "periph_irq";
1189 qcom,ee = <0>;
1190 qcom,channel = <0>;
1191 #address-cells = <2>;
1192 #size-cells = <0>;
1193 interrupt-controller;
1194 #interrupt-cells = <4>;
1195 cell-index = <0>;
1199 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1202 #address-cells = <1>;
1203 #size-cells = <1>;
1212 clock-names = "cfg_noc", "core", "iface", "bus",
1215 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1218 assigned-clock-rates = <19200000>, <120000000>,
1223 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1225 power-domains = <&gcc USB_30_GDSC>;
1226 qcom,select-utmi-as-pipe-clk;
1241 maximum-speed = "high-speed";
1243 phy-names = "usb2-phy";
1244 snps,hird-threshold = /bits/ 8 <0>;
1248 qusb2phy: phy@c012000 {
1249 compatible = "qcom,sdm660-qusb2-phy";
1251 #phy-cells = <0>;
1255 clock-names = "cfg_ahb", "ref";
1258 nvmem-cells = <&qusb2_hstx_trim>;
1263 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1265 reg-names = "hc";
1269 interrupt-names = "hc_irq", "pwr_irq";
1271 bus-width = <4>;
1275 clock-names = "core", "iface", "xo";
1279 operating-points-v2 = <&sdhc2_opp_table>;
1281 pinctrl-names = "default", "sleep";
1282 pinctrl-0 = <&sdc2_state_on>;
1283 pinctrl-1 = <&sdc2_state_off>;
1284 power-domains = <&rpmpd SDM660_VDDCX>;
1288 sdhc2_opp_table: opp-table {
1289 compatible = "operating-points-v2";
1291 opp-50000000 {
1292 opp-hz = /bits/ 64 <50000000>;
1293 required-opps = <&rpmpd_opp_low_svs>;
1294 opp-peak-kBps = <200000 140000>;
1295 opp-avg-kBps = <130718 133320>;
1297 opp-100000000 {
1298 opp-hz = /bits/ 64 <100000000>;
1299 required-opps = <&rpmpd_opp_svs>;
1300 opp-peak-kBps = <250000 160000>;
1301 opp-avg-kBps = <196078 150000>;
1303 opp-200000000 {
1304 opp-hz = /bits/ 64 <200000000>;
1305 required-opps = <&rpmpd_opp_nom>;
1306 opp-peak-kBps = <4096000 4096000>;
1307 opp-avg-kBps = <1338562 1338562>;
1313 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1317 reg-names = "hc", "cqhci", "ice";
1321 interrupt-names = "hc_irq", "pwr_irq";
1327 clock-names = "core", "iface", "xo", "ice";
1331 interconnect-names = "sdhc1-ddr", "cpu-sdhc1";
1332 operating-points-v2 = <&sdhc1_opp_table>;
1333 pinctrl-names = "default", "sleep";
1334 pinctrl-0 = <&sdc1_state_on>;
1335 pinctrl-1 = <&sdc1_state_off>;
1336 power-domains = <&rpmpd SDM660_VDDCX>;
1338 bus-width = <8>;
1339 non-removable;
1343 sdhc1_opp_table: opp-table {
1344 compatible = "operating-points-v2";
1346 opp-50000000 {
1347 opp-hz = /bits/ 64 <50000000>;
1348 required-opps = <&rpmpd_opp_low_svs>;
1349 opp-peak-kBps = <200000 140000>;
1350 opp-avg-kBps = <130718 133320>;
1352 opp-100000000 {
1353 opp-hz = /bits/ 64 <100000000>;
1354 required-opps = <&rpmpd_opp_svs>;
1355 opp-peak-kBps = <250000 160000>;
1356 opp-avg-kBps = <196078 150000>;
1358 opp-384000000 {
1359 opp-hz = /bits/ 64 <384000000>;
1360 required-opps = <&rpmpd_opp_nom>;
1361 opp-peak-kBps = <4096000 4096000>;
1362 opp-avg-kBps = <1338562 1338562>;
1367 mmcc: clock-controller@c8c0000 {
1368 compatible = "qcom,mmcc-sdm630";
1370 #clock-cells = <1>;
1371 #reset-cells = <1>;
1372 #power-domain-cells = <1>;
1373 clock-names = "xo",
1395 dsi_opp_table: dsi-opp-table {
1396 compatible = "operating-points-v2";
1398 opp-131250000 {
1399 opp-hz = /bits/ 64 <131250000>;
1400 required-opps = <&rpmpd_opp_svs>;
1403 opp-210000000 {
1404 opp-hz = /bits/ 64 <210000000>;
1405 required-opps = <&rpmpd_opp_svs_plus>;
1408 opp-262500000 {
1409 opp-hz = /bits/ 64 <262500000>;
1410 required-opps = <&rpmpd_opp_nom>;
1415 compatible = "qcom,mdss";
1418 reg-names = "mdss_phys", "vbif_phys";
1420 power-domains = <&mmcc MDSS_GDSC>;
1426 clock-names = "iface",
1433 interrupt-controller;
1434 #interrupt-cells = <1>;
1436 #address-cells = <1>;
1437 #size-cells = <1>;
1442 compatible = "qcom,mdp5";
1444 reg-names = "mdp_phys";
1446 interrupt-parent = <&mdss>;
1449 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1451 assigned-clock-rates = <300000000>,
1457 clock-names = "iface",
1465 interconnect-names = "mdp0-mem",
1466 "mdp1-mem",
1467 "rotator-mem";
1469 operating-points-v2 = <&mdp_opp_table>;
1470 power-domains = <&rpmpd SDM660_VDDCX>;
1473 #address-cells = <1>;
1474 #size-cells = <0>;
1479 remote-endpoint = <&dsi0_in>;
1484 mdp_opp_table: mdp-opp {
1485 compatible = "operating-points-v2";
1487 opp-150000000 {
1488 opp-hz = /bits/ 64 <150000000>;
1489 opp-peak-kBps = <320000 320000 76800>;
1490 required-opps = <&rpmpd_opp_low_svs>;
1492 opp-275000000 {
1493 opp-hz = /bits/ 64 <275000000>;
1494 opp-peak-kBps = <6400000 6400000 160000>;
1495 required-opps = <&rpmpd_opp_svs>;
1497 opp-300000000 {
1498 opp-hz = /bits/ 64 <300000000>;
1499 opp-peak-kBps = <6400000 6400000 190000>;
1500 required-opps = <&rpmpd_opp_svs_plus>;
1502 opp-330000000 {
1503 opp-hz = /bits/ 64 <330000000>;
1504 opp-peak-kBps = <6400000 6400000 240000>;
1505 required-opps = <&rpmpd_opp_nom>;
1507 opp-412500000 {
1508 opp-hz = /bits/ 64 <412500000>;
1509 opp-peak-kBps = <6400000 6400000 320000>;
1510 required-opps = <&rpmpd_opp_turbo>;
1516 compatible = "qcom,mdss-dsi-ctrl";
1518 reg-names = "dsi_ctrl";
1520 operating-points-v2 = <&dsi_opp_table>;
1521 power-domains = <&rpmpd SDM660_VDDCX>;
1523 interrupt-parent = <&mdss>;
1526 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1528 assigned-clock-parents = <&dsi0_phy 0>,
1540 clock-names = "mdp_core",
1551 phy-names = "dsi";
1554 #address-cells = <1>;
1555 #size-cells = <0>;
1560 remote-endpoint = <&mdp5_intf1_out>;
1572 dsi0_phy: dsi-phy@c994400 {
1573 compatible = "qcom,dsi-phy-14nm-660";
1577 reg-names = "dsi_phy",
1581 #clock-cells = <1>;
1582 #phy-cells = <0>;
1585 clock-names = "iface", "ref";
1589 blsp1_dma: dma-controller@c144000 {
1590 compatible = "qcom,bam-v1.7.0";
1594 clock-names = "bam_clk";
1595 #dma-cells = <1>;
1596 qcom,ee = <0>;
1597 qcom,controlled-remotely;
1598 num-channels = <18>;
1599 qcom,num-ees = <4>;
1603 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1608 clock-names = "core", "iface";
1610 dma-names = "tx", "rx";
1611 pinctrl-names = "default", "sleep";
1612 pinctrl-0 = <&blsp1_uart1_default>;
1613 pinctrl-1 = <&blsp1_uart1_sleep>;
1618 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1623 clock-names = "core", "iface";
1625 dma-names = "tx", "rx";
1626 pinctrl-names = "default";
1627 pinctrl-0 = <&blsp1_uart2_default>;
1632 compatible = "qcom,i2c-qup-v2.2.1";
1638 clock-names = "core", "iface";
1639 clock-frequency = <400000>;
1641 dma-names = "tx", "rx";
1643 pinctrl-names = "default", "sleep";
1644 pinctrl-0 = <&i2c1_default>;
1645 pinctrl-1 = <&i2c1_sleep>;
1646 #address-cells = <1>;
1647 #size-cells = <0>;
1652 compatible = "qcom,i2c-qup-v2.2.1";
1658 clock-names = "core", "iface";
1659 clock-frequency = <400000>;
1661 dma-names = "tx", "rx";
1663 pinctrl-names = "default", "sleep";
1664 pinctrl-0 = <&i2c2_default>;
1665 pinctrl-1 = <&i2c2_sleep>;
1666 #address-cells = <1>;
1667 #size-cells = <0>;
1672 compatible = "qcom,i2c-qup-v2.2.1";
1678 clock-names = "core", "iface";
1679 clock-frequency = <400000>;
1681 dma-names = "tx", "rx";
1683 pinctrl-names = "default", "sleep";
1684 pinctrl-0 = <&i2c3_default>;
1685 pinctrl-1 = <&i2c3_sleep>;
1686 #address-cells = <1>;
1687 #size-cells = <0>;
1692 compatible = "qcom,i2c-qup-v2.2.1";
1698 clock-names = "core", "iface";
1699 clock-frequency = <400000>;
1701 dma-names = "tx", "rx";
1703 pinctrl-names = "default", "sleep";
1704 pinctrl-0 = <&i2c4_default>;
1705 pinctrl-1 = <&i2c4_sleep>;
1706 #address-cells = <1>;
1707 #size-cells = <0>;
1711 blsp2_dma: dma-controller@c184000 {
1712 compatible = "qcom,bam-v1.7.0";
1716 clock-names = "bam_clk";
1717 #dma-cells = <1>;
1718 qcom,ee = <0>;
1719 qcom,controlled-remotely;
1720 num-channels = <18>;
1721 qcom,num-ees = <4>;
1725 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1730 clock-names = "core", "iface";
1732 dma-names = "tx", "rx";
1733 pinctrl-names = "default", "sleep";
1734 pinctrl-0 = <&blsp2_uart1_default>;
1735 pinctrl-1 = <&blsp2_uart1_sleep>;
1740 compatible = "qcom,i2c-qup-v2.2.1";
1746 clock-names = "core", "iface";
1747 clock-frequency = <400000>;
1749 dma-names = "tx", "rx";
1751 pinctrl-names = "default", "sleep";
1752 pinctrl-0 = <&i2c5_default>;
1753 pinctrl-1 = <&i2c5_sleep>;
1754 #address-cells = <1>;
1755 #size-cells = <0>;
1760 compatible = "qcom,i2c-qup-v2.2.1";
1766 clock-names = "core", "iface";
1767 clock-frequency = <400000>;
1769 dma-names = "tx", "rx";
1771 pinctrl-names = "default", "sleep";
1772 pinctrl-0 = <&i2c6_default>;
1773 pinctrl-1 = <&i2c6_sleep>;
1774 #address-cells = <1>;
1775 #size-cells = <0>;
1780 compatible = "qcom,i2c-qup-v2.2.1";
1786 clock-names = "core", "iface";
1787 clock-frequency = <400000>;
1789 dma-names = "tx", "rx";
1791 pinctrl-names = "default", "sleep";
1792 pinctrl-0 = <&i2c7_default>;
1793 pinctrl-1 = <&i2c7_sleep>;
1794 #address-cells = <1>;
1795 #size-cells = <0>;
1800 compatible = "qcom,i2c-qup-v2.2.1";
1806 clock-names = "core", "iface";
1807 clock-frequency = <400000>;
1809 dma-names = "tx", "rx";
1811 pinctrl-names = "default", "sleep";
1812 pinctrl-0 = <&i2c8_default>;
1813 pinctrl-1 = <&i2c8_sleep>;
1814 #address-cells = <1>;
1815 #size-cells = <0>;
1820 compatible = "simple-mfd";
1823 #address-cells = <1>;
1824 #size-cells = <1>;
1828 pil-reloc@94c {
1829 compatible = "qcom,pil-reloc-info";
1835 compatible = "qcom,sdm660-camss";
1850 reg-names = "csiphy0",
1874 interrupt-names = "csiphy0",
1926 clock-names = "top_ahb",
1969 interconnect-names = "vfe-mem";
1974 power-domains = <&mmcc CAMSS_VFE0_GDSC>,
1979 #address-cells = <1>;
1980 #size-cells = <0>;
1985 compatible = "qcom,msm8996-cci";
1986 #address-cells = <1>;
1987 #size-cells = <0>;
1991 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1993 assigned-clock-rates = <80800000>, <37500000>;
1998 clock-names = "camss_top_ahb",
2003 pinctrl-names = "default";
2004 pinctrl-0 = <&cci0_default &cci1_default>;
2005 power-domains = <&mmcc CAMSS_TOP_GDSC>;
2008 cci_i2c0: i2c-bus@0 {
2010 clock-frequency = <400000>;
2011 #address-cells = <1>;
2012 #size-cells = <0>;
2015 cci_i2c1: i2c-bus@1 {
2017 clock-frequency = <400000>;
2018 #address-cells = <1>;
2019 #size-cells = <0>;
2024 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
2031 clock-names = "iface-mm", "iface-smmu",
2032 "bus-mm", "bus-smmu";
2033 #global-interrupts = <2>;
2034 #iommu-cells = <1>;
2069 compatible = "qcom,sdm660-adsp-pas";
2072 interrupts-extended =
2078 interrupt-names = "wdog", "fatal", "ready",
2079 "handover", "stop-ack";
2082 clock-names = "xo";
2084 memory-region = <&adsp_region>;
2085 power-domains = <&rpmpd SDM660_VDDCX>;
2086 power-domain-names = "cx";
2088 qcom,smem-states = <&adsp_smp2p_out 0>;
2089 qcom,smem-state-names = "stop";
2091 glink-edge {
2096 qcom,remote-pid = <2>;
2097 #address-cells = <1>;
2098 #size-cells = <0>;
2101 compatible = "qcom,apr-v2";
2102 qcom,glink-channels = "apr_audio_svc";
2103 qcom,apr-domain = <APR_DOMAIN_ADSP>;
2104 #address-cells = <1>;
2105 #size-cells = <0>;
2109 compatible = "qcom,q6core";
2112 q6afe: apr-service@4 {
2113 compatible = "qcom,q6afe";
2116 compatible = "qcom,q6afe-dais";
2117 #address-cells = <1>;
2118 #size-cells = <0>;
2119 #sound-dai-cells = <1>;
2123 q6asm: apr-service@7 {
2124 compatible = "qcom,q6asm";
2127 compatible = "qcom,q6asm-dais";
2128 #address-cells = <1>;
2129 #size-cells = <0>;
2130 #sound-dai-cells = <1>;
2135 q6adm: apr-service@8 {
2136 compatible = "qcom,q6adm";
2139 compatible = "qcom,q6adm-routing";
2140 #sound-dai-cells = <0>;
2148 compatible = "qcom,sdm660-gnoc";
2150 #interconnect-cells = <1>;
2155 clock-names = "bus", "bus_a";
2160 compatible = "qcom,sdm660-apcs-hmss-global";
2163 #mbox-cells = <1>;
2167 #address-cells = <1>;
2168 #size-cells = <1>;
2170 compatible = "arm,armv7-timer-mem";
2172 clock-frequency = <19200000>;
2175 frame-number = <0>;
2183 frame-number = <1>;
2190 frame-number = <2>;
2197 frame-number = <3>;
2204 frame-number = <4>;
2211 frame-number = <5>;
2218 frame-number = <6>;
2225 intc: interrupt-controller@17a00000 {
2226 compatible = "arm,gic-v3";
2229 #interrupt-cells = <3>;
2230 #address-cells = <1>;
2231 #size-cells = <1>;
2233 interrupt-controller;
2234 #redistributor-regions = <1>;
2235 redistributor-stride = <0x0 0x20000>;
2241 compatible = "qcom,tcsr-mutex";
2243 #hwlock-cells = <1>;
2249 thermal-zones {
2250 aoss-thermal {
2251 polling-delay-passive = <250>;
2252 polling-delay = <1000>;
2254 thermal-sensors = <&tsens 0>;
2257 aoss_alert0: trip-point0 {
2265 cpuss0-thermal {
2266 polling-delay-passive = <250>;
2267 polling-delay = <1000>;
2269 thermal-sensors = <&tsens 1>;
2272 cpuss0_alert0: trip-point0 {
2280 cpuss1-thermal {
2281 polling-delay-passive = <250>;
2282 polling-delay = <1000>;
2284 thermal-sensors = <&tsens 2>;
2287 cpuss1_alert0: trip-point0 {
2295 cpu0-thermal {
2296 polling-delay-passive = <250>;
2297 polling-delay = <1000>;
2299 thermal-sensors = <&tsens 3>;
2302 cpu0_alert0: trip-point0 {
2316 cpu1-thermal {
2317 polling-delay-passive = <250>;
2318 polling-delay = <1000>;
2320 thermal-sensors = <&tsens 4>;
2323 cpu1_alert0: trip-point0 {
2337 cpu2-thermal {
2338 polling-delay-passive = <250>;
2339 polling-delay = <1000>;
2341 thermal-sensors = <&tsens 5>;
2344 cpu2_alert0: trip-point0 {
2358 cpu3-thermal {
2359 polling-delay-passive = <250>;
2360 polling-delay = <1000>;
2362 thermal-sensors = <&tsens 6>;
2365 cpu3_alert0: trip-point0 {
2385 pwr-cluster-thermal {
2386 polling-delay-passive = <250>;
2387 polling-delay = <1000>;
2389 thermal-sensors = <&tsens 7>;
2392 pwr_cluster_alert0: trip-point0 {
2406 gpu-thermal {
2407 polling-delay-passive = <250>;
2408 polling-delay = <1000>;
2410 thermal-sensors = <&tsens 8>;
2413 gpu_alert0: trip-point0 {
2423 compatible = "arm,armv8-timer";