Lines Matching +full:qcom +full:- +full:ipcc
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/interconnect/qcom,sc7280.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/mailbox/qcom-ipcc.h>
13 #include <dt-bindings/power/qcom-aoss-qmp.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
16 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
17 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
18 #include <dt-bindings/thermal/thermal.h>
21 interrupt-parent = <&intc>;
23 #address-cells = <2>;
24 #size-cells = <2>;
34 xo_board: xo-board {
35 compatible = "fixed-clock";
36 clock-frequency = <76800000>;
37 #clock-cells = <0>;
40 sleep_clk: sleep-clk {
41 compatible = "fixed-clock";
42 clock-frequency = <32000>;
43 #clock-cells = <0>;
47 reserved-memory {
48 #address-cells = <2>;
49 #size-cells = <2>;
54 no-map;
59 compatible = "qcom,cmd-db";
60 no-map;
65 no-map;
69 no-map;
75 no-map;
80 #address-cells = <2>;
81 #size-cells = <0>;
87 enable-method = "psci";
88 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
91 next-level-cache = <&L2_0>;
92 qcom,freq-domain = <&cpufreq_hw 0>;
93 #cooling-cells = <2>;
94 L2_0: l2-cache {
96 next-level-cache = <&L3_0>;
97 L3_0: l3-cache {
107 enable-method = "psci";
108 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
111 next-level-cache = <&L2_100>;
112 qcom,freq-domain = <&cpufreq_hw 0>;
113 #cooling-cells = <2>;
114 L2_100: l2-cache {
116 next-level-cache = <&L3_0>;
124 enable-method = "psci";
125 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
128 next-level-cache = <&L2_200>;
129 qcom,freq-domain = <&cpufreq_hw 0>;
130 #cooling-cells = <2>;
131 L2_200: l2-cache {
133 next-level-cache = <&L3_0>;
141 enable-method = "psci";
142 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
145 next-level-cache = <&L2_300>;
146 qcom,freq-domain = <&cpufreq_hw 0>;
147 #cooling-cells = <2>;
148 L2_300: l2-cache {
150 next-level-cache = <&L3_0>;
158 enable-method = "psci";
159 cpu-idle-states = <&BIG_CPU_SLEEP_0
162 next-level-cache = <&L2_400>;
163 qcom,freq-domain = <&cpufreq_hw 1>;
164 #cooling-cells = <2>;
165 L2_400: l2-cache {
167 next-level-cache = <&L3_0>;
175 enable-method = "psci";
176 cpu-idle-states = <&BIG_CPU_SLEEP_0
179 next-level-cache = <&L2_500>;
180 qcom,freq-domain = <&cpufreq_hw 1>;
181 #cooling-cells = <2>;
182 L2_500: l2-cache {
184 next-level-cache = <&L3_0>;
192 enable-method = "psci";
193 cpu-idle-states = <&BIG_CPU_SLEEP_0
196 next-level-cache = <&L2_600>;
197 qcom,freq-domain = <&cpufreq_hw 1>;
198 #cooling-cells = <2>;
199 L2_600: l2-cache {
201 next-level-cache = <&L3_0>;
209 enable-method = "psci";
210 cpu-idle-states = <&BIG_CPU_SLEEP_0
213 next-level-cache = <&L2_700>;
214 qcom,freq-domain = <&cpufreq_hw 2>;
215 #cooling-cells = <2>;
216 L2_700: l2-cache {
218 next-level-cache = <&L3_0>;
222 idle-states {
223 entry-method = "psci";
225 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
226 compatible = "arm,idle-state";
227 idle-state-name = "little-power-down";
228 arm,psci-suspend-param = <0x40000003>;
229 entry-latency-us = <549>;
230 exit-latency-us = <901>;
231 min-residency-us = <1774>;
232 local-timer-stop;
235 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
236 compatible = "arm,idle-state";
237 idle-state-name = "little-rail-power-down";
238 arm,psci-suspend-param = <0x40000004>;
239 entry-latency-us = <702>;
240 exit-latency-us = <915>;
241 min-residency-us = <4001>;
242 local-timer-stop;
245 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
246 compatible = "arm,idle-state";
247 idle-state-name = "big-power-down";
248 arm,psci-suspend-param = <0x40000003>;
249 entry-latency-us = <523>;
250 exit-latency-us = <1244>;
251 min-residency-us = <2207>;
252 local-timer-stop;
255 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
256 compatible = "arm,idle-state";
257 idle-state-name = "big-rail-power-down";
258 arm,psci-suspend-param = <0x40000004>;
259 entry-latency-us = <526>;
260 exit-latency-us = <1854>;
261 min-residency-us = <5555>;
262 local-timer-stop;
265 CLUSTER_SLEEP_0: cluster-sleep-0 {
266 compatible = "arm,idle-state";
267 idle-state-name = "cluster-power-down";
268 arm,psci-suspend-param = <0x40003444>;
269 entry-latency-us = <3263>;
270 exit-latency-us = <6562>;
271 min-residency-us = <9926>;
272 local-timer-stop;
285 compatible = "qcom,scm-sc7280", "qcom,scm";
290 compatible = "qcom,sc7280-clk-virt";
291 #interconnect-cells = <2>;
292 qcom,bcm-voters = <&apps_bcm_voter>;
296 compatible = "qcom,smem";
297 memory-region = <&smem_mem>;
301 smp2p-adsp {
302 compatible = "qcom,smp2p";
303 qcom,smem = <443>, <429>;
304 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
307 mboxes = <&ipcc IPCC_CLIENT_LPASS
310 qcom,local-pid = <0>;
311 qcom,remote-pid = <2>;
313 adsp_smp2p_out: master-kernel {
314 qcom,entry-name = "master-kernel";
315 #qcom,smem-state-cells = <1>;
318 adsp_smp2p_in: slave-kernel {
319 qcom,entry-name = "slave-kernel";
320 interrupt-controller;
321 #interrupt-cells = <2>;
325 smp2p-cdsp {
326 compatible = "qcom,smp2p";
327 qcom,smem = <94>, <432>;
328 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
331 mboxes = <&ipcc IPCC_CLIENT_CDSP
334 qcom,local-pid = <0>;
335 qcom,remote-pid = <5>;
337 cdsp_smp2p_out: master-kernel {
338 qcom,entry-name = "master-kernel";
339 #qcom,smem-state-cells = <1>;
342 cdsp_smp2p_in: slave-kernel {
343 qcom,entry-name = "slave-kernel";
344 interrupt-controller;
345 #interrupt-cells = <2>;
349 smp2p-mpss {
350 compatible = "qcom,smp2p";
351 qcom,smem = <435>, <428>;
352 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
355 mboxes = <&ipcc IPCC_CLIENT_MPSS
358 qcom,local-pid = <0>;
359 qcom,remote-pid = <1>;
361 modem_smp2p_out: master-kernel {
362 qcom,entry-name = "master-kernel";
363 #qcom,smem-state-cells = <1>;
366 modem_smp2p_in: slave-kernel {
367 qcom,entry-name = "slave-kernel";
368 interrupt-controller;
369 #interrupt-cells = <2>;
372 ipa_smp2p_out: ipa-ap-to-modem {
373 qcom,entry-name = "ipa";
374 #qcom,smem-state-cells = <1>;
377 ipa_smp2p_in: ipa-modem-to-ap {
378 qcom,entry-name = "ipa";
379 interrupt-controller;
380 #interrupt-cells = <2>;
384 smp2p-wpss {
385 compatible = "qcom,smp2p";
386 qcom,smem = <617>, <616>;
387 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
390 mboxes = <&ipcc IPCC_CLIENT_WPSS
393 qcom,local-pid = <0>;
394 qcom,remote-pid = <13>;
396 wpss_smp2p_out: master-kernel {
397 qcom,entry-name = "master-kernel";
398 #qcom,smem-state-cells = <1>;
401 wpss_smp2p_in: slave-kernel {
402 qcom,entry-name = "slave-kernel";
403 interrupt-controller;
404 #interrupt-cells = <2>;
409 compatible = "arm,armv8-pmuv3";
414 compatible = "arm,psci-1.0";
419 #address-cells = <2>;
420 #size-cells = <2>;
422 dma-ranges = <0 0 0 0 0x10 0>;
423 compatible = "simple-bus";
425 gcc: clock-controller@100000 {
426 compatible = "qcom,gcc-sc7280";
431 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
432 "pcie_0_pipe_clk", "pcie_1_pipe-clk",
436 #clock-cells = <1>;
437 #reset-cells = <1>;
438 #power-domain-cells = <1>;
441 ipcc: mailbox@408000 { label
442 compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
445 interrupt-controller;
446 #interrupt-cells = <3>;
447 #mbox-cells = <2>;
451 compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
457 clock-names = "core";
458 power-domains = <&rpmhpd SC7280_MX>;
459 #address-cells = <1>;
460 #size-cells = <1>;
464 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
469 reg-names = "hc", "cqhci";
474 interrupt-names = "hc_irq", "pwr_irq";
479 clock-names = "core", "iface", "xo";
482 interconnect-names = "sdhc-ddr","cpu-sdhc";
483 power-domains = <&rpmhpd SC7280_CX>;
484 operating-points-v2 = <&sdhc1_opp_table>;
486 bus-width = <8>;
487 supports-cqe;
489 qcom,dll-config = <0x0007642c>;
490 qcom,ddr-config = <0x80040868>;
492 mmc-ddr-1_8v;
493 mmc-hs200-1_8v;
494 mmc-hs400-1_8v;
495 mmc-hs400-enhanced-strobe;
497 sdhc1_opp_table: opp-table {
498 compatible = "operating-points-v2";
500 opp-100000000 {
501 opp-hz = /bits/ 64 <100000000>;
502 required-opps = <&rpmhpd_opp_low_svs>;
503 opp-peak-kBps = <1800000 400000>;
504 opp-avg-kBps = <100000 0>;
507 opp-384000000 {
508 opp-hz = /bits/ 64 <384000000>;
509 required-opps = <&rpmhpd_opp_nom>;
510 opp-peak-kBps = <5400000 1600000>;
511 opp-avg-kBps = <390000 0>;
518 compatible = "qcom,geni-se-qup";
520 clock-names = "m-ahb", "s-ahb";
523 #address-cells = <2>;
524 #size-cells = <2>;
529 compatible = "qcom,geni-debug-uart";
531 clock-names = "se";
533 pinctrl-names = "default";
534 pinctrl-0 = <&qup_uart5_default>;
542 compatible = "qcom,sc7280-cnoc2";
543 #interconnect-cells = <2>;
544 qcom,bcm-voters = <&apps_bcm_voter>;
549 compatible = "qcom,sc7280-cnoc3";
550 #interconnect-cells = <2>;
551 qcom,bcm-voters = <&apps_bcm_voter>;
556 compatible = "qcom,sc7280-mc-virt";
557 #interconnect-cells = <2>;
558 qcom,bcm-voters = <&apps_bcm_voter>;
563 compatible = "qcom,sc7280-system-noc";
564 #interconnect-cells = <2>;
565 qcom,bcm-voters = <&apps_bcm_voter>;
569 compatible = "qcom,sc7280-aggre1-noc";
571 #interconnect-cells = <2>;
572 qcom,bcm-voters = <&apps_bcm_voter>;
577 compatible = "qcom,sc7280-aggre2-noc";
578 #interconnect-cells = <2>;
579 qcom,bcm-voters = <&apps_bcm_voter>;
584 compatible = "qcom,sc7280-mmss-noc";
585 #interconnect-cells = <2>;
586 qcom,bcm-voters = <&apps_bcm_voter>;
590 compatible = "qcom,sc7280-ipa";
597 reg-names = "ipa-reg",
598 "ipa-shared",
601 interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>,
605 interrupt-names = "ipa",
607 "ipa-clock-query",
608 "ipa-setup-ready";
611 clock-names = "core";
615 interconnect-names = "memory",
618 qcom,smem-states = <&ipa_smp2p_out 0>,
620 qcom,smem-state-names = "ipa-clock-enabled-valid",
621 "ipa-clock-enabled";
627 compatible = "qcom,tcsr-mutex", "syscon";
629 #hwlock-cells = <1>;
633 compatible = "qcom,sc7280-lpasscc";
637 reg-names = "qdsp6ss", "top_cc", "cc";
639 clock-names = "iface";
640 #clock-cells = <1>;
645 compatible = "qcom,sc7280-lpass-ag-noc";
646 #interconnect-cells = <2>;
647 qcom,bcm-voters = <&apps_bcm_voter>;
650 gpucc: clock-controller@3d90000 {
651 compatible = "qcom,sc7280-gpucc";
656 clock-names = "bi_tcxo",
659 #clock-cells = <1>;
660 #reset-cells = <1>;
661 #power-domain-cells = <1>;
665 compatible = "arm,coresight-stm", "arm,primecell";
668 reg-names = "stm-base", "stm-stimulus-base";
671 clock-names = "apb_pclk";
673 out-ports {
676 remote-endpoint = <&funnel0_in7>;
683 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
687 clock-names = "apb_pclk";
689 out-ports {
692 remote-endpoint = <&merge_funnel_in0>;
697 in-ports {
698 #address-cells = <1>;
699 #size-cells = <0>;
704 remote-endpoint = <&stm_out>;
711 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
715 clock-names = "apb_pclk";
717 out-ports {
720 remote-endpoint = <&merge_funnel_in1>;
725 in-ports {
726 #address-cells = <1>;
727 #size-cells = <0>;
732 remote-endpoint = <&apss_merge_funnel_out>;
739 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
743 clock-names = "apb_pclk";
745 out-ports {
748 remote-endpoint = <&swao_funnel_in>;
753 in-ports {
754 #address-cells = <1>;
755 #size-cells = <0>;
760 remote-endpoint = <&funnel0_out>;
767 remote-endpoint = <&funnel1_out>;
774 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
778 clock-names = "apb_pclk";
780 out-ports {
783 remote-endpoint = <&etr_in>;
788 in-ports {
791 remote-endpoint = <&swao_replicator_out>;
798 compatible = "arm,coresight-tmc", "arm,primecell";
803 clock-names = "apb_pclk";
804 arm,scatter-gather;
806 in-ports {
809 remote-endpoint = <&replicator_out>;
816 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
820 clock-names = "apb_pclk";
822 out-ports {
825 remote-endpoint = <&etf_in>;
830 in-ports {
831 #address-cells = <1>;
832 #size-cells = <0>;
837 remote-endpoint = <&merge_funnel_out>;
844 compatible = "arm,coresight-tmc", "arm,primecell";
848 clock-names = "apb_pclk";
850 out-ports {
853 remote-endpoint = <&swao_replicator_in>;
858 in-ports {
861 remote-endpoint = <&swao_funnel_out>;
868 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
872 clock-names = "apb_pclk";
873 qcom,replicator-loses-context;
875 out-ports {
878 remote-endpoint = <&replicator_in>;
883 in-ports {
886 remote-endpoint = <&etf_out>;
893 compatible = "arm,coresight-etm4x", "arm,primecell";
899 clock-names = "apb_pclk";
900 arm,coresight-loses-context-with-cpu;
901 qcom,skip-power-up;
903 out-ports {
906 remote-endpoint = <&apss_funnel_in0>;
913 compatible = "arm,coresight-etm4x", "arm,primecell";
919 clock-names = "apb_pclk";
920 arm,coresight-loses-context-with-cpu;
921 qcom,skip-power-up;
923 out-ports {
926 remote-endpoint = <&apss_funnel_in1>;
933 compatible = "arm,coresight-etm4x", "arm,primecell";
939 clock-names = "apb_pclk";
940 arm,coresight-loses-context-with-cpu;
941 qcom,skip-power-up;
943 out-ports {
946 remote-endpoint = <&apss_funnel_in2>;
953 compatible = "arm,coresight-etm4x", "arm,primecell";
959 clock-names = "apb_pclk";
960 arm,coresight-loses-context-with-cpu;
961 qcom,skip-power-up;
963 out-ports {
966 remote-endpoint = <&apss_funnel_in3>;
973 compatible = "arm,coresight-etm4x", "arm,primecell";
979 clock-names = "apb_pclk";
980 arm,coresight-loses-context-with-cpu;
981 qcom,skip-power-up;
983 out-ports {
986 remote-endpoint = <&apss_funnel_in4>;
993 compatible = "arm,coresight-etm4x", "arm,primecell";
999 clock-names = "apb_pclk";
1000 arm,coresight-loses-context-with-cpu;
1001 qcom,skip-power-up;
1003 out-ports {
1006 remote-endpoint = <&apss_funnel_in5>;
1013 compatible = "arm,coresight-etm4x", "arm,primecell";
1019 clock-names = "apb_pclk";
1020 arm,coresight-loses-context-with-cpu;
1021 qcom,skip-power-up;
1023 out-ports {
1026 remote-endpoint = <&apss_funnel_in6>;
1033 compatible = "arm,coresight-etm4x", "arm,primecell";
1039 clock-names = "apb_pclk";
1040 arm,coresight-loses-context-with-cpu;
1041 qcom,skip-power-up;
1043 out-ports {
1046 remote-endpoint = <&apss_funnel_in7>;
1053 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1057 clock-names = "apb_pclk";
1059 out-ports {
1062 remote-endpoint = <&apss_merge_funnel_in>;
1067 in-ports {
1068 #address-cells = <1>;
1069 #size-cells = <0>;
1074 remote-endpoint = <&etm0_out>;
1081 remote-endpoint = <&etm1_out>;
1088 remote-endpoint = <&etm2_out>;
1095 remote-endpoint = <&etm3_out>;
1102 remote-endpoint = <&etm4_out>;
1109 remote-endpoint = <&etm5_out>;
1116 remote-endpoint = <&etm6_out>;
1123 remote-endpoint = <&etm7_out>;
1130 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1134 clock-names = "apb_pclk";
1136 out-ports {
1139 remote-endpoint = <&funnel1_in4>;
1144 in-ports {
1147 remote-endpoint = <&apss_funnel_out>;
1154 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
1162 interrupt-names = "hc_irq", "pwr_irq";
1167 clock-names = "core", "iface", "xo";
1170 interconnect-names = "sdhc-ddr","cpu-sdhc";
1171 power-domains = <&rpmhpd SC7280_CX>;
1172 operating-points-v2 = <&sdhc2_opp_table>;
1174 bus-width = <4>;
1176 qcom,dll-config = <0x0007642c>;
1178 sdhc2_opp_table: opp-table {
1179 compatible = "operating-points-v2";
1181 opp-100000000 {
1182 opp-hz = /bits/ 64 <100000000>;
1183 required-opps = <&rpmhpd_opp_low_svs>;
1184 opp-peak-kBps = <1800000 400000>;
1185 opp-avg-kBps = <100000 0>;
1188 opp-202000000 {
1189 opp-hz = /bits/ 64 <202000000>;
1190 required-opps = <&rpmhpd_opp_nom>;
1191 opp-peak-kBps = <5400000 1600000>;
1192 opp-avg-kBps = <200000 0>;
1199 compatible = "qcom,sc7280-usb-hs-phy",
1200 "qcom,usb-snps-hs-7nm-phy";
1203 #phy-cells = <0>;
1206 clock-names = "ref";
1212 compatible = "qcom,sc7280-usb-hs-phy",
1213 "qcom,usb-snps-hs-7nm-phy";
1216 #phy-cells = <0>;
1219 clock-names = "ref";
1224 usb_1_qmpphy: phy-wrapper@88e9000 {
1225 compatible = "qcom,sc7280-qmp-usb3-dp-phy",
1226 "qcom,sm8250-qmp-usb3-dp-phy";
1231 #address-cells = <2>;
1232 #size-cells = <2>;
1238 clock-names = "aux", "ref_clk_src", "com_aux";
1242 reset-names = "phy", "common";
1244 usb_1_ssphy: usb3-phy@88e9200 {
1251 #clock-cells = <0>;
1252 #phy-cells = <0>;
1254 clock-names = "pipe0";
1255 clock-output-names = "usb3_phy_pipe_clk_src";
1258 dp_phy: dp-phy@88ea200 {
1265 #phy-cells = <0>;
1266 #clock-cells = <1>;
1268 clock-names = "pipe0";
1269 clock-output-names = "usb3_phy_pipe_clk_src";
1274 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
1277 #address-cells = <2>;
1278 #size-cells = <2>;
1280 dma-ranges;
1287 clock-names = "cfg_noc", "core", "iface","mock_utmi",
1290 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1292 assigned-clock-rates = <19200000>, <200000000>;
1294 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1297 interrupt-names = "hs_phy_irq",
1300 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
1306 interconnect-names = "usb-ddr", "apps-usb";
1316 phy-names = "usb2-phy";
1317 maximum-speed = "high-speed";
1323 compatible = "qcom,sc7280-dc-noc";
1324 #interconnect-cells = <2>;
1325 qcom,bcm-voters = <&apps_bcm_voter>;
1330 compatible = "qcom,sc7280-gem-noc";
1331 #interconnect-cells = <2>;
1332 qcom,bcm-voters = <&apps_bcm_voter>;
1335 system-cache-controller@9200000 {
1336 compatible = "qcom,sc7280-llcc";
1338 reg-names = "llcc_base", "llcc_broadcast_base";
1344 compatible = "qcom,sc7280-nsp-noc";
1345 #interconnect-cells = <2>;
1346 qcom,bcm-voters = <&apps_bcm_voter>;
1350 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
1353 #address-cells = <2>;
1354 #size-cells = <2>;
1356 dma-ranges;
1363 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1366 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1368 assigned-clock-rates = <19200000>, <200000000>;
1370 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1374 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
1377 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1383 interconnect-names = "usb-ddr", "apps-usb";
1393 phy-names = "usb2-phy", "usb3-phy";
1394 maximum-speed = "super-speed";
1398 videocc: clock-controller@aaf0000 {
1399 compatible = "qcom,sc7280-videocc";
1403 clock-names = "bi_tcxo", "bi_tcxo_ao";
1404 #clock-cells = <1>;
1405 #reset-cells = <1>;
1406 #power-domain-cells = <1>;
1409 dispcc: clock-controller@af00000 {
1410 compatible = "qcom,sc7280-dispcc";
1415 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
1422 #clock-cells = <1>;
1423 #reset-cells = <1>;
1424 #power-domain-cells = <1>;
1427 pdc: interrupt-controller@b220000 {
1428 compatible = "qcom,sc7280-pdc", "qcom,pdc";
1430 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
1435 #interrupt-cells = <2>;
1436 interrupt-parent = <&intc>;
1437 interrupt-controller;
1440 pdc_reset: reset-controller@b5e0000 {
1441 compatible = "qcom,sc7280-pdc-global";
1443 #reset-cells = <1>;
1446 tsens0: thermal-sensor@c263000 {
1447 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
1450 #qcom,sensors = <15>;
1453 interrupt-names = "uplow","critical";
1454 #thermal-sensor-cells = <1>;
1457 tsens1: thermal-sensor@c265000 {
1458 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
1461 #qcom,sensors = <12>;
1464 interrupt-names = "uplow","critical";
1465 #thermal-sensor-cells = <1>;
1468 aoss_reset: reset-controller@c2a0000 {
1469 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
1471 #reset-cells = <1>;
1474 aoss_qmp: power-controller@c300000 {
1475 compatible = "qcom,sc7280-aoss-qmp";
1477 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
1480 mboxes = <&ipcc IPCC_CLIENT_AOP
1483 #clock-cells = <0>;
1484 #power-domain-cells = <1>;
1488 compatible = "qcom,spmi-pmic-arb";
1494 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1495 interrupt-names = "periph_irq";
1496 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1497 qcom,ee = <0>;
1498 qcom,channel = <0>;
1499 #address-cells = <1>;
1500 #size-cells = <1>;
1501 interrupt-controller;
1502 #interrupt-cells = <4>;
1506 compatible = "qcom,sc7280-pinctrl";
1509 gpio-controller;
1510 #gpio-cells = <2>;
1511 interrupt-controller;
1512 #interrupt-cells = <2>;
1513 gpio-ranges = <&tlmm 0 0 175>;
1514 wakeup-parent = <&pdc>;
1516 qup_uart5_default: qup-uart5-default {
1521 sdc1_on: sdc1-on {
1539 sdc1_off: sdc1-off {
1542 drive-strength = <2>;
1543 bias-bus-hold;
1548 drive-strength = <2>;
1549 bias-bus-hold;
1554 drive-strength = <2>;
1555 bias-bus-hold;
1560 bias-bus-hold;
1564 sdc2_on: sdc2-on {
1577 sd-cd {
1582 sdc2_off: sdc2-off {
1585 drive-strength = <2>;
1586 bias-bus-hold;
1591 drive-strength = <2>;
1592 bias-bus-hold;
1597 drive-strength = <2>;
1598 bias-bus-hold;
1604 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
1606 #iommu-cells = <2>;
1607 #global-interrupts = <1>;
1608 dma-coherent;
1692 intc: interrupt-controller@17a00000 {
1693 compatible = "arm,gic-v3";
1694 #address-cells = <2>;
1695 #size-cells = <2>;
1697 #interrupt-cells = <3>;
1698 interrupt-controller;
1703 gic-its@17a40000 {
1704 compatible = "arm,gic-v3-its";
1705 msi-controller;
1706 #msi-cells = <1>;
1713 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
1720 #address-cells = <2>;
1721 #size-cells = <2>;
1723 compatible = "arm,armv7-timer-mem";
1727 frame-number = <0>;
1735 frame-number = <1>;
1742 frame-number = <2>;
1749 frame-number = <3>;
1756 frame-number = <4>;
1763 frame-number = <5>;
1770 frame-number = <6>;
1778 compatible = "qcom,rpmh-rsc";
1782 reg-names = "drv-0", "drv-1", "drv-2";
1786 qcom,tcs-offset = <0xd00>;
1787 qcom,drv-id = <2>;
1788 qcom,tcs-config = <ACTIVE_TCS 2>,
1793 apps_bcm_voter: bcm-voter {
1794 compatible = "qcom,bcm-voter";
1797 rpmhpd: power-controller {
1798 compatible = "qcom,sc7280-rpmhpd";
1799 #power-domain-cells = <1>;
1800 operating-points-v2 = <&rpmhpd_opp_table>;
1802 rpmhpd_opp_table: opp-table {
1803 compatible = "operating-points-v2";
1806 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1810 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1814 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1818 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1822 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1826 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1830 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1834 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1838 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1843 rpmhcc: clock-controller {
1844 compatible = "qcom,sc7280-rpmh-clk";
1846 clock-names = "xo";
1847 #clock-cells = <1>;
1852 compatible = "qcom,cpufreq-epss";
1857 clock-names = "xo", "alternate";
1858 #freq-domain-cells = <1>;
1862 thermal_zones: thermal-zones {
1863 cpu0-thermal {
1864 polling-delay-passive = <250>;
1865 polling-delay = <0>;
1867 thermal-sensors = <&tsens0 1>;
1870 cpu0_alert0: trip-point0 {
1876 cpu0_alert1: trip-point1 {
1882 cpu0_crit: cpu-crit {
1889 cooling-maps {
1892 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1899 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1907 cpu1-thermal {
1908 polling-delay-passive = <250>;
1909 polling-delay = <0>;
1911 thermal-sensors = <&tsens0 2>;
1914 cpu1_alert0: trip-point0 {
1920 cpu1_alert1: trip-point1 {
1926 cpu1_crit: cpu-crit {
1933 cooling-maps {
1936 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1943 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1951 cpu2-thermal {
1952 polling-delay-passive = <250>;
1953 polling-delay = <0>;
1955 thermal-sensors = <&tsens0 3>;
1958 cpu2_alert0: trip-point0 {
1964 cpu2_alert1: trip-point1 {
1970 cpu2_crit: cpu-crit {
1977 cooling-maps {
1980 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1987 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1995 cpu3-thermal {
1996 polling-delay-passive = <250>;
1997 polling-delay = <0>;
1999 thermal-sensors = <&tsens0 4>;
2002 cpu3_alert0: trip-point0 {
2008 cpu3_alert1: trip-point1 {
2014 cpu3_crit: cpu-crit {
2021 cooling-maps {
2024 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2031 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2039 cpu4-thermal {
2040 polling-delay-passive = <250>;
2041 polling-delay = <0>;
2043 thermal-sensors = <&tsens0 7>;
2046 cpu4_alert0: trip-point0 {
2052 cpu4_alert1: trip-point1 {
2058 cpu4_crit: cpu-crit {
2065 cooling-maps {
2068 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2075 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2083 cpu5-thermal {
2084 polling-delay-passive = <250>;
2085 polling-delay = <0>;
2087 thermal-sensors = <&tsens0 8>;
2090 cpu5_alert0: trip-point0 {
2096 cpu5_alert1: trip-point1 {
2102 cpu5_crit: cpu-crit {
2109 cooling-maps {
2112 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2119 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2127 cpu6-thermal {
2128 polling-delay-passive = <250>;
2129 polling-delay = <0>;
2131 thermal-sensors = <&tsens0 9>;
2134 cpu6_alert0: trip-point0 {
2140 cpu6_alert1: trip-point1 {
2146 cpu6_crit: cpu-crit {
2153 cooling-maps {
2156 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2163 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2171 cpu7-thermal {
2172 polling-delay-passive = <250>;
2173 polling-delay = <0>;
2175 thermal-sensors = <&tsens0 10>;
2178 cpu7_alert0: trip-point0 {
2184 cpu7_alert1: trip-point1 {
2190 cpu7_crit: cpu-crit {
2197 cooling-maps {
2200 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2207 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2215 cpu8-thermal {
2216 polling-delay-passive = <250>;
2217 polling-delay = <0>;
2219 thermal-sensors = <&tsens0 11>;
2222 cpu8_alert0: trip-point0 {
2228 cpu8_alert1: trip-point1 {
2234 cpu8_crit: cpu-crit {
2241 cooling-maps {
2244 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2251 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2259 cpu9-thermal {
2260 polling-delay-passive = <250>;
2261 polling-delay = <0>;
2263 thermal-sensors = <&tsens0 12>;
2266 cpu9_alert0: trip-point0 {
2272 cpu9_alert1: trip-point1 {
2278 cpu9_crit: cpu-crit {
2285 cooling-maps {
2288 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2295 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2303 cpu10-thermal {
2304 polling-delay-passive = <250>;
2305 polling-delay = <0>;
2307 thermal-sensors = <&tsens0 13>;
2310 cpu10_alert0: trip-point0 {
2316 cpu10_alert1: trip-point1 {
2322 cpu10_crit: cpu-crit {
2329 cooling-maps {
2332 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2339 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2347 cpu11-thermal {
2348 polling-delay-passive = <250>;
2349 polling-delay = <0>;
2351 thermal-sensors = <&tsens0 14>;
2354 cpu11_alert0: trip-point0 {
2360 cpu11_alert1: trip-point1 {
2366 cpu11_crit: cpu-crit {
2373 cooling-maps {
2376 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2383 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2391 aoss0-thermal {
2392 polling-delay-passive = <0>;
2393 polling-delay = <0>;
2395 thermal-sensors = <&tsens0 0>;
2398 aoss0_alert0: trip-point0 {
2404 aoss0_crit: aoss0-crit {
2412 aoss1-thermal {
2413 polling-delay-passive = <0>;
2414 polling-delay = <0>;
2416 thermal-sensors = <&tsens1 0>;
2419 aoss1_alert0: trip-point0 {
2425 aoss1_crit: aoss1-crit {
2433 cpuss0-thermal {
2434 polling-delay-passive = <0>;
2435 polling-delay = <0>;
2437 thermal-sensors = <&tsens0 5>;
2440 cpuss0_alert0: trip-point0 {
2445 cpuss0_crit: cluster0-crit {
2453 cpuss1-thermal {
2454 polling-delay-passive = <0>;
2455 polling-delay = <0>;
2457 thermal-sensors = <&tsens0 6>;
2460 cpuss1_alert0: trip-point0 {
2465 cpuss1_crit: cluster0-crit {
2473 gpuss0-thermal {
2474 polling-delay-passive = <0>;
2475 polling-delay = <0>;
2477 thermal-sensors = <&tsens1 1>;
2480 gpuss0_alert0: trip-point0 {
2486 gpuss0_crit: gpuss0-crit {
2494 gpuss1-thermal {
2495 polling-delay-passive = <0>;
2496 polling-delay = <0>;
2498 thermal-sensors = <&tsens1 2>;
2501 gpuss1_alert0: trip-point0 {
2507 gpuss1_crit: gpuss1-crit {
2515 nspss0-thermal {
2516 polling-delay-passive = <0>;
2517 polling-delay = <0>;
2519 thermal-sensors = <&tsens1 3>;
2522 nspss0_alert0: trip-point0 {
2528 nspss0_crit: nspss0-crit {
2536 nspss1-thermal {
2537 polling-delay-passive = <0>;
2538 polling-delay = <0>;
2540 thermal-sensors = <&tsens1 4>;
2543 nspss1_alert0: trip-point0 {
2549 nspss1_crit: nspss1-crit {
2557 video-thermal {
2558 polling-delay-passive = <0>;
2559 polling-delay = <0>;
2561 thermal-sensors = <&tsens1 5>;
2564 video_alert0: trip-point0 {
2570 video_crit: video-crit {
2578 ddr-thermal {
2579 polling-delay-passive = <0>;
2580 polling-delay = <0>;
2582 thermal-sensors = <&tsens1 6>;
2585 ddr_alert0: trip-point0 {
2591 ddr_crit: ddr-crit {
2599 mdmss0-thermal {
2600 polling-delay-passive = <0>;
2601 polling-delay = <0>;
2603 thermal-sensors = <&tsens1 7>;
2606 mdmss0_alert0: trip-point0 {
2612 mdmss0_crit: mdmss0-crit {
2620 mdmss1-thermal {
2621 polling-delay-passive = <0>;
2622 polling-delay = <0>;
2624 thermal-sensors = <&tsens1 8>;
2627 mdmss1_alert0: trip-point0 {
2633 mdmss1_crit: mdmss1-crit {
2641 mdmss2-thermal {
2642 polling-delay-passive = <0>;
2643 polling-delay = <0>;
2645 thermal-sensors = <&tsens1 9>;
2648 mdmss2_alert0: trip-point0 {
2654 mdmss2_crit: mdmss2-crit {
2662 mdmss3-thermal {
2663 polling-delay-passive = <0>;
2664 polling-delay = <0>;
2666 thermal-sensors = <&tsens1 10>;
2669 mdmss3_alert0: trip-point0 {
2675 mdmss3_crit: mdmss3-crit {
2683 camera0-thermal {
2684 polling-delay-passive = <0>;
2685 polling-delay = <0>;
2687 thermal-sensors = <&tsens1 11>;
2690 camera0_alert0: trip-point0 {
2696 camera0_crit: camera0-crit {
2706 compatible = "arm,armv8-timer";