Lines Matching +full:sdm845 +full:- +full:aoss +full:- +full:cc
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sc7180.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
18 #include <dt-bindings/power/qcom-aoss-qmp.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
23 #include <dt-bindings/thermal/thermal.h>
26 interrupt-parent = <&intc>;
28 #address-cells = <2>;
29 #size-cells = <2>;
59 xo_board: xo-board {
60 compatible = "fixed-clock";
61 clock-frequency = <38400000>;
62 #clock-cells = <0>;
65 sleep_clk: sleep-clk {
66 compatible = "fixed-clock";
67 clock-frequency = <32764>;
68 #clock-cells = <0>;
72 reserved_memory: reserved-memory {
73 #address-cells = <2>;
74 #size-cells = <2>;
79 no-map;
84 no-map;
89 no-map;
94 compatible = "qcom,cmd-db";
95 no-map;
100 no-map;
105 no-map;
110 no-map;
115 no-map;
119 compatible = "qcom,rmtfs-mem";
121 no-map;
123 qcom,client-id = <1>;
129 #address-cells = <2>;
130 #size-cells = <0>;
136 enable-method = "psci";
137 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
140 capacity-dmips-mhz = <1024>;
141 dynamic-power-coefficient = <100>;
142 operating-points-v2 = <&cpu0_opp_table>;
145 next-level-cache = <&L2_0>;
146 #cooling-cells = <2>;
147 qcom,freq-domain = <&cpufreq_hw 0>;
148 L2_0: l2-cache {
150 next-level-cache = <&L3_0>;
151 L3_0: l3-cache {
161 enable-method = "psci";
162 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
165 capacity-dmips-mhz = <1024>;
166 dynamic-power-coefficient = <100>;
167 next-level-cache = <&L2_100>;
168 operating-points-v2 = <&cpu0_opp_table>;
171 #cooling-cells = <2>;
172 qcom,freq-domain = <&cpufreq_hw 0>;
173 L2_100: l2-cache {
175 next-level-cache = <&L3_0>;
183 enable-method = "psci";
184 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
187 capacity-dmips-mhz = <1024>;
188 dynamic-power-coefficient = <100>;
189 next-level-cache = <&L2_200>;
190 operating-points-v2 = <&cpu0_opp_table>;
193 #cooling-cells = <2>;
194 qcom,freq-domain = <&cpufreq_hw 0>;
195 L2_200: l2-cache {
197 next-level-cache = <&L3_0>;
205 enable-method = "psci";
206 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
209 capacity-dmips-mhz = <1024>;
210 dynamic-power-coefficient = <100>;
211 next-level-cache = <&L2_300>;
212 operating-points-v2 = <&cpu0_opp_table>;
215 #cooling-cells = <2>;
216 qcom,freq-domain = <&cpufreq_hw 0>;
217 L2_300: l2-cache {
219 next-level-cache = <&L3_0>;
227 enable-method = "psci";
228 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
231 capacity-dmips-mhz = <1024>;
232 dynamic-power-coefficient = <100>;
233 next-level-cache = <&L2_400>;
234 operating-points-v2 = <&cpu0_opp_table>;
237 #cooling-cells = <2>;
238 qcom,freq-domain = <&cpufreq_hw 0>;
239 L2_400: l2-cache {
241 next-level-cache = <&L3_0>;
249 enable-method = "psci";
250 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
253 capacity-dmips-mhz = <1024>;
254 dynamic-power-coefficient = <100>;
255 next-level-cache = <&L2_500>;
256 operating-points-v2 = <&cpu0_opp_table>;
259 #cooling-cells = <2>;
260 qcom,freq-domain = <&cpufreq_hw 0>;
261 L2_500: l2-cache {
263 next-level-cache = <&L3_0>;
271 enable-method = "psci";
272 cpu-idle-states = <&BIG_CPU_SLEEP_0
275 capacity-dmips-mhz = <1740>;
276 dynamic-power-coefficient = <405>;
277 next-level-cache = <&L2_600>;
278 operating-points-v2 = <&cpu6_opp_table>;
281 #cooling-cells = <2>;
282 qcom,freq-domain = <&cpufreq_hw 1>;
283 L2_600: l2-cache {
285 next-level-cache = <&L3_0>;
293 enable-method = "psci";
294 cpu-idle-states = <&BIG_CPU_SLEEP_0
297 capacity-dmips-mhz = <1740>;
298 dynamic-power-coefficient = <405>;
299 next-level-cache = <&L2_700>;
300 operating-points-v2 = <&cpu6_opp_table>;
303 #cooling-cells = <2>;
304 qcom,freq-domain = <&cpufreq_hw 1>;
305 L2_700: l2-cache {
307 next-level-cache = <&L3_0>;
311 cpu-map {
347 idle-states {
348 entry-method = "psci";
350 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
351 compatible = "arm,idle-state";
352 idle-state-name = "little-power-down";
353 arm,psci-suspend-param = <0x40000003>;
354 entry-latency-us = <549>;
355 exit-latency-us = <901>;
356 min-residency-us = <1774>;
357 local-timer-stop;
360 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
361 compatible = "arm,idle-state";
362 idle-state-name = "little-rail-power-down";
363 arm,psci-suspend-param = <0x40000004>;
364 entry-latency-us = <702>;
365 exit-latency-us = <915>;
366 min-residency-us = <4001>;
367 local-timer-stop;
370 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
371 compatible = "arm,idle-state";
372 idle-state-name = "big-power-down";
373 arm,psci-suspend-param = <0x40000003>;
374 entry-latency-us = <523>;
375 exit-latency-us = <1244>;
376 min-residency-us = <2207>;
377 local-timer-stop;
380 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
381 compatible = "arm,idle-state";
382 idle-state-name = "big-rail-power-down";
383 arm,psci-suspend-param = <0x40000004>;
384 entry-latency-us = <526>;
385 exit-latency-us = <1854>;
386 min-residency-us = <5555>;
387 local-timer-stop;
390 CLUSTER_SLEEP_0: cluster-sleep-0 {
391 compatible = "arm,idle-state";
392 idle-state-name = "cluster-power-down";
393 arm,psci-suspend-param = <0x40003444>;
394 entry-latency-us = <3263>;
395 exit-latency-us = <6562>;
396 min-residency-us = <9926>;
397 local-timer-stop;
403 compatible = "operating-points-v2";
404 opp-shared;
406 cpu0_opp1: opp-300000000 {
407 opp-hz = /bits/ 64 <300000000>;
408 opp-peak-kBps = <1200000 4800000>;
411 cpu0_opp2: opp-576000000 {
412 opp-hz = /bits/ 64 <576000000>;
413 opp-peak-kBps = <1200000 4800000>;
416 cpu0_opp3: opp-768000000 {
417 opp-hz = /bits/ 64 <768000000>;
418 opp-peak-kBps = <1200000 4800000>;
421 cpu0_opp4: opp-1017600000 {
422 opp-hz = /bits/ 64 <1017600000>;
423 opp-peak-kBps = <1804000 8908800>;
426 cpu0_opp5: opp-1248000000 {
427 opp-hz = /bits/ 64 <1248000000>;
428 opp-peak-kBps = <2188000 12902400>;
431 cpu0_opp6: opp-1324800000 {
432 opp-hz = /bits/ 64 <1324800000>;
433 opp-peak-kBps = <2188000 12902400>;
436 cpu0_opp7: opp-1516800000 {
437 opp-hz = /bits/ 64 <1516800000>;
438 opp-peak-kBps = <3072000 15052800>;
441 cpu0_opp8: opp-1612800000 {
442 opp-hz = /bits/ 64 <1612800000>;
443 opp-peak-kBps = <3072000 15052800>;
446 cpu0_opp9: opp-1708800000 {
447 opp-hz = /bits/ 64 <1708800000>;
448 opp-peak-kBps = <3072000 15052800>;
451 cpu0_opp10: opp-1804800000 {
452 opp-hz = /bits/ 64 <1804800000>;
453 opp-peak-kBps = <4068000 22425600>;
458 compatible = "operating-points-v2";
459 opp-shared;
461 cpu6_opp1: opp-300000000 {
462 opp-hz = /bits/ 64 <300000000>;
463 opp-peak-kBps = <2188000 8908800>;
466 cpu6_opp2: opp-652800000 {
467 opp-hz = /bits/ 64 <652800000>;
468 opp-peak-kBps = <2188000 8908800>;
471 cpu6_opp3: opp-825600000 {
472 opp-hz = /bits/ 64 <825600000>;
473 opp-peak-kBps = <2188000 8908800>;
476 cpu6_opp4: opp-979200000 {
477 opp-hz = /bits/ 64 <979200000>;
478 opp-peak-kBps = <2188000 8908800>;
481 cpu6_opp5: opp-1113600000 {
482 opp-hz = /bits/ 64 <1113600000>;
483 opp-peak-kBps = <2188000 8908800>;
486 cpu6_opp6: opp-1267200000 {
487 opp-hz = /bits/ 64 <1267200000>;
488 opp-peak-kBps = <4068000 12902400>;
491 cpu6_opp7: opp-1555200000 {
492 opp-hz = /bits/ 64 <1555200000>;
493 opp-peak-kBps = <4068000 15052800>;
496 cpu6_opp8: opp-1708800000 {
497 opp-hz = /bits/ 64 <1708800000>;
498 opp-peak-kBps = <6220000 19353600>;
501 cpu6_opp9: opp-1843200000 {
502 opp-hz = /bits/ 64 <1843200000>;
503 opp-peak-kBps = <6220000 19353600>;
506 cpu6_opp10: opp-1900800000 {
507 opp-hz = /bits/ 64 <1900800000>;
508 opp-peak-kBps = <6220000 22425600>;
511 cpu6_opp11: opp-1996800000 {
512 opp-hz = /bits/ 64 <1996800000>;
513 opp-peak-kBps = <6220000 22425600>;
516 cpu6_opp12: opp-2112000000 {
517 opp-hz = /bits/ 64 <2112000000>;
518 opp-peak-kBps = <6220000 22425600>;
521 cpu6_opp13: opp-2208000000 {
522 opp-hz = /bits/ 64 <2208000000>;
523 opp-peak-kBps = <7216000 22425600>;
526 cpu6_opp14: opp-2323200000 {
527 opp-hz = /bits/ 64 <2323200000>;
528 opp-peak-kBps = <7216000 22425600>;
531 cpu6_opp15: opp-2400000000 {
532 opp-hz = /bits/ 64 <2400000000>;
533 opp-peak-kBps = <8532000 23347200>;
536 cpu6_opp16: opp-2553600000 {
537 opp-hz = /bits/ 64 <2553600000>;
538 opp-peak-kBps = <8532000 23347200>;
549 compatible = "arm,armv8-pmuv3";
555 compatible = "qcom,scm-sc7180", "qcom,scm";
560 compatible = "qcom,tcsr-mutex";
562 #hwlock-cells = <1>;
567 memory-region = <&smem_mem>;
571 smp2p-cdsp {
579 qcom,local-pid = <0>;
580 qcom,remote-pid = <5>;
582 cdsp_smp2p_out: master-kernel {
583 qcom,entry-name = "master-kernel";
584 #qcom,smem-state-cells = <1>;
587 cdsp_smp2p_in: slave-kernel {
588 qcom,entry-name = "slave-kernel";
590 interrupt-controller;
591 #interrupt-cells = <2>;
595 smp2p-lpass {
603 qcom,local-pid = <0>;
604 qcom,remote-pid = <2>;
606 adsp_smp2p_out: master-kernel {
607 qcom,entry-name = "master-kernel";
608 #qcom,smem-state-cells = <1>;
611 adsp_smp2p_in: slave-kernel {
612 qcom,entry-name = "slave-kernel";
614 interrupt-controller;
615 #interrupt-cells = <2>;
619 smp2p-mpss {
624 qcom,local-pid = <0>;
625 qcom,remote-pid = <1>;
627 modem_smp2p_out: master-kernel {
628 qcom,entry-name = "master-kernel";
629 #qcom,smem-state-cells = <1>;
632 modem_smp2p_in: slave-kernel {
633 qcom,entry-name = "slave-kernel";
634 interrupt-controller;
635 #interrupt-cells = <2>;
638 ipa_smp2p_out: ipa-ap-to-modem {
639 qcom,entry-name = "ipa";
640 #qcom,smem-state-cells = <1>;
643 ipa_smp2p_in: ipa-modem-to-ap {
644 qcom,entry-name = "ipa";
645 interrupt-controller;
646 #interrupt-cells = <2>;
651 compatible = "arm,psci-1.0";
656 #address-cells = <2>;
657 #size-cells = <2>;
659 dma-ranges = <0 0 0 0 0x10 0>;
660 compatible = "simple-bus";
662 gcc: clock-controller@100000 {
663 compatible = "qcom,gcc-sc7180";
668 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
669 #clock-cells = <1>;
670 #reset-cells = <1>;
671 #power-domain-cells = <1>;
675 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
682 clock-names = "core";
683 #address-cells = <1>;
684 #size-cells = <1>;
686 qusb2p_hstx_trim: hstx-trim-primary@25b {
698 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
701 reg-names = "hc", "cqhci";
706 interrupt-names = "hc_irq", "pwr_irq";
711 clock-names = "core", "iface", "xo";
714 interconnect-names = "sdhc-ddr","cpu-sdhc";
715 power-domains = <&rpmhpd SC7180_CX>;
716 operating-points-v2 = <&sdhc1_opp_table>;
718 bus-width = <8>;
719 non-removable;
720 supports-cqe;
722 mmc-ddr-1_8v;
723 mmc-hs200-1_8v;
724 mmc-hs400-1_8v;
725 mmc-hs400-enhanced-strobe;
729 sdhc1_opp_table: sdhc1-opp-table {
730 compatible = "operating-points-v2";
732 opp-100000000 {
733 opp-hz = /bits/ 64 <100000000>;
734 required-opps = <&rpmhpd_opp_low_svs>;
735 opp-peak-kBps = <1800000 600000>;
736 opp-avg-kBps = <100000 0>;
739 opp-384000000 {
740 opp-hz = /bits/ 64 <384000000>;
741 required-opps = <&rpmhpd_opp_nom>;
742 opp-peak-kBps = <5400000 1600000>;
743 opp-avg-kBps = <390000 0>;
748 qup_opp_table: qup-opp-table {
749 compatible = "operating-points-v2";
751 opp-75000000 {
752 opp-hz = /bits/ 64 <75000000>;
753 required-opps = <&rpmhpd_opp_low_svs>;
756 opp-100000000 {
757 opp-hz = /bits/ 64 <100000000>;
758 required-opps = <&rpmhpd_opp_svs>;
761 opp-128000000 {
762 opp-hz = /bits/ 64 <128000000>;
763 required-opps = <&rpmhpd_opp_nom>;
768 compatible = "qcom,geni-se-qup";
770 clock-names = "m-ahb", "s-ahb";
773 #address-cells = <2>;
774 #size-cells = <2>;
780 compatible = "qcom,geni-i2c";
782 clock-names = "se";
784 pinctrl-names = "default";
785 pinctrl-0 = <&qup_i2c0_default>;
787 #address-cells = <1>;
788 #size-cells = <0>;
792 interconnect-names = "qup-core", "qup-config",
793 "qup-memory";
794 power-domains = <&rpmhpd SC7180_CX>;
795 required-opps = <&rpmhpd_opp_low_svs>;
800 compatible = "qcom,geni-spi";
802 clock-names = "se";
804 pinctrl-names = "default";
805 pinctrl-0 = <&qup_spi0_default>;
807 #address-cells = <1>;
808 #size-cells = <0>;
809 power-domains = <&rpmhpd SC7180_CX>;
810 operating-points-v2 = <&qup_opp_table>;
813 interconnect-names = "qup-core", "qup-config";
818 compatible = "qcom,geni-uart";
820 clock-names = "se";
822 pinctrl-names = "default";
823 pinctrl-0 = <&qup_uart0_default>;
825 power-domains = <&rpmhpd SC7180_CX>;
826 operating-points-v2 = <&qup_opp_table>;
829 interconnect-names = "qup-core", "qup-config";
834 compatible = "qcom,geni-i2c";
836 clock-names = "se";
838 pinctrl-names = "default";
839 pinctrl-0 = <&qup_i2c1_default>;
841 #address-cells = <1>;
842 #size-cells = <0>;
846 interconnect-names = "qup-core", "qup-config",
847 "qup-memory";
848 power-domains = <&rpmhpd SC7180_CX>;
849 required-opps = <&rpmhpd_opp_low_svs>;
854 compatible = "qcom,geni-spi";
856 clock-names = "se";
858 pinctrl-names = "default";
859 pinctrl-0 = <&qup_spi1_default>;
861 #address-cells = <1>;
862 #size-cells = <0>;
863 power-domains = <&rpmhpd SC7180_CX>;
864 operating-points-v2 = <&qup_opp_table>;
867 interconnect-names = "qup-core", "qup-config";
872 compatible = "qcom,geni-uart";
874 clock-names = "se";
876 pinctrl-names = "default";
877 pinctrl-0 = <&qup_uart1_default>;
879 power-domains = <&rpmhpd SC7180_CX>;
880 operating-points-v2 = <&qup_opp_table>;
883 interconnect-names = "qup-core", "qup-config";
888 compatible = "qcom,geni-i2c";
890 clock-names = "se";
892 pinctrl-names = "default";
893 pinctrl-0 = <&qup_i2c2_default>;
895 #address-cells = <1>;
896 #size-cells = <0>;
900 interconnect-names = "qup-core", "qup-config",
901 "qup-memory";
902 power-domains = <&rpmhpd SC7180_CX>;
903 required-opps = <&rpmhpd_opp_low_svs>;
908 compatible = "qcom,geni-uart";
910 clock-names = "se";
912 pinctrl-names = "default";
913 pinctrl-0 = <&qup_uart2_default>;
915 power-domains = <&rpmhpd SC7180_CX>;
916 operating-points-v2 = <&qup_opp_table>;
919 interconnect-names = "qup-core", "qup-config";
924 compatible = "qcom,geni-i2c";
926 clock-names = "se";
928 pinctrl-names = "default";
929 pinctrl-0 = <&qup_i2c3_default>;
931 #address-cells = <1>;
932 #size-cells = <0>;
936 interconnect-names = "qup-core", "qup-config",
937 "qup-memory";
938 power-domains = <&rpmhpd SC7180_CX>;
939 required-opps = <&rpmhpd_opp_low_svs>;
944 compatible = "qcom,geni-spi";
946 clock-names = "se";
948 pinctrl-names = "default";
949 pinctrl-0 = <&qup_spi3_default>;
951 #address-cells = <1>;
952 #size-cells = <0>;
953 power-domains = <&rpmhpd SC7180_CX>;
954 operating-points-v2 = <&qup_opp_table>;
957 interconnect-names = "qup-core", "qup-config";
962 compatible = "qcom,geni-uart";
964 clock-names = "se";
966 pinctrl-names = "default";
967 pinctrl-0 = <&qup_uart3_default>;
969 power-domains = <&rpmhpd SC7180_CX>;
970 operating-points-v2 = <&qup_opp_table>;
973 interconnect-names = "qup-core", "qup-config";
978 compatible = "qcom,geni-i2c";
980 clock-names = "se";
982 pinctrl-names = "default";
983 pinctrl-0 = <&qup_i2c4_default>;
985 #address-cells = <1>;
986 #size-cells = <0>;
990 interconnect-names = "qup-core", "qup-config",
991 "qup-memory";
992 power-domains = <&rpmhpd SC7180_CX>;
993 required-opps = <&rpmhpd_opp_low_svs>;
998 compatible = "qcom,geni-uart";
1000 clock-names = "se";
1002 pinctrl-names = "default";
1003 pinctrl-0 = <&qup_uart4_default>;
1005 power-domains = <&rpmhpd SC7180_CX>;
1006 operating-points-v2 = <&qup_opp_table>;
1009 interconnect-names = "qup-core", "qup-config";
1014 compatible = "qcom,geni-i2c";
1016 clock-names = "se";
1018 pinctrl-names = "default";
1019 pinctrl-0 = <&qup_i2c5_default>;
1021 #address-cells = <1>;
1022 #size-cells = <0>;
1026 interconnect-names = "qup-core", "qup-config",
1027 "qup-memory";
1028 power-domains = <&rpmhpd SC7180_CX>;
1029 required-opps = <&rpmhpd_opp_low_svs>;
1034 compatible = "qcom,geni-spi";
1036 clock-names = "se";
1038 pinctrl-names = "default";
1039 pinctrl-0 = <&qup_spi5_default>;
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1043 power-domains = <&rpmhpd SC7180_CX>;
1044 operating-points-v2 = <&qup_opp_table>;
1047 interconnect-names = "qup-core", "qup-config";
1052 compatible = "qcom,geni-uart";
1054 clock-names = "se";
1056 pinctrl-names = "default";
1057 pinctrl-0 = <&qup_uart5_default>;
1059 power-domains = <&rpmhpd SC7180_CX>;
1060 operating-points-v2 = <&qup_opp_table>;
1063 interconnect-names = "qup-core", "qup-config";
1069 compatible = "qcom,geni-se-qup";
1071 clock-names = "m-ahb", "s-ahb";
1074 #address-cells = <2>;
1075 #size-cells = <2>;
1081 compatible = "qcom,geni-i2c";
1083 clock-names = "se";
1085 pinctrl-names = "default";
1086 pinctrl-0 = <&qup_i2c6_default>;
1088 #address-cells = <1>;
1089 #size-cells = <0>;
1093 interconnect-names = "qup-core", "qup-config",
1094 "qup-memory";
1095 power-domains = <&rpmhpd SC7180_CX>;
1096 required-opps = <&rpmhpd_opp_low_svs>;
1101 compatible = "qcom,geni-spi";
1103 clock-names = "se";
1105 pinctrl-names = "default";
1106 pinctrl-0 = <&qup_spi6_default>;
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1110 power-domains = <&rpmhpd SC7180_CX>;
1111 operating-points-v2 = <&qup_opp_table>;
1114 interconnect-names = "qup-core", "qup-config";
1119 compatible = "qcom,geni-uart";
1121 clock-names = "se";
1123 pinctrl-names = "default";
1124 pinctrl-0 = <&qup_uart6_default>;
1126 power-domains = <&rpmhpd SC7180_CX>;
1127 operating-points-v2 = <&qup_opp_table>;
1130 interconnect-names = "qup-core", "qup-config";
1135 compatible = "qcom,geni-i2c";
1137 clock-names = "se";
1139 pinctrl-names = "default";
1140 pinctrl-0 = <&qup_i2c7_default>;
1142 #address-cells = <1>;
1143 #size-cells = <0>;
1147 interconnect-names = "qup-core", "qup-config",
1148 "qup-memory";
1149 power-domains = <&rpmhpd SC7180_CX>;
1150 required-opps = <&rpmhpd_opp_low_svs>;
1155 compatible = "qcom,geni-uart";
1157 clock-names = "se";
1159 pinctrl-names = "default";
1160 pinctrl-0 = <&qup_uart7_default>;
1162 power-domains = <&rpmhpd SC7180_CX>;
1163 operating-points-v2 = <&qup_opp_table>;
1166 interconnect-names = "qup-core", "qup-config";
1171 compatible = "qcom,geni-i2c";
1173 clock-names = "se";
1175 pinctrl-names = "default";
1176 pinctrl-0 = <&qup_i2c8_default>;
1178 #address-cells = <1>;
1179 #size-cells = <0>;
1183 interconnect-names = "qup-core", "qup-config",
1184 "qup-memory";
1185 power-domains = <&rpmhpd SC7180_CX>;
1186 required-opps = <&rpmhpd_opp_low_svs>;
1191 compatible = "qcom,geni-spi";
1193 clock-names = "se";
1195 pinctrl-names = "default";
1196 pinctrl-0 = <&qup_spi8_default>;
1198 #address-cells = <1>;
1199 #size-cells = <0>;
1200 power-domains = <&rpmhpd SC7180_CX>;
1201 operating-points-v2 = <&qup_opp_table>;
1204 interconnect-names = "qup-core", "qup-config";
1209 compatible = "qcom,geni-debug-uart";
1211 clock-names = "se";
1213 pinctrl-names = "default";
1214 pinctrl-0 = <&qup_uart8_default>;
1216 power-domains = <&rpmhpd SC7180_CX>;
1217 operating-points-v2 = <&qup_opp_table>;
1220 interconnect-names = "qup-core", "qup-config";
1225 compatible = "qcom,geni-i2c";
1227 clock-names = "se";
1229 pinctrl-names = "default";
1230 pinctrl-0 = <&qup_i2c9_default>;
1232 #address-cells = <1>;
1233 #size-cells = <0>;
1237 interconnect-names = "qup-core", "qup-config",
1238 "qup-memory";
1239 power-domains = <&rpmhpd SC7180_CX>;
1240 required-opps = <&rpmhpd_opp_low_svs>;
1245 compatible = "qcom,geni-uart";
1247 clock-names = "se";
1249 pinctrl-names = "default";
1250 pinctrl-0 = <&qup_uart9_default>;
1252 power-domains = <&rpmhpd SC7180_CX>;
1253 operating-points-v2 = <&qup_opp_table>;
1256 interconnect-names = "qup-core", "qup-config";
1261 compatible = "qcom,geni-i2c";
1263 clock-names = "se";
1265 pinctrl-names = "default";
1266 pinctrl-0 = <&qup_i2c10_default>;
1268 #address-cells = <1>;
1269 #size-cells = <0>;
1273 interconnect-names = "qup-core", "qup-config",
1274 "qup-memory";
1275 power-domains = <&rpmhpd SC7180_CX>;
1276 required-opps = <&rpmhpd_opp_low_svs>;
1281 compatible = "qcom,geni-spi";
1283 clock-names = "se";
1285 pinctrl-names = "default";
1286 pinctrl-0 = <&qup_spi10_default>;
1288 #address-cells = <1>;
1289 #size-cells = <0>;
1290 power-domains = <&rpmhpd SC7180_CX>;
1291 operating-points-v2 = <&qup_opp_table>;
1294 interconnect-names = "qup-core", "qup-config";
1299 compatible = "qcom,geni-uart";
1301 clock-names = "se";
1303 pinctrl-names = "default";
1304 pinctrl-0 = <&qup_uart10_default>;
1306 power-domains = <&rpmhpd SC7180_CX>;
1307 operating-points-v2 = <&qup_opp_table>;
1310 interconnect-names = "qup-core", "qup-config";
1315 compatible = "qcom,geni-i2c";
1317 clock-names = "se";
1319 pinctrl-names = "default";
1320 pinctrl-0 = <&qup_i2c11_default>;
1322 #address-cells = <1>;
1323 #size-cells = <0>;
1327 interconnect-names = "qup-core", "qup-config",
1328 "qup-memory";
1329 power-domains = <&rpmhpd SC7180_CX>;
1330 required-opps = <&rpmhpd_opp_low_svs>;
1335 compatible = "qcom,geni-spi";
1337 clock-names = "se";
1339 pinctrl-names = "default";
1340 pinctrl-0 = <&qup_spi11_default>;
1342 #address-cells = <1>;
1343 #size-cells = <0>;
1344 power-domains = <&rpmhpd SC7180_CX>;
1345 operating-points-v2 = <&qup_opp_table>;
1348 interconnect-names = "qup-core", "qup-config";
1353 compatible = "qcom,geni-uart";
1355 clock-names = "se";
1357 pinctrl-names = "default";
1358 pinctrl-0 = <&qup_uart11_default>;
1360 power-domains = <&rpmhpd SC7180_CX>;
1361 operating-points-v2 = <&qup_opp_table>;
1364 interconnect-names = "qup-core", "qup-config";
1370 compatible = "qcom,sc7180-config-noc";
1372 #interconnect-cells = <2>;
1373 qcom,bcm-voters = <&apps_bcm_voter>;
1377 compatible = "qcom,sc7180-system-noc";
1379 #interconnect-cells = <2>;
1380 qcom,bcm-voters = <&apps_bcm_voter>;
1384 compatible = "qcom,sc7180-mc-virt";
1386 #interconnect-cells = <2>;
1387 qcom,bcm-voters = <&apps_bcm_voter>;
1391 compatible = "qcom,sc7180-qup-virt";
1393 #interconnect-cells = <2>;
1394 qcom,bcm-voters = <&apps_bcm_voter>;
1398 compatible = "qcom,sc7180-aggre1-noc";
1400 #interconnect-cells = <2>;
1401 qcom,bcm-voters = <&apps_bcm_voter>;
1405 compatible = "qcom,sc7180-aggre2-noc";
1407 #interconnect-cells = <2>;
1408 qcom,bcm-voters = <&apps_bcm_voter>;
1412 compatible = "qcom,sc7180-compute-noc";
1414 #interconnect-cells = <2>;
1415 qcom,bcm-voters = <&apps_bcm_voter>;
1419 compatible = "qcom,sc7180-mmss-noc";
1421 #interconnect-cells = <2>;
1422 qcom,bcm-voters = <&apps_bcm_voter>;
1426 compatible = "qcom,sc7180-ipa-virt";
1428 #interconnect-cells = <2>;
1429 qcom,bcm-voters = <&apps_bcm_voter>;
1433 compatible = "qcom,sc7180-ipa";
1440 reg-names = "ipa-reg",
1441 "ipa-shared",
1444 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1448 interrupt-names = "ipa",
1450 "ipa-clock-query",
1451 "ipa-setup-ready";
1454 clock-names = "core";
1459 interconnect-names = "memory",
1463 qcom,smem-states = <&ipa_smp2p_out 0>,
1465 qcom,smem-state-names = "ipa-clock-enabled-valid",
1466 "ipa-clock-enabled";
1482 compatible = "qcom,sc7180-pinctrl";
1486 reg-names = "west", "north", "south";
1488 gpio-controller;
1489 #gpio-cells = <2>;
1490 interrupt-controller;
1491 #interrupt-cells = <2>;
1492 gpio-ranges = <&tlmm 0 0 120>;
1493 wakeup-parent = <&pdc>;
1495 dp_hot_plug_det: dp-hot-plug-det {
1502 qspi_clk: qspi-clk {
1509 qspi_cs0: qspi-cs0 {
1516 qspi_cs1: qspi-cs1 {
1523 qspi_data01: qspi-data01 {
1524 pinmux-data {
1530 qspi_data12: qspi-data12 {
1531 pinmux-data {
1537 qup_i2c0_default: qup-i2c0-default {
1544 qup_i2c1_default: qup-i2c1-default {
1551 qup_i2c2_default: qup-i2c2-default {
1558 qup_i2c3_default: qup-i2c3-default {
1565 qup_i2c4_default: qup-i2c4-default {
1572 qup_i2c5_default: qup-i2c5-default {
1579 qup_i2c6_default: qup-i2c6-default {
1586 qup_i2c7_default: qup-i2c7-default {
1593 qup_i2c8_default: qup-i2c8-default {
1600 qup_i2c9_default: qup-i2c9-default {
1607 qup_i2c10_default: qup-i2c10-default {
1614 qup_i2c11_default: qup-i2c11-default {
1621 qup_spi0_default: qup-spi0-default {
1629 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
1636 pinmux-cs {
1642 qup_spi1_default: qup-spi1-default {
1650 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
1657 pinmux-cs {
1663 qup_spi3_default: qup-spi3-default {
1671 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
1678 pinmux-cs {
1684 qup_spi5_default: qup-spi5-default {
1692 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
1699 pinmux-cs {
1705 qup_spi6_default: qup-spi6-default {
1713 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
1720 pinmux-cs {
1726 qup_spi8_default: qup-spi8-default {
1734 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
1741 pinmux-cs {
1747 qup_spi10_default: qup-spi10-default {
1755 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
1762 pinmux-cs {
1768 qup_spi11_default: qup-spi11-default {
1776 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
1783 pinmux-cs {
1789 qup_uart0_default: qup-uart0-default {
1797 qup_uart1_default: qup-uart1-default {
1805 qup_uart2_default: qup-uart2-default {
1812 qup_uart3_default: qup-uart3-default {
1820 qup_uart4_default: qup-uart4-default {
1827 qup_uart5_default: qup-uart5-default {
1835 qup_uart6_default: qup-uart6-default {
1843 qup_uart7_default: qup-uart7-default {
1850 qup_uart8_default: qup-uart8-default {
1857 qup_uart9_default: qup-uart9-default {
1864 qup_uart10_default: qup-uart10-default {
1872 qup_uart11_default: qup-uart11-default {
1880 sec_mi2s_active: sec-mi2s-active {
1887 pri_mi2s_active: pri-mi2s-active {
1894 pri_mi2s_mclk_active: pri-mi2s-mclk-active {
1903 compatible = "qcom,sc7180-mpss-pas";
1905 reg-names = "qdsp6", "rmb";
1907 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
1913 interrupt-names = "wdog", "fatal", "ready", "handover",
1914 "stop-ack", "shutdown-ack";
1922 clock-names = "iface", "bus", "nav", "snoc_axi",
1925 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
1929 power-domain-names = "load_state", "cx", "mx", "mss";
1931 memory-region = <&mpss_mem>;
1933 qcom,smem-states = <&modem_smp2p_out 0>;
1934 qcom,smem-state-names = "stop";
1938 reset-names = "mss_restart", "pdc_reset";
1940 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1941 qcom,spare-regs = <&tcsr_regs 0xb3e4>;
1945 glink-edge {
1948 qcom,remote-pid = <1>;
1954 compatible = "qcom,adreno-618.0", "qcom,adreno";
1955 #stream-id-cells = <16>;
1958 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
1961 operating-points-v2 = <&gpu_opp_table>;
1964 #cooling-cells = <2>;
1966 nvmem-cells = <&gpu_speed_bin>;
1967 nvmem-cell-names = "speed_bin";
1970 interconnect-names = "gfx-mem";
1972 gpu_opp_table: opp-table {
1973 compatible = "operating-points-v2";
1975 opp-825000000 {
1976 opp-hz = /bits/ 64 <825000000>;
1977 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1978 opp-peak-kBps = <8532000>;
1979 opp-supported-hw = <0x04>;
1982 opp-800000000 {
1983 opp-hz = /bits/ 64 <800000000>;
1984 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1985 opp-peak-kBps = <8532000>;
1986 opp-supported-hw = <0x07>;
1989 opp-650000000 {
1990 opp-hz = /bits/ 64 <650000000>;
1991 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1992 opp-peak-kBps = <7216000>;
1993 opp-supported-hw = <0x07>;
1996 opp-565000000 {
1997 opp-hz = /bits/ 64 <565000000>;
1998 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1999 opp-peak-kBps = <5412000>;
2000 opp-supported-hw = <0x07>;
2003 opp-430000000 {
2004 opp-hz = /bits/ 64 <430000000>;
2005 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2006 opp-peak-kBps = <5412000>;
2007 opp-supported-hw = <0x07>;
2010 opp-355000000 {
2011 opp-hz = /bits/ 64 <355000000>;
2012 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2013 opp-peak-kBps = <3072000>;
2014 opp-supported-hw = <0x07>;
2017 opp-267000000 {
2018 opp-hz = /bits/ 64 <267000000>;
2019 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2020 opp-peak-kBps = <3072000>;
2021 opp-supported-hw = <0x07>;
2024 opp-180000000 {
2025 opp-hz = /bits/ 64 <180000000>;
2026 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2027 opp-peak-kBps = <1804000>;
2028 opp-supported-hw = <0x07>;
2034 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2036 #iommu-cells = <1>;
2037 #global-interrupts = <2>;
2051 clock-names = "bus", "iface";
2053 power-domains = <&gpucc CX_GDSC>;
2057 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2060 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2063 interrupt-names = "hfi", "gmu";
2068 clock-names = "gmu", "cxo", "axi", "memnoc";
2069 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2070 power-domain-names = "cx", "gx";
2072 operating-points-v2 = <&gmu_opp_table>;
2074 gmu_opp_table: opp-table {
2075 compatible = "operating-points-v2";
2077 opp-200000000 {
2078 opp-hz = /bits/ 64 <200000000>;
2079 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2084 gpucc: clock-controller@5090000 {
2085 compatible = "qcom,sc7180-gpucc";
2090 clock-names = "bi_tcxo",
2093 #clock-cells = <1>;
2094 #reset-cells = <1>;
2095 #power-domain-cells = <1>;
2099 compatible = "arm,coresight-stm", "arm,primecell";
2102 reg-names = "stm-base", "stm-stimulus-base";
2105 clock-names = "apb_pclk";
2107 out-ports {
2110 remote-endpoint = <&funnel0_in7>;
2117 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2121 clock-names = "apb_pclk";
2123 out-ports {
2126 remote-endpoint = <&merge_funnel_in0>;
2131 in-ports {
2132 #address-cells = <1>;
2133 #size-cells = <0>;
2138 remote-endpoint = <&stm_out>;
2145 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2149 clock-names = "apb_pclk";
2151 out-ports {
2154 remote-endpoint = <&merge_funnel_in1>;
2159 in-ports {
2160 #address-cells = <1>;
2161 #size-cells = <0>;
2166 remote-endpoint = <&apss_merge_funnel_out>;
2173 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2177 clock-names = "apb_pclk";
2179 out-ports {
2182 remote-endpoint = <&swao_funnel_in>;
2187 in-ports {
2188 #address-cells = <1>;
2189 #size-cells = <0>;
2194 remote-endpoint = <&funnel0_out>;
2201 remote-endpoint = <&funnel1_out>;
2208 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2212 clock-names = "apb_pclk";
2214 out-ports {
2217 remote-endpoint = <&etr_in>;
2222 in-ports {
2225 remote-endpoint = <&swao_replicator_out>;
2232 compatible = "arm,coresight-tmc", "arm,primecell";
2237 clock-names = "apb_pclk";
2238 arm,scatter-gather;
2240 in-ports {
2243 remote-endpoint = <&replicator_out>;
2250 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2254 clock-names = "apb_pclk";
2256 out-ports {
2259 remote-endpoint = <&etf_in>;
2264 in-ports {
2265 #address-cells = <1>;
2266 #size-cells = <0>;
2271 remote-endpoint = <&merge_funnel_out>;
2278 compatible = "arm,coresight-tmc", "arm,primecell";
2282 clock-names = "apb_pclk";
2284 out-ports {
2287 remote-endpoint = <&swao_replicator_in>;
2292 in-ports {
2295 remote-endpoint = <&swao_funnel_out>;
2302 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2306 clock-names = "apb_pclk";
2307 qcom,replicator-loses-context;
2309 out-ports {
2312 remote-endpoint = <&replicator_in>;
2317 in-ports {
2320 remote-endpoint = <&etf_out>;
2327 compatible = "arm,coresight-etm4x", "arm,primecell";
2333 clock-names = "apb_pclk";
2334 arm,coresight-loses-context-with-cpu;
2335 qcom,skip-power-up;
2337 out-ports {
2340 remote-endpoint = <&apss_funnel_in0>;
2347 compatible = "arm,coresight-etm4x", "arm,primecell";
2353 clock-names = "apb_pclk";
2354 arm,coresight-loses-context-with-cpu;
2355 qcom,skip-power-up;
2357 out-ports {
2360 remote-endpoint = <&apss_funnel_in1>;
2367 compatible = "arm,coresight-etm4x", "arm,primecell";
2373 clock-names = "apb_pclk";
2374 arm,coresight-loses-context-with-cpu;
2375 qcom,skip-power-up;
2377 out-ports {
2380 remote-endpoint = <&apss_funnel_in2>;
2387 compatible = "arm,coresight-etm4x", "arm,primecell";
2393 clock-names = "apb_pclk";
2394 arm,coresight-loses-context-with-cpu;
2395 qcom,skip-power-up;
2397 out-ports {
2400 remote-endpoint = <&apss_funnel_in3>;
2407 compatible = "arm,coresight-etm4x", "arm,primecell";
2413 clock-names = "apb_pclk";
2414 arm,coresight-loses-context-with-cpu;
2415 qcom,skip-power-up;
2417 out-ports {
2420 remote-endpoint = <&apss_funnel_in4>;
2427 compatible = "arm,coresight-etm4x", "arm,primecell";
2433 clock-names = "apb_pclk";
2434 arm,coresight-loses-context-with-cpu;
2435 qcom,skip-power-up;
2437 out-ports {
2440 remote-endpoint = <&apss_funnel_in5>;
2447 compatible = "arm,coresight-etm4x", "arm,primecell";
2453 clock-names = "apb_pclk";
2454 arm,coresight-loses-context-with-cpu;
2455 qcom,skip-power-up;
2457 out-ports {
2460 remote-endpoint = <&apss_funnel_in6>;
2467 compatible = "arm,coresight-etm4x", "arm,primecell";
2473 clock-names = "apb_pclk";
2474 arm,coresight-loses-context-with-cpu;
2475 qcom,skip-power-up;
2477 out-ports {
2480 remote-endpoint = <&apss_funnel_in7>;
2487 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2491 clock-names = "apb_pclk";
2493 out-ports {
2496 remote-endpoint = <&apss_merge_funnel_in>;
2501 in-ports {
2502 #address-cells = <1>;
2503 #size-cells = <0>;
2508 remote-endpoint = <&etm0_out>;
2515 remote-endpoint = <&etm1_out>;
2522 remote-endpoint = <&etm2_out>;
2529 remote-endpoint = <&etm3_out>;
2536 remote-endpoint = <&etm4_out>;
2543 remote-endpoint = <&etm5_out>;
2550 remote-endpoint = <&etm6_out>;
2557 remote-endpoint = <&etm7_out>;
2564 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2568 clock-names = "apb_pclk";
2570 out-ports {
2573 remote-endpoint = <&funnel1_in4>;
2578 in-ports {
2581 remote-endpoint = <&apss_funnel_out>;
2588 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2594 interrupt-names = "hc_irq", "pwr_irq";
2599 clock-names = "core", "iface", "xo";
2603 interconnect-names = "sdhc-ddr","cpu-sdhc";
2604 power-domains = <&rpmhpd SC7180_CX>;
2605 operating-points-v2 = <&sdhc2_opp_table>;
2607 bus-width = <4>;
2611 sdhc2_opp_table: sdhc2-opp-table {
2612 compatible = "operating-points-v2";
2614 opp-100000000 {
2615 opp-hz = /bits/ 64 <100000000>;
2616 required-opps = <&rpmhpd_opp_low_svs>;
2617 opp-peak-kBps = <1800000 600000>;
2618 opp-avg-kBps = <100000 0>;
2621 opp-202000000 {
2622 opp-hz = /bits/ 64 <202000000>;
2623 required-opps = <&rpmhpd_opp_nom>;
2624 opp-peak-kBps = <5400000 1600000>;
2625 opp-avg-kBps = <200000 0>;
2630 qspi_opp_table: qspi-opp-table {
2631 compatible = "operating-points-v2";
2633 opp-75000000 {
2634 opp-hz = /bits/ 64 <75000000>;
2635 required-opps = <&rpmhpd_opp_low_svs>;
2638 opp-150000000 {
2639 opp-hz = /bits/ 64 <150000000>;
2640 required-opps = <&rpmhpd_opp_svs>;
2643 opp-300000000 {
2644 opp-hz = /bits/ 64 <300000000>;
2645 required-opps = <&rpmhpd_opp_nom>;
2650 compatible = "qcom,qspi-v1";
2652 #address-cells = <1>;
2653 #size-cells = <0>;
2657 clock-names = "iface", "core";
2660 interconnect-names = "qspi-config";
2661 power-domains = <&rpmhpd SC7180_CX>;
2662 operating-points-v2 = <&qspi_opp_table>;
2667 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2670 #phy-cells = <0>;
2673 clock-names = "cfg_ahb", "ref";
2676 nvmem-cells = <&qusb2p_hstx_trim>;
2679 usb_1_qmpphy: phy-wrapper@88e9000 {
2680 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2685 #address-cells = <2>;
2686 #size-cells = <2>;
2693 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2697 reset-names = "phy", "common";
2699 usb_1_ssphy: usb3-phy@88e9200 {
2706 #clock-cells = <0>;
2707 #phy-cells = <0>;
2709 clock-names = "pipe0";
2710 clock-output-names = "usb3_phy_pipe_clk_src";
2713 dp_phy: dp-phy@88ea200 {
2719 #clock-cells = <1>;
2720 #phy-cells = <0>;
2725 compatible = "qcom,sc7180-dc-noc";
2727 #interconnect-cells = <2>;
2728 qcom,bcm-voters = <&apps_bcm_voter>;
2731 system-cache-controller@9200000 {
2732 compatible = "qcom,sc7180-llcc";
2734 reg-names = "llcc_base", "llcc_broadcast_base";
2739 compatible = "qcom,sc7180-gem-noc";
2741 #interconnect-cells = <2>;
2742 qcom,bcm-voters = <&apps_bcm_voter>;
2746 compatible = "qcom,sc7180-npu-noc";
2748 #interconnect-cells = <2>;
2749 qcom,bcm-voters = <&apps_bcm_voter>;
2753 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
2756 #address-cells = <2>;
2757 #size-cells = <2>;
2759 dma-ranges;
2766 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2769 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2771 assigned-clock-rates = <19200000>, <150000000>;
2773 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2777 interrupt-names = "hs_phy_irq", "ss_phy_irq",
2780 power-domains = <&gcc USB30_PRIM_GDSC>;
2786 interconnect-names = "usb-ddr", "apps-usb";
2796 phy-names = "usb2-phy", "usb3-phy";
2797 maximum-speed = "super-speed";
2801 venus: video-codec@aa00000 {
2802 compatible = "qcom,sc7180-venus";
2805 power-domains = <&videocc VENUS_GDSC>,
2808 power-domain-names = "venus", "vcodec0", "cx";
2809 operating-points-v2 = <&venus_opp_table>;
2815 clock-names = "core", "iface", "bus",
2818 memory-region = <&venus_mem>;
2821 interconnect-names = "video-mem", "cpu-cfg";
2823 video-decoder {
2824 compatible = "venus-decoder";
2827 video-encoder {
2828 compatible = "venus-encoder";
2831 venus_opp_table: venus-opp-table {
2832 compatible = "operating-points-v2";
2834 opp-150000000 {
2835 opp-hz = /bits/ 64 <150000000>;
2836 required-opps = <&rpmhpd_opp_low_svs>;
2839 opp-270000000 {
2840 opp-hz = /bits/ 64 <270000000>;
2841 required-opps = <&rpmhpd_opp_svs>;
2844 opp-340000000 {
2845 opp-hz = /bits/ 64 <340000000>;
2846 required-opps = <&rpmhpd_opp_svs_l1>;
2849 opp-434000000 {
2850 opp-hz = /bits/ 64 <434000000>;
2851 required-opps = <&rpmhpd_opp_nom>;
2854 opp-500000097 {
2855 opp-hz = /bits/ 64 <500000097>;
2856 required-opps = <&rpmhpd_opp_turbo>;
2861 videocc: clock-controller@ab00000 {
2862 compatible = "qcom,sc7180-videocc";
2865 clock-names = "bi_tcxo";
2866 #clock-cells = <1>;
2867 #reset-cells = <1>;
2868 #power-domain-cells = <1>;
2872 compatible = "qcom,sc7180-camnoc-virt";
2874 #interconnect-cells = <2>;
2875 qcom,bcm-voters = <&apps_bcm_voter>;
2878 camcc: clock-controller@ad00000 {
2879 compatible = "qcom,sc7180-camcc";
2884 clock-names = "bi_tcxo", "iface", "xo";
2885 #clock-cells = <1>;
2886 #reset-cells = <1>;
2887 #power-domain-cells = <1>;
2891 compatible = "qcom,sc7180-mdss";
2893 reg-names = "mdss";
2895 power-domains = <&dispcc MDSS_GDSC>;
2900 clock-names = "iface", "ahb", "core";
2902 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2903 assigned-clock-rates = <300000000>;
2906 interrupt-controller;
2907 #interrupt-cells = <1>;
2910 interconnect-names = "mdp0-mem";
2914 #address-cells = <2>;
2915 #size-cells = <2>;
2921 compatible = "qcom,sc7180-dpu";
2924 reg-names = "mdp", "vbif";
2932 clock-names = "bus", "iface", "rot", "lut", "core",
2934 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2938 assigned-clock-rates = <300000000>,
2942 operating-points-v2 = <&mdp_opp_table>;
2943 power-domains = <&rpmhpd SC7180_CX>;
2945 interrupt-parent = <&mdss>;
2951 #address-cells = <1>;
2952 #size-cells = <0>;
2957 remote-endpoint = <&dsi0_in>;
2964 remote-endpoint = <&dp_in>;
2969 mdp_opp_table: mdp-opp-table {
2970 compatible = "operating-points-v2";
2972 opp-200000000 {
2973 opp-hz = /bits/ 64 <200000000>;
2974 required-opps = <&rpmhpd_opp_low_svs>;
2977 opp-300000000 {
2978 opp-hz = /bits/ 64 <300000000>;
2979 required-opps = <&rpmhpd_opp_svs>;
2982 opp-345000000 {
2983 opp-hz = /bits/ 64 <345000000>;
2984 required-opps = <&rpmhpd_opp_svs_l1>;
2987 opp-460000000 {
2988 opp-hz = /bits/ 64 <460000000>;
2989 required-opps = <&rpmhpd_opp_nom>;
2996 compatible = "qcom,mdss-dsi-ctrl";
2998 reg-names = "dsi_ctrl";
3000 interrupt-parent = <&mdss>;
3009 clock-names = "byte",
3016 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3017 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
3019 operating-points-v2 = <&dsi_opp_table>;
3020 power-domains = <&rpmhpd SC7180_CX>;
3023 phy-names = "dsi";
3025 #address-cells = <1>;
3026 #size-cells = <0>;
3031 #address-cells = <1>;
3032 #size-cells = <0>;
3037 remote-endpoint = <&dpu_intf1_out>;
3048 dsi_opp_table: dsi-opp-table {
3049 compatible = "operating-points-v2";
3051 opp-187500000 {
3052 opp-hz = /bits/ 64 <187500000>;
3053 required-opps = <&rpmhpd_opp_low_svs>;
3056 opp-300000000 {
3057 opp-hz = /bits/ 64 <300000000>;
3058 required-opps = <&rpmhpd_opp_svs>;
3061 opp-358000000 {
3062 opp-hz = /bits/ 64 <358000000>;
3063 required-opps = <&rpmhpd_opp_svs_l1>;
3068 dsi_phy: dsi-phy@ae94400 {
3069 compatible = "qcom,dsi-phy-10nm";
3073 reg-names = "dsi_phy",
3077 #clock-cells = <1>;
3078 #phy-cells = <0>;
3082 clock-names = "iface", "ref";
3087 mdss_dp: displayport-controller@ae90000 {
3088 compatible = "qcom,sc7180-dp";
3093 interrupt-parent = <&mdss>;
3101 clock-names = "core_iface", "core_aux", "ctrl_link",
3103 #clock-cells = <1>;
3104 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3106 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3108 phy-names = "dp";
3110 operating-points-v2 = <&dp_opp_table>;
3111 power-domains = <&rpmhpd SC7180_CX>;
3113 #sound-dai-cells = <0>;
3116 #address-cells = <1>;
3117 #size-cells = <0>;
3121 remote-endpoint = <&dpu_intf0_out>;
3131 dp_opp_table: opp-table {
3132 compatible = "operating-points-v2";
3134 opp-160000000 {
3135 opp-hz = /bits/ 64 <160000000>;
3136 required-opps = <&rpmhpd_opp_low_svs>;
3139 opp-270000000 {
3140 opp-hz = /bits/ 64 <270000000>;
3141 required-opps = <&rpmhpd_opp_svs>;
3144 opp-540000000 {
3145 opp-hz = /bits/ 64 <540000000>;
3146 required-opps = <&rpmhpd_opp_svs_l1>;
3149 opp-810000000 {
3150 opp-hz = /bits/ 64 <810000000>;
3151 required-opps = <&rpmhpd_opp_nom>;
3157 dispcc: clock-controller@af00000 {
3158 compatible = "qcom,sc7180-dispcc";
3166 clock-names = "bi_tcxo",
3172 #clock-cells = <1>;
3173 #reset-cells = <1>;
3174 #power-domain-cells = <1>;
3177 pdc: interrupt-controller@b220000 {
3178 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3180 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3181 #interrupt-cells = <2>;
3182 interrupt-parent = <&intc>;
3183 interrupt-controller;
3186 pdc_reset: reset-controller@b2e0000 {
3187 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3189 #reset-cells = <1>;
3192 tsens0: thermal-sensor@c263000 {
3193 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3199 interrupt-names = "uplow","critical";
3200 #thermal-sensor-cells = <1>;
3203 tsens1: thermal-sensor@c265000 {
3204 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3210 interrupt-names = "uplow","critical";
3211 #thermal-sensor-cells = <1>;
3214 aoss_reset: reset-controller@c2a0000 {
3215 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3217 #reset-cells = <1>;
3220 aoss_qmp: power-controller@c300000 {
3221 compatible = "qcom,sc7180-aoss-qmp";
3226 #clock-cells = <0>;
3227 #power-domain-cells = <1>;
3231 compatible = "qcom,spmi-pmic-arb";
3237 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3238 interrupt-names = "periph_irq";
3239 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3242 #address-cells = <1>;
3243 #size-cells = <1>;
3244 interrupt-controller;
3245 #interrupt-cells = <4>;
3246 cell-index = <0>;
3250 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3252 #iommu-cells = <2>;
3253 #global-interrupts = <1>;
3337 intc: interrupt-controller@17a00000 {
3338 compatible = "arm,gic-v3";
3339 #address-cells = <2>;
3340 #size-cells = <2>;
3342 #interrupt-cells = <3>;
3343 interrupt-controller;
3348 msi-controller@17a40000 {
3349 compatible = "arm,gic-v3-its";
3350 msi-controller;
3351 #msi-cells = <1>;
3358 compatible = "qcom,sc7180-apss-shared";
3360 #mbox-cells = <1>;
3364 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3371 #address-cells = <2>;
3372 #size-cells = <2>;
3374 compatible = "arm,armv7-timer-mem";
3378 frame-number = <0>;
3386 frame-number = <1>;
3393 frame-number = <2>;
3400 frame-number = <3>;
3407 frame-number = <4>;
3414 frame-number = <5>;
3421 frame-number = <6>;
3429 compatible = "qcom,rpmh-rsc";
3433 reg-names = "drv-0", "drv-1", "drv-2";
3437 qcom,tcs-offset = <0xd00>;
3438 qcom,drv-id = <2>;
3439 qcom,tcs-config = <ACTIVE_TCS 2>,
3444 rpmhcc: clock-controller {
3445 compatible = "qcom,sc7180-rpmh-clk";
3447 clock-names = "xo";
3448 #clock-cells = <1>;
3451 rpmhpd: power-controller {
3452 compatible = "qcom,sc7180-rpmhpd";
3453 #power-domain-cells = <1>;
3454 operating-points-v2 = <&rpmhpd_opp_table>;
3456 rpmhpd_opp_table: opp-table {
3457 compatible = "operating-points-v2";
3460 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3464 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3468 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3472 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3476 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3480 opp-level = <224>;
3484 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3488 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3492 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3496 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3500 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3506 compatible = "qcom,bcm-voter";
3511 compatible = "qcom,sc7180-osm-l3";
3515 clock-names = "xo", "alternate";
3517 #interconnect-cells = <1>;
3521 compatible = "qcom,cpufreq-hw";
3523 reg-names = "freq-domain0", "freq-domain1";
3526 clock-names = "xo", "alternate";
3528 #freq-domain-cells = <1>;
3532 compatible = "qcom,wcn3990-wifi";
3534 reg-names = "membase";
3549 memory-region = <&wlan_mem>;
3550 qcom,msa-fixed-perm;
3554 lpasscc: clock-controller@62d00000 {
3555 compatible = "qcom,sc7180-lpasscorecc";
3558 reg-names = "lpass_core_cc", "lpass_audio_cc";
3561 clock-names = "iface", "bi_tcxo";
3562 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3563 #clock-cells = <1>;
3564 #power-domain-cells = <1>;
3568 compatible = "qcom,sc7180-lpass-cpu";
3571 reg-names = "lpass-hdmiif", "lpass-lpaif";
3577 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3588 clock-names = "pcnoc-sway-clk", "audio-core",
3589 "mclk0", "pcnoc-mport-clk",
3590 "mi2s-bit-clk0", "mi2s-bit-clk1";
3593 #sound-dai-cells = <1>;
3594 #address-cells = <1>;
3595 #size-cells = <0>;
3599 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
3602 lpass_hm: clock-controller@63000000 {
3603 compatible = "qcom,sc7180-lpasshm";
3607 clock-names = "iface", "bi_tcxo";
3608 #clock-cells = <1>;
3609 #power-domain-cells = <1>;
3613 thermal-zones {
3614 cpu0_thermal: cpu0-thermal {
3615 polling-delay-passive = <250>;
3616 polling-delay = <0>;
3618 thermal-sensors = <&tsens0 1>;
3619 sustainable-power = <768>;
3622 cpu0_alert0: trip-point0 {
3628 cpu0_alert1: trip-point1 {
3641 cooling-maps {
3644 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3653 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3663 cpu1_thermal: cpu1-thermal {
3664 polling-delay-passive = <250>;
3665 polling-delay = <0>;
3667 thermal-sensors = <&tsens0 2>;
3668 sustainable-power = <768>;
3671 cpu1_alert0: trip-point0 {
3677 cpu1_alert1: trip-point1 {
3690 cooling-maps {
3693 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3702 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3712 cpu2_thermal: cpu2-thermal {
3713 polling-delay-passive = <250>;
3714 polling-delay = <0>;
3716 thermal-sensors = <&tsens0 3>;
3717 sustainable-power = <768>;
3720 cpu2_alert0: trip-point0 {
3726 cpu2_alert1: trip-point1 {
3739 cooling-maps {
3742 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3751 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3761 cpu3_thermal: cpu3-thermal {
3762 polling-delay-passive = <250>;
3763 polling-delay = <0>;
3765 thermal-sensors = <&tsens0 4>;
3766 sustainable-power = <768>;
3769 cpu3_alert0: trip-point0 {
3775 cpu3_alert1: trip-point1 {
3788 cooling-maps {
3791 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3800 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3810 cpu4_thermal: cpu4-thermal {
3811 polling-delay-passive = <250>;
3812 polling-delay = <0>;
3814 thermal-sensors = <&tsens0 5>;
3815 sustainable-power = <768>;
3818 cpu4_alert0: trip-point0 {
3824 cpu4_alert1: trip-point1 {
3837 cooling-maps {
3840 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3849 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3859 cpu5_thermal: cpu5-thermal {
3860 polling-delay-passive = <250>;
3861 polling-delay = <0>;
3863 thermal-sensors = <&tsens0 6>;
3864 sustainable-power = <768>;
3867 cpu5_alert0: trip-point0 {
3873 cpu5_alert1: trip-point1 {
3886 cooling-maps {
3889 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3898 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3908 cpu6_thermal: cpu6-thermal {
3909 polling-delay-passive = <250>;
3910 polling-delay = <0>;
3912 thermal-sensors = <&tsens0 9>;
3913 sustainable-power = <1202>;
3916 cpu6_alert0: trip-point0 {
3922 cpu6_alert1: trip-point1 {
3935 cooling-maps {
3938 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3943 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3949 cpu7_thermal: cpu7-thermal {
3950 polling-delay-passive = <250>;
3951 polling-delay = <0>;
3953 thermal-sensors = <&tsens0 10>;
3954 sustainable-power = <1202>;
3957 cpu7_alert0: trip-point0 {
3963 cpu7_alert1: trip-point1 {
3976 cooling-maps {
3979 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3984 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3990 cpu8_thermal: cpu8-thermal {
3991 polling-delay-passive = <250>;
3992 polling-delay = <0>;
3994 thermal-sensors = <&tsens0 11>;
3995 sustainable-power = <1202>;
3998 cpu8_alert0: trip-point0 {
4004 cpu8_alert1: trip-point1 {
4017 cooling-maps {
4020 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4025 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4031 cpu9_thermal: cpu9-thermal {
4032 polling-delay-passive = <250>;
4033 polling-delay = <0>;
4035 thermal-sensors = <&tsens0 12>;
4036 sustainable-power = <1202>;
4039 cpu9_alert0: trip-point0 {
4045 cpu9_alert1: trip-point1 {
4058 cooling-maps {
4061 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4066 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4072 aoss0-thermal {
4073 polling-delay-passive = <250>;
4074 polling-delay = <0>;
4076 thermal-sensors = <&tsens0 0>;
4079 aoss0_alert0: trip-point0 {
4093 cpuss0-thermal {
4094 polling-delay-passive = <250>;
4095 polling-delay = <0>;
4097 thermal-sensors = <&tsens0 7>;
4100 cpuss0_alert0: trip-point0 {
4113 cpuss1-thermal {
4114 polling-delay-passive = <250>;
4115 polling-delay = <0>;
4117 thermal-sensors = <&tsens0 8>;
4120 cpuss1_alert0: trip-point0 {
4133 gpuss0-thermal {
4134 polling-delay-passive = <250>;
4135 polling-delay = <0>;
4137 thermal-sensors = <&tsens0 13>;
4140 gpuss0_alert0: trip-point0 {
4153 cooling-maps {
4156 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4161 gpuss1-thermal {
4162 polling-delay-passive = <250>;
4163 polling-delay = <0>;
4165 thermal-sensors = <&tsens0 14>;
4168 gpuss1_alert0: trip-point0 {
4181 cooling-maps {
4184 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4189 aoss1-thermal {
4190 polling-delay-passive = <250>;
4191 polling-delay = <0>;
4193 thermal-sensors = <&tsens1 0>;
4196 aoss1_alert0: trip-point0 {
4210 cwlan-thermal {
4211 polling-delay-passive = <250>;
4212 polling-delay = <0>;
4214 thermal-sensors = <&tsens1 1>;
4217 cwlan_alert0: trip-point0 {
4231 audio-thermal {
4232 polling-delay-passive = <250>;
4233 polling-delay = <0>;
4235 thermal-sensors = <&tsens1 2>;
4238 audio_alert0: trip-point0 {
4252 ddr-thermal {
4253 polling-delay-passive = <250>;
4254 polling-delay = <0>;
4256 thermal-sensors = <&tsens1 3>;
4259 ddr_alert0: trip-point0 {
4273 q6-hvx-thermal {
4274 polling-delay-passive = <250>;
4275 polling-delay = <0>;
4277 thermal-sensors = <&tsens1 4>;
4280 q6_hvx_alert0: trip-point0 {
4294 camera-thermal {
4295 polling-delay-passive = <250>;
4296 polling-delay = <0>;
4298 thermal-sensors = <&tsens1 5>;
4301 camera_alert0: trip-point0 {
4315 mdm-core-thermal {
4316 polling-delay-passive = <250>;
4317 polling-delay = <0>;
4319 thermal-sensors = <&tsens1 6>;
4322 mdm_alert0: trip-point0 {
4336 mdm-dsp-thermal {
4337 polling-delay-passive = <250>;
4338 polling-delay = <0>;
4340 thermal-sensors = <&tsens1 7>;
4343 mdm_dsp_alert0: trip-point0 {
4357 npu-thermal {
4358 polling-delay-passive = <250>;
4359 polling-delay = <0>;
4361 thermal-sensors = <&tsens1 8>;
4364 npu_alert0: trip-point0 {
4378 video-thermal {
4379 polling-delay-passive = <250>;
4380 polling-delay = <0>;
4382 thermal-sensors = <&tsens1 9>;
4385 video_alert0: trip-point0 {
4401 compatible = "arm,armv8-timer";