Lines Matching refs:gcc
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
852 gcc: clock-controller@100000 { label
853 compatible = "qcom,gcc-msm8998";
962 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
963 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
964 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
965 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
966 <&gcc GCC_PCIE_0_AUX_CLK>;
969 power-domains = <&gcc PCIE_0_GDSC>;
982 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
983 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
984 <&gcc GCC_PCIE_CLKREF_CLK>;
987 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
997 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1011 power-domains = <&gcc UFS_GDSC>;
1025 <&gcc GCC_UFS_AXI_CLK>,
1026 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1027 <&gcc GCC_UFS_AHB_CLK>,
1028 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1030 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1031 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1032 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1043 resets = <&gcc GCC_UFS_BCR>;
1059 <&gcc GCC_UFS_CLKREF_CLK>,
1060 <&gcc GCC_UFS_PHY_AUX_CLK>;
1378 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1379 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1380 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1381 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1382 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1383 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1392 resets = <&gcc GCC_MSS_RESTART>;
1427 <&gcc GPLL0_OUT_MAIN>;
1947 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
1948 <&gcc GCC_USB30_MASTER_CLK>,
1949 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
1950 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1951 <&gcc GCC_USB30_SLEEP_CLK>;
1955 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1956 <&gcc GCC_USB30_MASTER_CLK>;
1963 power-domains = <&gcc USB_30_GDSC>;
1965 resets = <&gcc GCC_USB_30_BCR>;
1989 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
1990 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1991 <&gcc GCC_USB3_CLKREF_CLK>;
1994 resets = <&gcc GCC_USB3_PHY_BCR>,
1995 <&gcc GCC_USB3PHY_PHY_BCR>;
2005 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2017 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2018 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2021 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2036 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2037 <&gcc GCC_SDCC2_APPS_CLK>,
2047 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2060 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2061 <&gcc GCC_BLSP1_AHB_CLK>;
2075 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2076 <&gcc GCC_BLSP1_AHB_CLK>;
2095 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2096 <&gcc GCC_BLSP1_AHB_CLK>;
2115 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2116 <&gcc GCC_BLSP1_AHB_CLK>;
2135 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2136 <&gcc GCC_BLSP1_AHB_CLK>;
2155 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2156 <&gcc GCC_BLSP1_AHB_CLK>;
2175 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2176 <&gcc GCC_BLSP1_AHB_CLK>;
2194 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2207 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2208 <&gcc GCC_BLSP2_AHB_CLK>;
2218 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2219 <&gcc GCC_BLSP2_AHB_CLK>;
2238 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2239 <&gcc GCC_BLSP2_AHB_CLK>;
2258 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2259 <&gcc GCC_BLSP2_AHB_CLK>;
2278 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2279 <&gcc GCC_BLSP2_AHB_CLK>;
2298 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2299 <&gcc GCC_BLSP2_AHB_CLK>;
2318 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2319 <&gcc GCC_BLSP2_AHB_CLK>;