Lines Matching full:mmcc
7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
718 mmcc: clock-controller@8c0000 { label
719 compatible = "qcom,mmcc-msm8996";
724 assigned-clocks = <&mmcc MMPLL9_PLL>,
725 <&mmcc MMPLL1_PLL>,
726 <&mmcc MMPLL3_PLL>,
727 <&mmcc MMPLL4_PLL>,
728 <&mmcc MMPLL5_PLL>;
746 power-domains = <&mmcc MDSS_GDSC>;
752 clocks = <&mmcc MDSS_AHB_CLK>;
769 clocks = <&mmcc MDSS_AHB_CLK>,
770 <&mmcc MDSS_AXI_CLK>,
771 <&mmcc MDSS_MDP_CLK>,
772 <&mmcc SMMU_MDP_AXI_CLK>,
773 <&mmcc MDSS_VSYNC_CLK>;
782 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
783 <&mmcc MDSS_VSYNC_CLK>;
815 clocks = <&mmcc MDSS_MDP_CLK>,
816 <&mmcc MDSS_BYTE0_CLK>,
817 <&mmcc MDSS_AHB_CLK>,
818 <&mmcc MDSS_AXI_CLK>,
819 <&mmcc MMSS_MISC_AHB_CLK>,
820 <&mmcc MDSS_PCLK0_CLK>,
821 <&mmcc MDSS_ESC0_CLK>;
868 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
885 clocks = <&mmcc MDSS_MDP_CLK>,
886 <&mmcc MDSS_AHB_CLK>,
887 <&mmcc MDSS_HDMI_CLK>,
888 <&mmcc MDSS_HDMI_AHB_CLK>,
889 <&mmcc MDSS_EXTPCLK_CLK>;
932 clocks = <&mmcc MDSS_AHB_CLK>,
950 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
951 <&mmcc GPU_AHB_CLK>,
952 <&mmcc GPU_GX_RBBMTIMER_CLK>,
962 power-domains = <&mmcc GPU_GX_GDSC>;
1807 power-domains = <&mmcc VFE0_GDSC>,
1808 <&mmcc VFE1_GDSC>;
1809 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1810 <&mmcc CAMSS_ISPIF_AHB_CLK>,
1811 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1812 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1813 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1814 <&mmcc CAMSS_CSI0_AHB_CLK>,
1815 <&mmcc CAMSS_CSI0_CLK>,
1816 <&mmcc CAMSS_CSI0PHY_CLK>,
1817 <&mmcc CAMSS_CSI0PIX_CLK>,
1818 <&mmcc CAMSS_CSI0RDI_CLK>,
1819 <&mmcc CAMSS_CSI1_AHB_CLK>,
1820 <&mmcc CAMSS_CSI1_CLK>,
1821 <&mmcc CAMSS_CSI1PHY_CLK>,
1822 <&mmcc CAMSS_CSI1PIX_CLK>,
1823 <&mmcc CAMSS_CSI1RDI_CLK>,
1824 <&mmcc CAMSS_CSI2_AHB_CLK>,
1825 <&mmcc CAMSS_CSI2_CLK>,
1826 <&mmcc CAMSS_CSI2PHY_CLK>,
1827 <&mmcc CAMSS_CSI2PIX_CLK>,
1828 <&mmcc CAMSS_CSI2RDI_CLK>,
1829 <&mmcc CAMSS_CSI3_AHB_CLK>,
1830 <&mmcc CAMSS_CSI3_CLK>,
1831 <&mmcc CAMSS_CSI3PHY_CLK>,
1832 <&mmcc CAMSS_CSI3PIX_CLK>,
1833 <&mmcc CAMSS_CSI3RDI_CLK>,
1834 <&mmcc CAMSS_AHB_CLK>,
1835 <&mmcc CAMSS_VFE0_CLK>,
1836 <&mmcc CAMSS_CSI_VFE0_CLK>,
1837 <&mmcc CAMSS_VFE0_AHB_CLK>,
1838 <&mmcc CAMSS_VFE0_STREAM_CLK>,
1839 <&mmcc CAMSS_VFE1_CLK>,
1840 <&mmcc CAMSS_CSI_VFE1_CLK>,
1841 <&mmcc CAMSS_VFE1_AHB_CLK>,
1842 <&mmcc CAMSS_VFE1_STREAM_CLK>,
1843 <&mmcc CAMSS_VFE_AHB_CLK>,
1844 <&mmcc CAMSS_VFE_AXI_CLK>;
1898 power-domains = <&mmcc CAMSS_GDSC>;
1899 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1900 <&mmcc CAMSS_CCI_AHB_CLK>,
1901 <&mmcc CAMSS_CCI_CLK>,
1902 <&mmcc CAMSS_AHB_CLK>;
1907 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1908 <&mmcc CAMSS_CCI_CLK>;
1939 clocks = <&mmcc GPU_AHB_CLK>,
1943 power-domains = <&mmcc GPU_GDSC>;
1950 power-domains = <&mmcc VENUS_GDSC>;
1951 clocks = <&mmcc VIDEO_CORE_CLK>,
1952 <&mmcc VIDEO_AHB_CLK>,
1953 <&mmcc VIDEO_AXI_CLK>,
1954 <&mmcc VIDEO_MAXI_CLK>;
1981 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
1983 power-domains = <&mmcc VENUS_CORE0_GDSC>;
1988 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
1990 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2003 clocks = <&mmcc SMMU_MDP_AHB_CLK>,
2004 <&mmcc SMMU_MDP_AXI_CLK>;
2007 power-domains = <&mmcc MDSS_GDSC>;
2022 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2023 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2024 <&mmcc SMMU_VIDEO_AXI_CLK>;
2038 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2039 clocks = <&mmcc SMMU_VFE_AHB_CLK>,
2040 <&mmcc SMMU_VFE_AXI_CLK>;