Lines Matching +full:gcc +full:- +full:msm8996
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/soc/qcom,apr.h>
11 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&intc>;
16 #address-cells = <2>;
17 #size-cells = <2>;
22 xo_board: xo-board {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <19200000>;
26 clock-output-names = "xo_board";
29 sleep_clk: sleep-clk {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <32764>;
33 clock-output-names = "sleep_clk";
38 #address-cells = <2>;
39 #size-cells = <0>;
45 enable-method = "psci";
46 cpu-idle-states = <&CPU_SLEEP_0>;
47 capacity-dmips-mhz = <1024>;
49 operating-points-v2 = <&cluster0_opp>;
50 #cooling-cells = <2>;
51 next-level-cache = <&L2_0>;
52 L2_0: l2-cache {
54 cache-level = <2>;
62 enable-method = "psci";
63 cpu-idle-states = <&CPU_SLEEP_0>;
64 capacity-dmips-mhz = <1024>;
66 operating-points-v2 = <&cluster0_opp>;
67 #cooling-cells = <2>;
68 next-level-cache = <&L2_0>;
75 enable-method = "psci";
76 cpu-idle-states = <&CPU_SLEEP_0>;
77 capacity-dmips-mhz = <1024>;
79 operating-points-v2 = <&cluster1_opp>;
80 #cooling-cells = <2>;
81 next-level-cache = <&L2_1>;
82 L2_1: l2-cache {
84 cache-level = <2>;
92 enable-method = "psci";
93 cpu-idle-states = <&CPU_SLEEP_0>;
94 capacity-dmips-mhz = <1024>;
96 operating-points-v2 = <&cluster1_opp>;
97 #cooling-cells = <2>;
98 next-level-cache = <&L2_1>;
101 cpu-map {
123 idle-states {
124 entry-method = "psci";
126 CPU_SLEEP_0: cpu-sleep-0 {
127 compatible = "arm,idle-state";
128 idle-state-name = "standalone-power-collapse";
129 arm,psci-suspend-param = <0x00000004>;
130 entry-latency-us = <130>;
131 exit-latency-us = <80>;
132 min-residency-us = <300>;
138 compatible = "operating-points-v2-kryo-cpu";
139 nvmem-cells = <&speedbin_efuse>;
140 opp-shared;
143 opp-307200000 {
144 opp-hz = /bits/ 64 <307200000>;
145 opp-supported-hw = <0x77>;
146 clock-latency-ns = <200000>;
148 opp-422400000 {
149 opp-hz = /bits/ 64 <422400000>;
150 opp-supported-hw = <0x77>;
151 clock-latency-ns = <200000>;
153 opp-480000000 {
154 opp-hz = /bits/ 64 <480000000>;
155 opp-supported-hw = <0x77>;
156 clock-latency-ns = <200000>;
158 opp-556800000 {
159 opp-hz = /bits/ 64 <556800000>;
160 opp-supported-hw = <0x77>;
161 clock-latency-ns = <200000>;
163 opp-652800000 {
164 opp-hz = /bits/ 64 <652800000>;
165 opp-supported-hw = <0x77>;
166 clock-latency-ns = <200000>;
168 opp-729600000 {
169 opp-hz = /bits/ 64 <729600000>;
170 opp-supported-hw = <0x77>;
171 clock-latency-ns = <200000>;
173 opp-844800000 {
174 opp-hz = /bits/ 64 <844800000>;
175 opp-supported-hw = <0x77>;
176 clock-latency-ns = <200000>;
178 opp-960000000 {
179 opp-hz = /bits/ 64 <960000000>;
180 opp-supported-hw = <0x77>;
181 clock-latency-ns = <200000>;
183 opp-1036800000 {
184 opp-hz = /bits/ 64 <1036800000>;
185 opp-supported-hw = <0x77>;
186 clock-latency-ns = <200000>;
188 opp-1113600000 {
189 opp-hz = /bits/ 64 <1113600000>;
190 opp-supported-hw = <0x77>;
191 clock-latency-ns = <200000>;
193 opp-1190400000 {
194 opp-hz = /bits/ 64 <1190400000>;
195 opp-supported-hw = <0x77>;
196 clock-latency-ns = <200000>;
198 opp-1228800000 {
199 opp-hz = /bits/ 64 <1228800000>;
200 opp-supported-hw = <0x77>;
201 clock-latency-ns = <200000>;
203 opp-1324800000 {
204 opp-hz = /bits/ 64 <1324800000>;
205 opp-supported-hw = <0x77>;
206 clock-latency-ns = <200000>;
208 opp-1401600000 {
209 opp-hz = /bits/ 64 <1401600000>;
210 opp-supported-hw = <0x77>;
211 clock-latency-ns = <200000>;
213 opp-1478400000 {
214 opp-hz = /bits/ 64 <1478400000>;
215 opp-supported-hw = <0x77>;
216 clock-latency-ns = <200000>;
218 opp-1593600000 {
219 opp-hz = /bits/ 64 <1593600000>;
220 opp-supported-hw = <0x77>;
221 clock-latency-ns = <200000>;
226 compatible = "operating-points-v2-kryo-cpu";
227 nvmem-cells = <&speedbin_efuse>;
228 opp-shared;
231 opp-307200000 {
232 opp-hz = /bits/ 64 <307200000>;
233 opp-supported-hw = <0x77>;
234 clock-latency-ns = <200000>;
236 opp-403200000 {
237 opp-hz = /bits/ 64 <403200000>;
238 opp-supported-hw = <0x77>;
239 clock-latency-ns = <200000>;
241 opp-480000000 {
242 opp-hz = /bits/ 64 <480000000>;
243 opp-supported-hw = <0x77>;
244 clock-latency-ns = <200000>;
246 opp-556800000 {
247 opp-hz = /bits/ 64 <556800000>;
248 opp-supported-hw = <0x77>;
249 clock-latency-ns = <200000>;
251 opp-652800000 {
252 opp-hz = /bits/ 64 <652800000>;
253 opp-supported-hw = <0x77>;
254 clock-latency-ns = <200000>;
256 opp-729600000 {
257 opp-hz = /bits/ 64 <729600000>;
258 opp-supported-hw = <0x77>;
259 clock-latency-ns = <200000>;
261 opp-806400000 {
262 opp-hz = /bits/ 64 <806400000>;
263 opp-supported-hw = <0x77>;
264 clock-latency-ns = <200000>;
266 opp-883200000 {
267 opp-hz = /bits/ 64 <883200000>;
268 opp-supported-hw = <0x77>;
269 clock-latency-ns = <200000>;
271 opp-940800000 {
272 opp-hz = /bits/ 64 <940800000>;
273 opp-supported-hw = <0x77>;
274 clock-latency-ns = <200000>;
276 opp-1036800000 {
277 opp-hz = /bits/ 64 <1036800000>;
278 opp-supported-hw = <0x77>;
279 clock-latency-ns = <200000>;
281 opp-1113600000 {
282 opp-hz = /bits/ 64 <1113600000>;
283 opp-supported-hw = <0x77>;
284 clock-latency-ns = <200000>;
286 opp-1190400000 {
287 opp-hz = /bits/ 64 <1190400000>;
288 opp-supported-hw = <0x77>;
289 clock-latency-ns = <200000>;
291 opp-1248000000 {
292 opp-hz = /bits/ 64 <1248000000>;
293 opp-supported-hw = <0x77>;
294 clock-latency-ns = <200000>;
296 opp-1324800000 {
297 opp-hz = /bits/ 64 <1324800000>;
298 opp-supported-hw = <0x77>;
299 clock-latency-ns = <200000>;
301 opp-1401600000 {
302 opp-hz = /bits/ 64 <1401600000>;
303 opp-supported-hw = <0x77>;
304 clock-latency-ns = <200000>;
306 opp-1478400000 {
307 opp-hz = /bits/ 64 <1478400000>;
308 opp-supported-hw = <0x77>;
309 clock-latency-ns = <200000>;
311 opp-1555200000 {
312 opp-hz = /bits/ 64 <1555200000>;
313 opp-supported-hw = <0x77>;
314 clock-latency-ns = <200000>;
316 opp-1632000000 {
317 opp-hz = /bits/ 64 <1632000000>;
318 opp-supported-hw = <0x77>;
319 clock-latency-ns = <200000>;
321 opp-1708800000 {
322 opp-hz = /bits/ 64 <1708800000>;
323 opp-supported-hw = <0x77>;
324 clock-latency-ns = <200000>;
326 opp-1785600000 {
327 opp-hz = /bits/ 64 <1785600000>;
328 opp-supported-hw = <0x77>;
329 clock-latency-ns = <200000>;
331 opp-1824000000 {
332 opp-hz = /bits/ 64 <1824000000>;
333 opp-supported-hw = <0x77>;
334 clock-latency-ns = <200000>;
336 opp-1920000000 {
337 opp-hz = /bits/ 64 <1920000000>;
338 opp-supported-hw = <0x77>;
339 clock-latency-ns = <200000>;
341 opp-1996800000 {
342 opp-hz = /bits/ 64 <1996800000>;
343 opp-supported-hw = <0x77>;
344 clock-latency-ns = <200000>;
346 opp-2073600000 {
347 opp-hz = /bits/ 64 <2073600000>;
348 opp-supported-hw = <0x77>;
349 clock-latency-ns = <200000>;
351 opp-2150400000 {
352 opp-hz = /bits/ 64 <2150400000>;
353 opp-supported-hw = <0x77>;
354 clock-latency-ns = <200000>;
360 compatible = "qcom,scm-msm8996";
361 qcom,dload-mode = <&tcsr 0x13000>;
366 compatible = "qcom,tcsr-mutex";
368 #hwlock-cells = <1>;
378 compatible = "arm,psci-1.0";
382 reserved-memory {
383 #address-cells = <2>;
384 #size-cells = <2>;
389 no-map;
394 no-map;
399 no-map;
404 no-map;
409 no-map;
412 smem_mem: smem-mem@86000000 {
414 no-map;
419 no-map;
424 no-map;
428 compatible = "qcom,rmtfs-mem";
431 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
432 no-map;
434 qcom,client-id = <1>;
439 compatible = "shared-dma-pool";
441 no-map;
445 rpm-glink {
446 compatible = "qcom,glink-rpm";
450 qcom,rpm-msg-ram = <&rpm_msg_ram>;
454 rpm_requests: rpm-requests {
455 compatible = "qcom,rpm-msm8996";
456 qcom,glink-channels = "rpm_requests";
459 compatible = "qcom,rpmcc-msm8996";
460 #clock-cells = <1>;
463 rpmpd: power-controller {
464 compatible = "qcom,msm8996-rpmpd";
465 #power-domain-cells = <1>;
466 operating-points-v2 = <&rpmpd_opp_table>;
468 rpmpd_opp_table: opp-table {
469 compatible = "operating-points-v2";
472 opp-level = <1>;
476 opp-level = <2>;
480 opp-level = <3>;
484 opp-level = <4>;
488 opp-level = <5>;
492 opp-level = <6>;
501 memory-region = <&smem_mem>;
505 smp2p-adsp {
513 qcom,local-pid = <0>;
514 qcom,remote-pid = <2>;
516 smp2p_adsp_out: master-kernel {
517 qcom,entry-name = "master-kernel";
518 #qcom,smem-state-cells = <1>;
521 smp2p_adsp_in: slave-kernel {
522 qcom,entry-name = "slave-kernel";
524 interrupt-controller;
525 #interrupt-cells = <2>;
529 smp2p-modem {
537 qcom,local-pid = <0>;
538 qcom,remote-pid = <1>;
540 modem_smp2p_out: master-kernel {
541 qcom,entry-name = "master-kernel";
542 #qcom,smem-state-cells = <1>;
545 modem_smp2p_in: slave-kernel {
546 qcom,entry-name = "slave-kernel";
548 interrupt-controller;
549 #interrupt-cells = <2>;
553 smp2p-slpi {
561 qcom,local-pid = <0>;
562 qcom,remote-pid = <3>;
564 smp2p_slpi_in: slave-kernel {
565 qcom,entry-name = "slave-kernel";
566 interrupt-controller;
567 #interrupt-cells = <2>;
570 smp2p_slpi_out: master-kernel {
571 qcom,entry-name = "master-kernel";
572 #qcom,smem-state-cells = <1>;
577 #address-cells = <1>;
578 #size-cells = <1>;
580 compatible = "simple-bus";
583 compatible = "qcom,msm8996-qmp-pcie-phy";
585 #clock-cells = <1>;
586 #address-cells = <1>;
587 #size-cells = <1>;
590 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
591 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
592 <&gcc GCC_PCIE_CLKREF_CLK>;
593 clock-names = "aux", "cfg_ahb", "ref";
595 resets = <&gcc GCC_PCIE_PHY_BCR>,
596 <&gcc GCC_PCIE_PHY_COM_BCR>,
597 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
598 reset-names = "phy", "common", "cfg";
605 #phy-cells = <0>;
607 clock-output-names = "pcie_0_pipe_clk_src";
608 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
609 clock-names = "pipe0";
610 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
611 reset-names = "lane0";
618 #phy-cells = <0>;
620 clock-output-names = "pcie_1_pipe_clk_src";
621 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
622 clock-names = "pipe1";
623 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
624 reset-names = "lane1";
631 #phy-cells = <0>;
633 clock-output-names = "pcie_2_pipe_clk_src";
634 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
635 clock-names = "pipe2";
636 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
637 reset-names = "lane2";
642 compatible = "qcom,rpm-msg-ram";
649 #address-cells = <1>;
650 #size-cells = <1>;
669 compatible = "qcom,prng-ee";
671 clocks = <&gcc GCC_PRNG_AHB_CLK>;
672 clock-names = "core";
675 gcc: clock-controller@300000 { label
676 compatible = "qcom,gcc-msm8996";
677 #clock-cells = <1>;
678 #reset-cells = <1>;
679 #power-domain-cells = <1>;
683 clock-names = "cxo2";
686 tsens0: thermal-sensor@4a9000 {
687 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
693 interrupt-names = "uplow", "critical";
694 #thermal-sensor-cells = <1>;
697 tsens1: thermal-sensor@4ad000 {
698 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
704 interrupt-names = "uplow", "critical";
705 #thermal-sensor-cells = <1>;
714 compatible = "qcom,tcsr-msm8996", "syscon";
718 mmcc: clock-controller@8c0000 {
719 compatible = "qcom,mmcc-msm8996";
720 #clock-cells = <1>;
721 #reset-cells = <1>;
722 #power-domain-cells = <1>;
724 assigned-clocks = <&mmcc MMPLL9_PLL>,
729 assigned-clock-rates = <624000000>,
742 reg-names = "mdss_phys",
746 power-domains = <&mmcc MDSS_GDSC>;
749 interrupt-controller;
750 #interrupt-cells = <1>;
753 clock-names = "iface";
755 #address-cells = <1>;
756 #size-cells = <1>;
764 reg-names = "mdp_phys";
766 interrupt-parent = <&mdss>;
774 clock-names = "iface",
782 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
784 assigned-clock-rates = <300000000>,
788 #address-cells = <1>;
789 #size-cells = <0>;
794 remote-endpoint = <&hdmi_in>;
801 remote-endpoint = <&dsi0_in>;
808 compatible = "qcom,mdss-dsi-ctrl";
810 reg-names = "dsi_ctrl";
812 interrupt-parent = <&mdss>;
822 clock-names = "mdp_core",
831 phy-names = "dsi";
834 #address-cells = <1>;
835 #size-cells = <0>;
838 #address-cells = <1>;
839 #size-cells = <0>;
844 remote-endpoint = <&mdp5_intf1_out>;
856 dsi0_phy: dsi-phy@994400 {
857 compatible = "qcom,dsi-phy-14nm";
861 reg-names = "dsi_phy",
865 #clock-cells = <1>;
866 #phy-cells = <0>;
869 clock-names = "iface", "ref";
873 hdmi: hdmi-tx@9a0000 {
874 compatible = "qcom,hdmi-tx-8996";
878 reg-names = "core_physical",
882 interrupt-parent = <&mdss>;
890 clock-names =
898 phy-names = "hdmi_phy";
899 #sound-dai-cells = <1>;
904 #address-cells = <1>;
905 #size-cells = <0>;
910 remote-endpoint = <&mdp5_intf3_out>;
916 hdmi_phy: hdmi-phy@9a0600 {
917 #phy-cells = <0>;
918 compatible = "qcom,hdmi-phy-8996";
925 reg-names = "hdmi_pll",
933 <&gcc GCC_HDMI_CLKREF_CLK>;
934 clock-names = "iface",
942 compatible = "qcom,adreno-530.2", "qcom,adreno";
943 #stream-id-cells = <16>;
946 reg-names = "kgsl_3d0_reg_memory";
953 <&gcc GCC_BIMC_GFX_CLK>,
954 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
956 clock-names = "core",
962 power-domains = <&mmcc GPU_GX_GDSC>;
965 nvmem-cells = <&speedbin_efuse>;
966 nvmem-cell-names = "speed_bin";
968 qcom,gpu-quirk-two-pass-use-wfi;
969 qcom,gpu-quirk-fault-detect-mask;
971 operating-points-v2 = <&gpu_opp_table>;
975 #cooling-cells = <2>;
977 gpu_opp_table: opp-table {
978 compatible ="operating-points-v2";
985 opp-624000000 {
986 opp-hz = /bits/ 64 <624000000>;
987 opp-supported-hw = <0x01>;
989 opp-560000000 {
990 opp-hz = /bits/ 64 <560000000>;
991 opp-supported-hw = <0x01>;
993 opp-510000000 {
994 opp-hz = /bits/ 64 <510000000>;
995 opp-supported-hw = <0xFF>;
997 opp-401800000 {
998 opp-hz = /bits/ 64 <401800000>;
999 opp-supported-hw = <0xFF>;
1001 opp-315000000 {
1002 opp-hz = /bits/ 64 <315000000>;
1003 opp-supported-hw = <0xFF>;
1005 opp-214000000 {
1006 opp-hz = /bits/ 64 <214000000>;
1007 opp-supported-hw = <0xFF>;
1009 opp-133000000 {
1010 opp-hz = /bits/ 64 <133000000>;
1011 opp-supported-hw = <0xFF>;
1015 zap-shader {
1016 memory-region = <&zap_shader_region>;
1021 compatible = "qcom,msm8996-pinctrl";
1024 gpio-controller;
1025 gpio-ranges = <&tlmm 0 0 150>;
1026 #gpio-cells = <2>;
1027 interrupt-controller;
1028 #interrupt-cells = <2>;
1030 blsp1_spi1_default: blsp1-spi1-default {
1034 drive-strength = <12>;
1035 bias-disable;
1041 drive-strength = <16>;
1042 bias-disable;
1043 output-high;
1047 blsp1_spi1_sleep: blsp1-spi1-sleep {
1050 drive-strength = <2>;
1051 bias-pull-down;
1054 blsp2_uart2_2pins_default: blsp2-uart1-2pins {
1057 drive-strength = <16>;
1058 bias-disable;
1061 blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
1064 drive-strength = <2>;
1065 bias-disable;
1068 blsp2_i2c2_default: blsp2-i2c2 {
1071 drive-strength = <16>;
1072 bias-disable;
1075 blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1078 drive-strength = <2>;
1079 bias-disable;
1082 cci0_default: cci0-default {
1085 drive-strength = <16>;
1086 bias-disable;
1090 camera_rear_default: camera-rear-default {
1094 drive-strength = <16>;
1095 bias-disable;
1101 drive-strength = <16>;
1102 bias-disable;
1108 drive-strength = <16>;
1109 bias-disable;
1113 cci1_default: cci1-default {
1116 drive-strength = <16>;
1117 bias-disable;
1121 camera_board_default: camera-board-default {
1125 drive-strength = <16>;
1126 bias-disable;
1132 drive-strength = <16>;
1133 bias-disable;
1139 drive-strength = <16>;
1140 bias-disable;
1145 camera_front_default: camera-front-default {
1149 drive-strength = <16>;
1150 bias-disable;
1156 drive-strength = <16>;
1157 bias-disable;
1163 drive-strength = <16>;
1164 bias-disable;
1168 pcie0_state_on: pcie0-state-on {
1172 drive-strength = <2>;
1173 bias-pull-down;
1179 drive-strength = <2>;
1180 bias-pull-up;
1186 drive-strength = <2>;
1187 bias-pull-up;
1191 pcie0_state_off: pcie0-state-off {
1195 drive-strength = <2>;
1196 bias-pull-down;
1202 drive-strength = <2>;
1203 bias-disable;
1209 drive-strength = <2>;
1210 bias-disable;
1214 blsp1_i2c3_default: blsp1-i2c2-default {
1217 drive-strength = <16>;
1218 bias-disable = <0>;
1221 blsp1_i2c3_sleep: blsp1-i2c2-sleep {
1224 drive-strength = <2>;
1225 bias-disable = <0>;
1228 blsp2_uart3_4pins_default: blsp2-uart2-4pins {
1231 drive-strength = <16>;
1232 bias-disable;
1235 blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
1238 drive-strength = <2>;
1239 bias-disable;
1242 wcd_intr_default: wcd-intr-default{
1245 drive-strength = <2>;
1246 bias-pull-down;
1247 input-enable;
1250 blsp2_i2c1_default: blsp2-i2c1 {
1253 drive-strength = <16>;
1254 bias-disable;
1257 blsp2_i2c1_sleep: blsp2-i2c0-sleep {
1260 drive-strength = <2>;
1261 bias-disable;
1264 blsp2_i2c5_default: blsp2-i2c5 {
1267 drive-strength = <2>;
1268 bias-disable;
1273 cdc_reset_active: cdc-reset-active {
1276 drive-strength = <16>;
1277 bias-pull-down;
1278 output-high;
1281 cdc_reset_sleep: cdc-reset-sleep {
1284 drive-strength = <16>;
1285 bias-disable;
1286 output-low;
1289 blsp2_spi6_default: blsp2-spi5-default {
1293 drive-strength = <12>;
1294 bias-disable;
1300 drive-strength = <16>;
1301 bias-disable;
1302 output-high;
1306 blsp2_spi6_sleep: blsp2-spi5-sleep {
1309 drive-strength = <2>;
1310 bias-pull-down;
1313 blsp2_i2c6_default: blsp2-i2c6 {
1316 drive-strength = <16>;
1317 bias-disable;
1320 blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1323 drive-strength = <2>;
1324 bias-disable;
1327 pcie1_state_on: pcie1-state-on {
1331 drive-strength = <2>;
1332 bias-pull-down;
1338 drive-strength = <2>;
1339 bias-pull-up;
1345 drive-strength = <2>;
1346 bias-pull-down;
1350 pcie1_state_off: pcie1-state-off {
1355 drive-strength = <2>;
1356 bias-disable;
1362 drive-strength = <2>;
1363 bias-disable;
1367 pcie2_state_on: pcie2-state-on {
1371 drive-strength = <2>;
1372 bias-pull-down;
1378 drive-strength = <2>;
1379 bias-pull-up;
1385 drive-strength = <2>;
1386 bias-pull-down;
1390 pcie2_state_off: pcie2-state-off {
1395 drive-strength = <2>;
1396 bias-disable;
1402 drive-strength = <2>;
1403 bias-disable;
1407 sdc1_state_on: sdc1-state-on {
1410 bias-disable;
1411 drive-strength = <16>;
1416 bias-pull-up;
1417 drive-strength = <10>;
1422 bias-pull-up;
1423 drive-strength = <10>;
1428 bias-pull-down;
1432 sdc1_state_off: sdc1-state-off {
1435 bias-disable;
1436 drive-strength = <2>;
1441 bias-pull-up;
1442 drive-strength = <2>;
1447 bias-pull-up;
1448 drive-strength = <2>;
1453 bias-pull-down;
1457 sdc2_state_on: sdc2-clk-on {
1460 bias-disable;
1461 drive-strength = <16>;
1466 bias-pull-up;
1467 drive-strength = <10>;
1472 bias-pull-up;
1473 drive-strength = <10>;
1477 sdc2_state_off: sdc2-clk-off {
1480 bias-disable;
1481 drive-strength = <2>;
1486 bias-pull-up;
1487 drive-strength = <2>;
1492 bias-pull-up;
1493 drive-strength = <2>;
1499 compatible = "qcom,spmi-pmic-arb";
1505 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1506 interrupt-names = "periph_irq";
1510 #address-cells = <2>;
1511 #size-cells = <0>;
1512 interrupt-controller;
1513 #interrupt-cells = <4>;
1517 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1518 compatible = "simple-pm-bus";
1519 #address-cells = <1>;
1520 #size-cells = <1>;
1524 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1526 power-domains = <&gcc PCIE0_GDSC>;
1527 bus-range = <0x00 0xff>;
1528 num-lanes = <1>;
1534 reg-names = "parf", "dbi", "elbi","config";
1537 phy-names = "pciephy";
1539 #address-cells = <3>;
1540 #size-cells = <2>;
1547 interrupt-names = "msi";
1548 #interrupt-cells = <1>;
1549 interrupt-map-mask = <0 0 0 0x7>;
1550 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1555 pinctrl-names = "default", "sleep";
1556 pinctrl-0 = <&pcie0_state_on>;
1557 pinctrl-1 = <&pcie0_state_off>;
1559 linux,pci-domain = <0>;
1561 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1562 <&gcc GCC_PCIE_0_AUX_CLK>,
1563 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1564 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1565 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1567 clock-names = "pipe",
1576 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1577 power-domains = <&gcc PCIE1_GDSC>;
1578 bus-range = <0x00 0xff>;
1579 num-lanes = <1>;
1588 reg-names = "parf", "dbi", "elbi","config";
1591 phy-names = "pciephy";
1593 #address-cells = <3>;
1594 #size-cells = <2>;
1601 interrupt-names = "msi";
1602 #interrupt-cells = <1>;
1603 interrupt-map-mask = <0 0 0 0x7>;
1604 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1609 pinctrl-names = "default", "sleep";
1610 pinctrl-0 = <&pcie1_state_on>;
1611 pinctrl-1 = <&pcie1_state_off>;
1613 linux,pci-domain = <1>;
1615 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1616 <&gcc GCC_PCIE_1_AUX_CLK>,
1617 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1618 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1619 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1621 clock-names = "pipe",
1629 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1630 power-domains = <&gcc PCIE2_GDSC>;
1631 bus-range = <0x00 0xff>;
1632 num-lanes = <1>;
1639 reg-names = "parf", "dbi", "elbi","config";
1642 phy-names = "pciephy";
1644 #address-cells = <3>;
1645 #size-cells = <2>;
1652 interrupt-names = "msi";
1653 #interrupt-cells = <1>;
1654 interrupt-map-mask = <0 0 0 0x7>;
1655 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1660 pinctrl-names = "default", "sleep";
1661 pinctrl-0 = <&pcie2_state_on>;
1662 pinctrl-1 = <&pcie2_state_off>;
1664 linux,pci-domain = <2>;
1665 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1666 <&gcc GCC_PCIE_2_AUX_CLK>,
1667 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1668 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1669 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1671 clock-names = "pipe",
1685 phy-names = "ufsphy";
1687 power-domains = <&gcc UFS_GDSC>;
1689 clock-names =
1702 <&gcc UFS_AXI_CLK_SRC>,
1703 <&gcc GCC_UFS_AXI_CLK>,
1704 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
1705 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
1706 <&gcc GCC_UFS_AHB_CLK>,
1707 <&gcc UFS_ICE_CORE_CLK_SRC>,
1708 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1709 <&gcc GCC_UFS_ICE_CORE_CLK>,
1711 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1712 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
1713 freq-table-hz =
1726 lanes-per-direction = <1>;
1727 #reset-cells = <1>;
1736 compatible = "qcom,msm8996-qmp-ufs-phy";
1738 #address-cells = <1>;
1739 #size-cells = <1>;
1742 clocks = <&gcc GCC_UFS_CLKREF_CLK>;
1743 clock-names = "ref";
1746 reset-names = "ufsphy";
1753 #phy-cells = <0>;
1758 compatible = "qcom,msm8996-camss";
1773 reg-names = "csiphy0",
1797 interrupt-names = "csiphy0",
1807 power-domains = <&mmcc VFE0_GDSC>,
1845 clock-names = "top_ahb",
1887 #address-cells = <1>;
1888 #size-cells = <0>;
1893 compatible = "qcom,msm8996-cci";
1894 #address-cells = <1>;
1895 #size-cells = <0>;
1898 power-domains = <&mmcc CAMSS_GDSC>;
1903 clock-names = "camss_top_ahb",
1907 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1909 assigned-clock-rates = <80000000>, <37500000>;
1910 pinctrl-names = "default";
1911 pinctrl-0 = <&cci0_default &cci1_default>;
1914 cci_i2c0: i2c-bus@0 {
1916 clock-frequency = <400000>;
1917 #address-cells = <1>;
1918 #size-cells = <0>;
1921 cci_i2c1: i2c-bus@1 {
1923 clock-frequency = <400000>;
1924 #address-cells = <1>;
1925 #size-cells = <0>;
1930 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1933 #global-interrupts = <1>;
1937 #iommu-cells = <1>;
1940 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1941 clock-names = "iface", "bus";
1943 power-domains = <&mmcc GPU_GDSC>;
1946 venus: video-codec@c00000 {
1947 compatible = "qcom,msm8996-venus";
1950 power-domains = <&mmcc VENUS_GDSC>;
1955 clock-names = "core", "iface", "bus", "mbus";
1976 memory-region = <&venus_region>;
1979 video-decoder {
1980 compatible = "venus-decoder";
1982 clock-names = "core";
1983 power-domains = <&mmcc VENUS_CORE0_GDSC>;
1986 video-encoder {
1987 compatible = "venus-encoder";
1989 clock-names = "core";
1990 power-domains = <&mmcc VENUS_CORE1_GDSC>;
1995 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1998 #global-interrupts = <1>;
2002 #iommu-cells = <1>;
2005 clock-names = "iface", "bus";
2007 power-domains = <&mmcc MDSS_GDSC>;
2011 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2013 #global-interrupts = <1>;
2022 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2025 clock-names = "iface", "bus";
2026 #iommu-cells = <1>;
2031 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2034 #global-interrupts = <1>;
2038 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2041 clock-names = "iface",
2043 #iommu-cells = <1>;
2047 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2049 #iommu-cells = <1>;
2050 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2052 #global-interrupts = <1>;
2067 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2068 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
2069 clock-names = "iface", "bus";
2073 compatible = "arm,coresight-stm", "arm,primecell";
2076 reg-names = "stm-base", "stm-stimulus-base";
2079 clock-names = "apb_pclk", "atclk";
2081 out-ports {
2084 remote-endpoint =
2092 compatible = "arm,coresight-tpiu", "arm,primecell";
2096 clock-names = "apb_pclk", "atclk";
2098 in-ports {
2101 remote-endpoint =
2109 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2113 clock-names = "apb_pclk", "atclk";
2115 in-ports {
2116 #address-cells = <1>;
2117 #size-cells = <0>;
2122 remote-endpoint =
2128 out-ports {
2131 remote-endpoint =
2139 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2143 clock-names = "apb_pclk", "atclk";
2145 in-ports {
2146 #address-cells = <1>;
2147 #size-cells = <0>;
2152 remote-endpoint =
2158 out-ports {
2161 remote-endpoint =
2169 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2173 clock-names = "apb_pclk", "atclk";
2176 out-ports {
2179 remote-endpoint =
2187 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2191 clock-names = "apb_pclk", "atclk";
2193 in-ports {
2194 #address-cells = <1>;
2195 #size-cells = <0>;
2200 remote-endpoint =
2208 remote-endpoint =
2216 remote-endpoint =
2222 out-ports {
2225 remote-endpoint =
2233 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2237 clock-names = "apb_pclk", "atclk";
2239 in-ports {
2242 remote-endpoint =
2248 out-ports {
2249 #address-cells = <1>;
2250 #size-cells = <0>;
2255 remote-endpoint =
2263 remote-endpoint =
2271 compatible = "arm,coresight-tmc", "arm,primecell";
2275 clock-names = "apb_pclk", "atclk";
2277 in-ports {
2280 remote-endpoint =
2286 out-ports {
2289 remote-endpoint =
2297 compatible = "arm,coresight-tmc", "arm,primecell";
2301 clock-names = "apb_pclk", "atclk";
2302 arm,scatter-gather;
2304 in-ports {
2307 remote-endpoint =
2315 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2319 clock-names = "apb_pclk";
2325 compatible = "arm,coresight-etm4x", "arm,primecell";
2329 clock-names = "apb_pclk", "atclk";
2333 out-ports {
2336 remote-endpoint =
2344 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2348 clock-names = "apb_pclk";
2354 compatible = "arm,coresight-etm4x", "arm,primecell";
2358 clock-names = "apb_pclk", "atclk";
2362 out-ports {
2365 remote-endpoint =
2373 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2377 clock-names = "apb_pclk", "atclk";
2379 in-ports {
2380 #address-cells = <1>;
2381 #size-cells = <0>;
2386 remote-endpoint = <&etm0_out>;
2393 remote-endpoint = <&etm1_out>;
2398 out-ports {
2401 remote-endpoint =
2409 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2413 clock-names = "apb_pclk";
2419 compatible = "arm,coresight-etm4x", "arm,primecell";
2423 clock-names = "apb_pclk", "atclk";
2427 out-ports {
2430 remote-endpoint =
2438 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2442 clock-names = "apb_pclk";
2448 compatible = "arm,coresight-etm4x", "arm,primecell";
2452 clock-names = "apb_pclk", "atclk";
2456 out-ports {
2459 remote-endpoint =
2467 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2471 clock-names = "apb_pclk", "atclk";
2473 in-ports {
2474 #address-cells = <1>;
2475 #size-cells = <0>;
2480 remote-endpoint = <&etm2_out>;
2487 remote-endpoint = <&etm3_out>;
2492 out-ports {
2495 remote-endpoint =
2503 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2507 clock-names = "apb_pclk", "atclk";
2509 in-ports {
2510 #address-cells = <1>;
2511 #size-cells = <0>;
2516 remote-endpoint =
2524 remote-endpoint =
2530 out-ports {
2533 remote-endpoint =
2540 kryocc: clock-controller@6400000 {
2541 compatible = "qcom,msm8996-apcc";
2544 clock-names = "xo";
2547 #clock-cells = <1>;
2551 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2553 #address-cells = <1>;
2554 #size-cells = <1>;
2559 interrupt-names = "hs_phy_irq", "ss_phy_irq";
2561 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
2562 <&gcc GCC_USB30_MASTER_CLK>,
2563 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
2564 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2565 <&gcc GCC_USB30_SLEEP_CLK>,
2566 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2568 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2569 <&gcc GCC_USB30_MASTER_CLK>;
2570 assigned-clock-rates = <19200000>, <120000000>;
2572 power-domains = <&gcc USB30_GDSC>;
2580 phy-names = "usb2-phy", "usb3-phy";
2587 compatible = "qcom,msm8996-qmp-usb3-phy";
2589 #clock-cells = <1>;
2590 #address-cells = <1>;
2591 #size-cells = <1>;
2594 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2595 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2596 <&gcc GCC_USB3_CLKREF_CLK>;
2597 clock-names = "aux", "cfg_ahb", "ref";
2599 resets = <&gcc GCC_USB3_PHY_BCR>,
2600 <&gcc GCC_USB3PHY_PHY_BCR>;
2601 reset-names = "phy", "common";
2608 #phy-cells = <0>;
2610 clock-output-names = "usb3_phy_pipe_clk_src";
2611 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2612 clock-names = "pipe0";
2617 compatible = "qcom,msm8996-qusb2-phy";
2619 #phy-cells = <0>;
2621 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2622 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2623 clock-names = "cfg_ahb", "ref";
2625 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2626 nvmem-cells = <&qusb2p_hstx_trim>;
2631 compatible = "qcom,msm8996-qusb2-phy";
2633 #phy-cells = <0>;
2635 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2636 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
2637 clock-names = "cfg_ahb", "ref";
2639 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2640 nvmem-cells = <&qusb2s_hstx_trim>;
2645 compatible = "qcom,sdhci-msm-v4";
2647 reg-names = "hc_mem", "core_mem";
2651 interrupt-names = "hc_irq", "pwr_irq";
2653 clock-names = "iface", "core", "xo";
2654 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2655 <&gcc GCC_SDCC1_APPS_CLK>,
2658 pinctrl-names = "default", "sleep";
2659 pinctrl-0 = <&sdc1_state_on>;
2660 pinctrl-1 = <&sdc1_state_off>;
2662 bus-width = <8>;
2663 non-removable;
2668 compatible = "qcom,sdhci-msm-v4";
2670 reg-names = "hc_mem", "core_mem";
2674 interrupt-names = "hc_irq", "pwr_irq";
2676 clock-names = "iface", "core", "xo";
2677 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2678 <&gcc GCC_SDCC2_APPS_CLK>,
2681 pinctrl-names = "default", "sleep";
2682 pinctrl-0 = <&sdc2_state_on>;
2683 pinctrl-1 = <&sdc2_state_off>;
2685 bus-width = <4>;
2690 compatible = "qcom,bam-v1.7.0";
2693 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2694 clock-names = "bam_clk";
2695 qcom,controlled-remotely;
2696 #dma-cells = <1>;
2701 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2704 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
2705 <&gcc GCC_BLSP1_AHB_CLK>;
2706 clock-names = "core", "iface";
2708 dma-names = "tx", "rx";
2713 compatible = "qcom,spi-qup-v2.2.1";
2716 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2717 <&gcc GCC_BLSP1_AHB_CLK>;
2718 clock-names = "core", "iface";
2719 pinctrl-names = "default", "sleep";
2720 pinctrl-0 = <&blsp1_spi1_default>;
2721 pinctrl-1 = <&blsp1_spi1_sleep>;
2723 dma-names = "tx", "rx";
2724 #address-cells = <1>;
2725 #size-cells = <0>;
2730 compatible = "qcom,i2c-qup-v2.2.1";
2733 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
2734 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
2735 clock-names = "iface", "core";
2736 pinctrl-names = "default", "sleep";
2737 pinctrl-0 = <&blsp1_i2c3_default>;
2738 pinctrl-1 = <&blsp1_i2c3_sleep>;
2740 dma-names = "tx", "rx";
2741 #address-cells = <1>;
2742 #size-cells = <0>;
2747 compatible = "qcom,bam-v1.7.0";
2750 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2751 clock-names = "bam_clk";
2752 qcom,controlled-remotely;
2753 #dma-cells = <1>;
2758 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2761 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2762 <&gcc GCC_BLSP2_AHB_CLK>;
2763 clock-names = "core", "iface";
2768 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2771 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
2772 <&gcc GCC_BLSP2_AHB_CLK>;
2773 clock-names = "core", "iface";
2778 compatible = "qcom,i2c-qup-v2.2.1";
2781 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2782 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
2783 clock-names = "iface", "core";
2784 pinctrl-names = "default", "sleep";
2785 pinctrl-0 = <&blsp2_i2c1_default>;
2786 pinctrl-1 = <&blsp2_i2c1_sleep>;
2788 dma-names = "tx", "rx";
2789 #address-cells = <1>;
2790 #size-cells = <0>;
2795 compatible = "qcom,i2c-qup-v2.2.1";
2798 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2799 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
2800 clock-names = "iface", "core";
2801 pinctrl-names = "default", "sleep";
2802 pinctrl-0 = <&blsp2_i2c2_default>;
2803 pinctrl-1 = <&blsp2_i2c2_sleep>;
2805 dma-names = "tx", "rx";
2806 #address-cells = <1>;
2807 #size-cells = <0>;
2812 compatible = "qcom,i2c-qup-v2.2.1";
2815 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2816 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
2817 clock-names = "iface", "core";
2818 pinctrl-names = "default";
2819 pinctrl-0 = <&blsp2_i2c5_default>;
2821 dma-names = "tx", "rx";
2822 #address-cells = <1>;
2823 #size-cells = <0>;
2828 compatible = "qcom,i2c-qup-v2.2.1";
2831 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2832 <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
2833 clock-names = "iface", "core";
2834 pinctrl-names = "default", "sleep";
2835 pinctrl-0 = <&blsp2_i2c6_default>;
2836 pinctrl-1 = <&blsp2_i2c6_sleep>;
2838 dma-names = "tx", "rx";
2839 #address-cells = <1>;
2840 #size-cells = <0>;
2845 compatible = "qcom,spi-qup-v2.2.1";
2848 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2849 <&gcc GCC_BLSP2_AHB_CLK>;
2850 clock-names = "core", "iface";
2851 pinctrl-names = "default", "sleep";
2852 pinctrl-0 = <&blsp2_spi6_default>;
2853 pinctrl-1 = <&blsp2_spi6_sleep>;
2855 dma-names = "tx", "rx";
2856 #address-cells = <1>;
2857 #size-cells = <0>;
2862 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2864 #address-cells = <1>;
2865 #size-cells = <1>;
2868 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
2869 <&gcc GCC_USB20_MASTER_CLK>,
2870 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
2871 <&gcc GCC_USB20_SLEEP_CLK>,
2872 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2874 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
2875 <&gcc GCC_USB20_MASTER_CLK>;
2876 assigned-clock-rates = <19200000>, <60000000>;
2878 power-domains = <&gcc USB30_GDSC>;
2879 qcom,select-utmi-as-pipe-clk;
2887 phy-names = "usb2-phy";
2888 maximum-speed = "high-speed";
2894 slimbam: dma-controller@9184000 {
2895 compatible = "qcom,bam-v1.7.0";
2896 qcom,controlled-remotely;
2898 num-channels = <31>;
2900 #dma-cells = <1>;
2902 qcom,num-ees = <2>;
2906 compatible = "qcom,slim-ngd-v1.5.0";
2908 reg-names = "ctrl";
2912 dma-names = "rx", "tx", "tx2", "rx2";
2913 #address-cells = <1>;
2914 #size-cells = <0>;
2917 #address-cells = <1>;
2918 #size-cells = <1>;
2920 tasha_ifd: tas-ifd {
2926 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
2927 pinctrl-names = "default";
2932 interrupt-parent = <&tlmm>;
2935 interrupt-names = "intr1", "intr2";
2936 interrupt-controller;
2937 #interrupt-cells = <1>;
2938 reset-gpios = <&tlmm 64 0>;
2940 slim-ifc-dev = <&tasha_ifd>;
2942 #sound-dai-cells = <1>;
2948 compatible = "qcom,msm8996-adsp-pil";
2951 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
2956 interrupt-names = "wdog", "fatal", "ready",
2957 "handover", "stop-ack";
2960 clock-names = "xo";
2962 memory-region = <&adsp_region>;
2964 qcom,smem-states = <&smp2p_adsp_out 0>;
2965 qcom,smem-state-names = "stop";
2967 power-domains = <&rpmpd MSM8996_VDDCX>;
2968 power-domain-names = "cx";
2972 smd-edge {
2977 qcom,smd-edge = <1>;
2978 qcom,remote-pid = <2>;
2979 #address-cells = <1>;
2980 #size-cells = <0>;
2982 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
2983 compatible = "qcom,apr-v2";
2984 qcom,smd-channels = "apr_audio_svc";
2985 qcom,apr-domain = <APR_DOMAIN_ADSP>;
2986 #address-cells = <1>;
2987 #size-cells = <0>;
2998 compatible = "qcom,q6afe-dais";
2999 #address-cells = <1>;
3000 #size-cells = <0>;
3001 #sound-dai-cells = <1>;
3012 compatible = "qcom,q6asm-dais";
3013 #address-cells = <1>;
3014 #size-cells = <0>;
3015 #sound-dai-cells = <1>;
3024 compatible = "qcom,q6adm-routing";
3025 #sound-dai-cells = <0>;
3034 compatible = "qcom,msm8996-apcs-hmss-global";
3037 #mbox-cells = <1>;
3041 #address-cells = <1>;
3042 #size-cells = <1>;
3044 compatible = "arm,armv7-timer-mem";
3046 clock-frequency = <19200000>;
3049 frame-number = <0>;
3057 frame-number = <1>;
3064 frame-number = <2>;
3071 frame-number = <3>;
3078 frame-number = <4>;
3085 frame-number = <5>;
3092 frame-number = <6>;
3104 intc: interrupt-controller@9bc0000 {
3105 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3106 #interrupt-cells = <3>;
3107 interrupt-controller;
3108 #redistributor-regions = <1>;
3109 redistributor-stride = <0x0 0x40000>;
3119 thermal-zones {
3120 cpu0-thermal {
3121 polling-delay-passive = <250>;
3122 polling-delay = <1000>;
3124 thermal-sensors = <&tsens0 3>;
3127 cpu0_alert0: trip-point0 {
3141 cpu1-thermal {
3142 polling-delay-passive = <250>;
3143 polling-delay = <1000>;
3145 thermal-sensors = <&tsens0 5>;
3148 cpu1_alert0: trip-point0 {
3162 cpu2-thermal {
3163 polling-delay-passive = <250>;
3164 polling-delay = <1000>;
3166 thermal-sensors = <&tsens0 8>;
3169 cpu2_alert0: trip-point0 {
3183 cpu3-thermal {
3184 polling-delay-passive = <250>;
3185 polling-delay = <1000>;
3187 thermal-sensors = <&tsens0 10>;
3190 cpu3_alert0: trip-point0 {
3204 gpu-thermal-top {
3205 polling-delay-passive = <250>;
3206 polling-delay = <1000>;
3208 thermal-sensors = <&tsens1 6>;
3211 gpu1_alert0: trip-point0 {
3218 cooling-maps {
3221 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3226 gpu-thermal-bottom {
3227 polling-delay-passive = <250>;
3228 polling-delay = <1000>;
3230 thermal-sensors = <&tsens1 7>;
3233 gpu2_alert0: trip-point0 {
3240 cooling-maps {
3243 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3248 m4m-thermal {
3249 polling-delay-passive = <250>;
3250 polling-delay = <1000>;
3252 thermal-sensors = <&tsens0 1>;
3255 m4m_alert0: trip-point0 {
3263 l3-or-venus-thermal {
3264 polling-delay-passive = <250>;
3265 polling-delay = <1000>;
3267 thermal-sensors = <&tsens0 2>;
3270 l3_or_venus_alert0: trip-point0 {
3278 cluster0-l2-thermal {
3279 polling-delay-passive = <250>;
3280 polling-delay = <1000>;
3282 thermal-sensors = <&tsens0 7>;
3285 cluster0_l2_alert0: trip-point0 {
3293 cluster1-l2-thermal {
3294 polling-delay-passive = <250>;
3295 polling-delay = <1000>;
3297 thermal-sensors = <&tsens0 12>;
3300 cluster1_l2_alert0: trip-point0 {
3308 camera-thermal {
3309 polling-delay-passive = <250>;
3310 polling-delay = <1000>;
3312 thermal-sensors = <&tsens1 1>;
3315 camera_alert0: trip-point0 {
3323 q6-dsp-thermal {
3324 polling-delay-passive = <250>;
3325 polling-delay = <1000>;
3327 thermal-sensors = <&tsens1 2>;
3330 q6_dsp_alert0: trip-point0 {
3338 mem-thermal {
3339 polling-delay-passive = <250>;
3340 polling-delay = <1000>;
3342 thermal-sensors = <&tsens1 3>;
3345 mem_alert0: trip-point0 {
3353 modemtx-thermal {
3354 polling-delay-passive = <250>;
3355 polling-delay = <1000>;
3357 thermal-sensors = <&tsens1 4>;
3360 modemtx_alert0: trip-point0 {
3370 compatible = "arm,armv8-timer";