Lines Matching full:gcc
6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
590 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
591 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
592 <&gcc GCC_PCIE_CLKREF_CLK>;
595 resets = <&gcc GCC_PCIE_PHY_BCR>,
596 <&gcc GCC_PCIE_PHY_COM_BCR>,
597 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
608 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
610 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
621 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
623 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
634 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
636 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
671 clocks = <&gcc GCC_PRNG_AHB_CLK>;
675 gcc: clock-controller@300000 { label
676 compatible = "qcom,gcc-msm8996";
933 <&gcc GCC_HDMI_CLKREF_CLK>;
953 <&gcc GCC_BIMC_GFX_CLK>,
954 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1517 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1526 power-domains = <&gcc PCIE0_GDSC>;
1561 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1562 <&gcc GCC_PCIE_0_AUX_CLK>,
1563 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1564 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1565 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1577 power-domains = <&gcc PCIE1_GDSC>;
1615 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1616 <&gcc GCC_PCIE_1_AUX_CLK>,
1617 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1618 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1619 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1630 power-domains = <&gcc PCIE2_GDSC>;
1665 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1666 <&gcc GCC_PCIE_2_AUX_CLK>,
1667 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1668 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1669 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1687 power-domains = <&gcc UFS_GDSC>;
1702 <&gcc UFS_AXI_CLK_SRC>,
1703 <&gcc GCC_UFS_AXI_CLK>,
1704 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
1705 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
1706 <&gcc GCC_UFS_AHB_CLK>,
1707 <&gcc UFS_ICE_CORE_CLK_SRC>,
1708 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1709 <&gcc GCC_UFS_ICE_CORE_CLK>,
1711 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1712 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
1742 clocks = <&gcc GCC_UFS_CLKREF_CLK>;
1940 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
2050 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2067 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2068 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
2561 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
2562 <&gcc GCC_USB30_MASTER_CLK>,
2563 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
2564 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2565 <&gcc GCC_USB30_SLEEP_CLK>,
2566 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2568 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2569 <&gcc GCC_USB30_MASTER_CLK>;
2572 power-domains = <&gcc USB30_GDSC>;
2594 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2595 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2596 <&gcc GCC_USB3_CLKREF_CLK>;
2599 resets = <&gcc GCC_USB3_PHY_BCR>,
2600 <&gcc GCC_USB3PHY_PHY_BCR>;
2611 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2621 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2622 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2625 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2635 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2636 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
2639 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2654 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2655 <&gcc GCC_SDCC1_APPS_CLK>,
2677 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2678 <&gcc GCC_SDCC2_APPS_CLK>,
2693 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2704 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
2705 <&gcc GCC_BLSP1_AHB_CLK>;
2716 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2717 <&gcc GCC_BLSP1_AHB_CLK>;
2733 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
2734 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
2750 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2761 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2762 <&gcc GCC_BLSP2_AHB_CLK>;
2771 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
2772 <&gcc GCC_BLSP2_AHB_CLK>;
2781 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2782 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
2798 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2799 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
2815 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2816 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
2831 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
2832 <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
2848 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2849 <&gcc GCC_BLSP2_AHB_CLK>;
2868 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
2869 <&gcc GCC_USB20_MASTER_CLK>,
2870 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
2871 <&gcc GCC_USB20_SLEEP_CLK>,
2872 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2874 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
2875 <&gcc GCC_USB20_MASTER_CLK>;
2878 power-domains = <&gcc USB30_GDSC>;
2982 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;