Lines Matching +full:gcc +full:- +full:msm8996
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
7 #include <dt-bindings/power/qcom-rpmpd.h>
10 interrupt-parent = <&intc>;
12 #address-cells = <2>;
13 #size-cells = <2>;
18 xo_board: xo-board {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <19200000>;
22 clock-output-names = "xo_board";
25 sleep_clk: sleep-clk {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <32768>;
29 clock-output-names = "sleep_clk";
34 #address-cells = <2>;
35 #size-cells = <0>;
39 compatible = "arm,cortex-a53";
41 enable-method = "psci";
42 next-level-cache = <&L2_0>;
43 L2_0: l2-cache {
45 cache-level = <2>;
51 compatible = "arm,cortex-a53";
53 enable-method = "psci";
54 next-level-cache = <&L2_0>;
59 compatible = "arm,cortex-a53";
61 enable-method = "psci";
62 next-level-cache = <&L2_0>;
67 compatible = "arm,cortex-a53";
69 enable-method = "psci";
70 next-level-cache = <&L2_0>;
75 compatible = "arm,cortex-a57";
77 enable-method = "psci";
78 next-level-cache = <&L2_1>;
79 L2_1: l2-cache {
81 cache-level = <2>;
87 compatible = "arm,cortex-a57";
89 enable-method = "psci";
90 next-level-cache = <&L2_1>;
95 compatible = "arm,cortex-a57";
97 enable-method = "psci";
98 next-level-cache = <&L2_1>;
103 compatible = "arm,cortex-a57";
105 enable-method = "psci";
106 next-level-cache = <&L2_1>;
109 cpu-map {
150 compatible = "qcom,scm-msm8994", "qcom,scm";
161 compatible = "qcom,tcsr-mutex";
163 #hwlock-cells = <1>;
167 compatible = "arm,cortex-a53-pmu";
172 compatible = "arm,psci-0.2";
176 reserved-memory {
177 #address-cells = <2>;
178 #size-cells = <2>;
183 no-map;
188 no-map;
193 no-map;
198 no-map;
203 no-map;
207 compatible = "qcom,rmtfs-mem";
209 no-map;
211 qcom,client-id = <1>;
216 no-map;
221 no-map;
226 no-map;
235 qcom,smd-edge = <15>;
236 qcom,local-pid = <0>;
237 qcom,remote-pid = <6>;
239 rpm_requests: rpm-requests {
240 compatible = "qcom,rpm-msm8994";
241 qcom,smd-channels = "rpm_requests";
244 compatible = "qcom,rpmcc-msm8994";
245 #clock-cells = <1>;
248 rpmpd: power-controller {
249 compatible = "qcom,msm8994-rpmpd";
250 #power-domain-cells = <1>;
251 operating-points-v2 = <&rpmpd_opp_table>;
253 rpmpd_opp_table: opp-table {
254 compatible = "operating-points-v2";
257 opp-level = <1>;
260 opp-level = <2>;
263 opp-level = <3>;
266 opp-level = <4>;
269 opp-level = <5>;
272 opp-level = <6>;
282 memory-region = <&smem_mem>;
283 qcom,rpm-msg-ram = <&rpm_msg_ram>;
287 smp2p-lpass {
295 qcom,local-pid = <0>;
296 qcom,remote-pid = <2>;
298 adsp_smp2p_out: master-kernel {
299 qcom,entry-name = "master-kernel";
300 #qcom,smem-state-cells = <1>;
303 adsp_smp2p_in: slave-kernel {
304 qcom,entry-name = "slave-kernel";
306 interrupt-controller;
307 #interrupt-cells = <2>;
311 smp2p-modem {
315 interrupt-parent = <&intc>;
320 qcom,local-pid = <0>;
321 qcom,remote-pid = <1>;
323 modem_smp2p_out: master-kernel {
324 qcom,entry-name = "master-kernel";
325 #qcom,smem-state-cells = <1>;
328 modem_smp2p_in: slave-kernel {
329 qcom,entry-name = "slave-kernel";
331 interrupt-controller;
332 #interrupt-cells = <2>;
338 #address-cells = <1>;
339 #size-cells = <1>;
341 compatible = "simple-bus";
343 intc: interrupt-controller@f9000000 {
344 compatible = "qcom,msm-qgic2";
345 interrupt-controller;
346 #interrupt-cells = <3>;
352 compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
354 #mbox-cells = <1>;
358 #address-cells = <1>;
359 #size-cells = <1>;
361 compatible = "arm,armv7-timer-mem";
365 frame-number = <0>;
373 frame-number = <1>;
380 frame-number = <2>;
387 frame-number = <3>;
394 frame-number = <4>;
401 frame-number = <5>;
408 frame-number = <6>;
416 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
418 #address-cells = <1>;
419 #size-cells = <1>;
422 clocks = <&gcc GCC_USB30_MASTER_CLK>,
423 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
424 <&gcc GCC_USB30_SLEEP_CLK>,
425 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
426 clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo";
428 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
429 <&gcc GCC_USB30_MASTER_CLK>;
430 assigned-clock-rates = <19200000>, <120000000>;
432 power-domains = <&gcc USB30_GDSC>;
433 qcom,select-utmi-as-pipe-clk;
441 maximum-speed = "high-speed";
447 compatible = "qcom,sdhci-msm-v4";
449 reg-names = "hc_mem", "core_mem";
453 interrupt-names = "hc_irq", "pwr_irq";
455 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
456 <&gcc GCC_SDCC1_AHB_CLK>,
458 clock-names = "core", "iface", "xo";
460 pinctrl-names = "default", "sleep";
461 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
462 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
464 bus-width = <8>;
465 non-removable;
470 compatible = "qcom,sdhci-msm-v4";
472 reg-names = "hc_mem", "core_mem";
476 interrupt-names = "hc_irq", "pwr_irq";
478 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
479 <&gcc GCC_SDCC2_AHB_CLK>,
481 clock-names = "core", "iface", "xo";
483 pinctrl-names = "default", "sleep";
484 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
485 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
487 cd-gpios = <&tlmm 100 0>;
488 bus-width = <4>;
492 blsp1_dma: dma-controller@f9904000 {
493 compatible = "qcom,bam-v1.7.0";
496 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
497 clock-names = "bam_clk";
498 #dma-cells = <1>;
500 qcom,controlled-remotely;
501 num-channels = <18>;
502 qcom,num-ees = <4>;
506 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
509 clock-names = "core", "iface";
510 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
511 <&gcc GCC_BLSP1_AHB_CLK>;
512 pinctrl-names = "default", "sleep";
513 pinctrl-0 = <&blsp1_uart2_default>;
514 pinctrl-1 = <&blsp1_uart2_sleep>;
519 compatible = "qcom,i2c-qup-v2.2.1";
522 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
523 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
524 clock-names = "iface", "core";
525 clock-frequency = <400000>;
527 dma-names = "tx", "rx";
528 pinctrl-names = "default", "sleep";
529 pinctrl-0 = <&i2c1_default>;
530 pinctrl-1 = <&i2c1_sleep>;
531 #address-cells = <1>;
532 #size-cells = <0>;
537 compatible = "qcom,spi-qup-v2.2.1";
540 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
541 <&gcc GCC_BLSP1_AHB_CLK>;
542 clock-names = "core", "iface";
543 spi-max-frequency = <19200000>;
545 dma-names = "tx", "rx";
546 pinctrl-names = "default", "sleep";
547 pinctrl-0 = <&blsp1_spi1_default>;
548 pinctrl-1 = <&blsp1_spi1_sleep>;
549 #address-cells = <1>;
550 #size-cells = <0>;
555 compatible = "qcom,i2c-qup-v2.2.1";
558 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
559 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
560 clock-names = "iface", "core";
561 clock-frequency = <400000>;
563 dma-names = "tx", "rx";
564 pinctrl-names = "default", "sleep";
565 pinctrl-0 = <&i2c2_default>;
566 pinctrl-1 = <&i2c2_sleep>;
567 #address-cells = <1>;
568 #size-cells = <0>;
575 compatible = "qcom,i2c-qup-v2.2.1";
578 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
579 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
580 clock-names = "iface", "core";
581 clock-frequency = <400000>;
583 dma-names = "tx", "rx";
584 pinctrl-names = "default", "sleep";
585 pinctrl-0 = <&i2c4_default>;
586 pinctrl-1 = <&i2c4_sleep>;
587 #address-cells = <1>;
588 #size-cells = <0>;
593 compatible = "qcom,i2c-qup-v2.2.1";
596 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
597 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
598 clock-names = "iface", "core";
599 clock-frequency = <400000>;
601 dma-names = "tx", "rx";
602 pinctrl-names = "default", "sleep";
603 pinctrl-0 = <&i2c5_default>;
604 pinctrl-1 = <&i2c5_sleep>;
605 #address-cells = <1>;
606 #size-cells = <0>;
611 compatible = "qcom,i2c-qup-v2.2.1";
614 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
615 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
616 clock-names = "iface", "core";
617 clock-frequency = <400000>;
619 dma-names = "tx", "rx";
620 pinctrl-names = "default", "sleep";
621 pinctrl-0 = <&i2c6_default>;
622 pinctrl-1 = <&i2c6_sleep>;
623 #address-cells = <1>;
624 #size-cells = <0>;
628 blsp2_dma: dma-controller@f9944000 {
629 compatible = "qcom,bam-v1.7.0";
632 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
633 clock-names = "bam_clk";
634 #dma-cells = <1>;
636 qcom,controlled-remotely;
637 num-channels = <18>;
638 qcom,num-ees = <4>;
642 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
645 clock-names = "core", "iface";
646 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
647 <&gcc GCC_BLSP2_AHB_CLK>;
649 dma-names = "tx", "rx";
650 pinctrl-names = "default", "sleep";
651 pinctrl-0 = <&blsp2_uart2_default>;
652 pinctrl-1 = <&blsp2_uart2_sleep>;
657 compatible = "qcom,i2c-qup-v2.2.1";
660 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
661 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
662 clock-names = "iface", "core";
663 clock-frequency = <400000>;
665 dma-names = "tx", "rx";
666 pinctrl-names = "default", "sleep";
667 pinctrl-0 = <&i2c7_default>;
668 pinctrl-1 = <&i2c7_sleep>;
669 #address-cells = <1>;
670 #size-cells = <0>;
675 compatible = "qcom,spi-qup-v2.2.1";
678 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
679 <&gcc GCC_BLSP2_AHB_CLK>;
680 clock-names = "core", "iface";
681 spi-max-frequency = <19200000>;
683 dma-names = "tx", "rx";
684 pinctrl-names = "default", "sleep";
685 pinctrl-0 = <&blsp2_spi10_default>;
686 pinctrl-1 = <&blsp2_spi10_sleep>;
687 #address-cells = <1>;
688 #size-cells = <0>;
693 compatible = "qcom,i2c-qup-v2.2.1";
696 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
697 <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
698 clock-names = "iface", "core";
699 clock-frequency = <355000>;
701 dma-names = "tx", "rx";
702 pinctrl-names = "default", "sleep";
703 pinctrl-0 = <&i2c11_default>;
704 pinctrl-1 = <&i2c11_sleep>;
705 #address-cells = <1>;
706 #size-cells = <0>;
710 gcc: clock-controller@fc400000 { label
711 compatible = "qcom,gcc-msm8994";
712 #clock-cells = <1>;
713 #reset-cells = <1>;
714 #power-domain-cells = <1>;
719 compatible = "qcom,rpm-msg-ram";
729 compatible = "qcom,spmi-pmic-arb";
733 reg-names = "core", "intr", "cnfg";
734 interrupt-names = "periph_irq";
738 #address-cells = <2>;
739 #size-cells = <0>;
740 interrupt-controller;
741 #interrupt-cells = <4>;
750 compatible = "qcom,msm8994-pinctrl";
753 gpio-controller;
754 gpio-ranges = <&tlmm 0 0 146>;
755 #gpio-cells = <2>;
756 interrupt-controller;
757 #interrupt-cells = <2>;
759 blsp1_uart2_default: blsp1-uart2-default {
762 drive-strength = <16>;
763 bias-disable;
766 blsp1_uart2_sleep: blsp1-uart2-sleep {
769 drive-strength = <2>;
770 bias-pull-down;
773 blsp2_uart2_default: blsp2-uart2-default {
777 drive-strength = <16>;
778 bias-disable;
781 blsp2_uart2_sleep: blsp2-uart2-sleep {
785 drive-strength = <2>;
786 bias-disable;
789 i2c1_default: i2c1-default {
792 drive-strength = <2>;
793 bias-disable;
796 i2c1_sleep: i2c1-sleep {
799 drive-strength = <2>;
800 bias-disable;
803 i2c2_default: i2c2-default {
806 drive-strength = <2>;
807 bias-disable;
810 i2c2_sleep: i2c2-sleep {
813 drive-strength = <2>;
814 bias-disable;
817 i2c4_default: i2c4-default {
820 drive-strength = <2>;
821 bias-disable;
824 i2c4_sleep: i2c4-sleep {
827 drive-strength = <2>;
828 bias-pull-down;
829 input-enable;
832 i2c5_default: i2c5-default {
835 drive-strength = <2>;
836 bias-disable;
839 i2c5_sleep: i2c5-sleep {
842 drive-strength = <2>;
843 bias-disable;
846 i2c6_default: i2c6-default {
849 drive-strength = <2>;
850 bias-disable;
853 i2c6_sleep: i2c6-sleep {
856 drive-strength = <2>;
857 bias-disable;
860 i2c7_default: i2c7-default {
863 drive-strength = <2>;
864 bias-disable;
867 i2c7_sleep: i2c7-sleep {
870 drive-strength = <2>;
871 bias-disable;
874 blsp2_spi10_default: blsp2-spi10-default {
878 drive-strength = <10>;
879 bias-pull-down;
884 drive-strength = <2>;
885 bias-disable;
889 blsp2_spi10_sleep: blsp2-spi10-sleep {
891 drive-strength = <2>;
892 bias-disable;
895 i2c11_default: i2c11-default {
898 drive-strength = <2>;
899 bias-disable;
902 i2c11_sleep: i2c11-sleep {
905 drive-strength = <2>;
906 bias-disable;
909 blsp1_spi1_default: blsp1-spi1-default {
913 drive-strength = <10>;
914 bias-pull-down;
919 drive-strength = <2>;
920 bias-disable;
924 blsp1_spi1_sleep: blsp1-spi1-sleep {
926 drive-strength = <2>;
927 bias-disable;
930 sdc1_clk_on: clk-on {
932 bias-disable;
933 drive-strength = <16>;
936 sdc1_clk_off: clk-off {
938 bias-disable;
939 drive-strength = <2>;
942 sdc1_cmd_on: cmd-on {
944 bias-pull-up;
945 drive-strength = <8>;
948 sdc1_cmd_off: cmd-off {
950 bias-pull-up;
951 drive-strength = <2>;
954 sdc1_data_on: data-on {
956 bias-pull-up;
957 drive-strength = <8>;
960 sdc1_data_off: data-off {
962 bias-pull-up;
963 drive-strength = <2>;
966 sdc1_rclk_on: rclk-on {
968 bias-pull-down;
971 sdc1_rclk_off: rclk-off {
973 bias-pull-down;
976 sdc2_clk_on: sdc2-clk-on {
978 bias-disable;
979 drive-strength = <10>;
982 sdc2_clk_off: sdc2-clk-off {
984 bias-disable;
985 drive-strength = <2>;
988 sdc2_cmd_on: sdc2-cmd-on {
990 bias-pull-up;
991 drive-strength = <10>;
994 sdc2_cmd_off: sdc2-cmd-off {
996 bias-pull-up;
997 drive-strength = <2>;
1000 sdc2_data_on: sdc2-data-on {
1002 bias-pull-up;
1003 drive-strength = <10>;
1006 sdc2_data_off: sdc2-data-off {
1008 bias-pull-up;
1009 drive-strength = <2>;
1015 compatible = "arm,armv8-timer";
1022 vph_pwr: vph-pwr-regulator {
1023 compatible = "regulator-fixed";
1024 regulator-name = "vph_pwr";
1026 regulator-min-microvolt = <3600000>;
1027 regulator-max-microvolt = <3600000>;
1029 regulator-always-on;