Lines Matching refs:gcc
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
99 clocks = <&gcc GCC_USB1_AUX_CLK>,
100 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
104 resets = <&gcc GCC_USB1_PHY_BCR>,
105 <&gcc GCC_USB3PHY_1_PHY_BCR>;
115 clocks = <&gcc GCC_USB1_PIPE_CLK>;
126 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
130 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
142 clocks = <&gcc GCC_USB0_AUX_CLK>,
143 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
147 resets = <&gcc GCC_USB0_PHY_BCR>,
148 <&gcc GCC_USB3PHY_0_PHY_BCR>;
158 clocks = <&gcc GCC_USB0_PIPE_CLK>;
169 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
173 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
181 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
185 resets = <&gcc GCC_PCIE0_PHY_BCR>,
186 <&gcc GCC_PCIE0PHY_PHY_BCR>;
196 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
200 resets = <&gcc GCC_PCIE1_PHY_BCR>,
201 <&gcc GCC_PCIE1PHY_PHY_BCR>;
210 clocks = <&gcc GCC_PRNG_AHB_CLK>;
219 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
230 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
231 <&gcc GCC_CRYPTO_AXI_CLK>,
232 <&gcc GCC_CRYPTO_CLK>;
289 gcc: gcc@1800000 { label
290 compatible = "qcom,gcc-ipq8074";
306 <&gcc GCC_SDCC1_AHB_CLK>,
307 <&gcc GCC_SDCC1_APPS_CLK>;
322 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
332 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
333 <&gcc GCC_BLSP1_AHB_CLK>;
342 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
343 <&gcc GCC_BLSP1_AHB_CLK>;
357 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
358 <&gcc GCC_BLSP1_AHB_CLK>;
372 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
373 <&gcc GCC_BLSP1_AHB_CLK>;
388 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
389 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
405 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
406 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
420 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
421 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
433 clocks = <&gcc GCC_QPIC_AHB_CLK>;
445 clocks = <&gcc GCC_QPIC_CLK>,
446 <&gcc GCC_QPIC_AHB_CLK>;
465 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
466 <&gcc GCC_USB0_MASTER_CLK>,
467 <&gcc GCC_USB0_SLEEP_CLK>,
468 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
474 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
475 <&gcc GCC_USB0_MASTER_CLK>,
476 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
481 resets = <&gcc GCC_USB0_BCR>;
505 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
506 <&gcc GCC_USB1_MASTER_CLK>,
507 <&gcc GCC_USB1_SLEEP_CLK>,
508 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
514 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
515 <&gcc GCC_USB1_MASTER_CLK>,
516 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
521 resets = <&gcc GCC_USB1_BCR>;
655 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
656 <&gcc GCC_PCIE1_AXI_M_CLK>,
657 <&gcc GCC_PCIE1_AXI_S_CLK>,
658 <&gcc GCC_PCIE1_AHB_CLK>,
659 <&gcc GCC_PCIE1_AUX_CLK>;
665 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
666 <&gcc GCC_PCIE1_SLEEP_ARES>,
667 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
668 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
669 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
670 <&gcc GCC_PCIE1_AHB_ARES>,
671 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
717 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
718 <&gcc GCC_PCIE0_AXI_M_CLK>,
719 <&gcc GCC_PCIE0_AXI_S_CLK>,
720 <&gcc GCC_PCIE0_AHB_CLK>,
721 <&gcc GCC_PCIE0_AUX_CLK>;
728 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
729 <&gcc GCC_PCIE0_SLEEP_ARES>,
730 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
731 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
732 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
733 <&gcc GCC_PCIE0_AHB_ARES>,
734 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;