Lines Matching +full:gcc +full:- +full:ipq8074
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
10 model = "Qualcomm Technologies, Inc. IPQ8074";
11 compatible = "qcom,ipq8074";
15 compatible = "fixed-clock";
16 clock-frequency = <32000>;
17 #clock-cells = <0>;
21 compatible = "fixed-clock";
22 clock-frequency = <19200000>;
23 #clock-cells = <0>;
28 #address-cells = <0x1>;
29 #size-cells = <0x0>;
33 compatible = "arm,cortex-a53";
35 next-level-cache = <&L2_0>;
36 enable-method = "psci";
41 compatible = "arm,cortex-a53";
42 enable-method = "psci";
44 next-level-cache = <&L2_0>;
49 compatible = "arm,cortex-a53";
50 enable-method = "psci";
52 next-level-cache = <&L2_0>;
57 compatible = "arm,cortex-a53";
58 enable-method = "psci";
60 next-level-cache = <&L2_0>;
63 L2_0: l2-cache {
65 cache-level = <0x2>;
70 compatible = "arm,cortex-a53-pmu";
75 compatible = "arm,psci-1.0";
81 compatible = "qcom,scm-ipq8074", "qcom,scm";
86 #address-cells = <0x1>;
87 #size-cells = <0x1>;
89 compatible = "simple-bus";
92 compatible = "qcom,ipq8074-qmp-usb3-phy";
94 #clock-cells = <1>;
95 #address-cells = <1>;
96 #size-cells = <1>;
99 clocks = <&gcc GCC_USB1_AUX_CLK>,
100 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
102 clock-names = "aux", "cfg_ahb", "ref";
104 resets = <&gcc GCC_USB1_PHY_BCR>,
105 <&gcc GCC_USB3PHY_1_PHY_BCR>;
106 reset-names = "phy","common";
114 #phy-cells = <0>;
115 clocks = <&gcc GCC_USB1_PIPE_CLK>;
116 clock-names = "pipe0";
117 clock-output-names = "gcc_usb1_pipe_clk_src";
122 compatible = "qcom,ipq8074-qusb2-phy";
124 #phy-cells = <0>;
126 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
128 clock-names = "cfg_ahb", "ref";
130 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
135 compatible = "qcom,ipq8074-qmp-usb3-phy";
137 #clock-cells = <1>;
138 #address-cells = <1>;
139 #size-cells = <1>;
142 clocks = <&gcc GCC_USB0_AUX_CLK>,
143 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
145 clock-names = "aux", "cfg_ahb", "ref";
147 resets = <&gcc GCC_USB0_PHY_BCR>,
148 <&gcc GCC_USB3PHY_0_PHY_BCR>;
149 reset-names = "phy","common";
157 #phy-cells = <0>;
158 clocks = <&gcc GCC_USB0_PIPE_CLK>;
159 clock-names = "pipe0";
160 clock-output-names = "gcc_usb0_pipe_clk_src";
165 compatible = "qcom,ipq8074-qusb2-phy";
167 #phy-cells = <0>;
169 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
171 clock-names = "cfg_ahb", "ref";
173 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
178 compatible = "qcom,ipq8074-qmp-pcie-phy";
180 #phy-cells = <0>;
181 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
182 clock-names = "pipe_clk";
183 clock-output-names = "pcie20_phy0_pipe_clk";
185 resets = <&gcc GCC_PCIE0_PHY_BCR>,
186 <&gcc GCC_PCIE0PHY_PHY_BCR>;
187 reset-names = "phy",
193 compatible = "qcom,ipq8074-qmp-pcie-phy";
195 #phy-cells = <0>;
196 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
197 clock-names = "pipe_clk";
198 clock-output-names = "pcie20_phy1_pipe_clk";
200 resets = <&gcc GCC_PCIE1_PHY_BCR>,
201 <&gcc GCC_PCIE1PHY_PHY_BCR>;
202 reset-names = "phy",
208 compatible = "qcom,prng-ee";
210 clocks = <&gcc GCC_PRNG_AHB_CLK>;
211 clock-names = "core";
216 compatible = "qcom,bam-v1.7.0";
219 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
220 clock-names = "bam_clk";
221 #dma-cells = <1>;
223 qcom,controlled-remotely = <1>;
228 compatible = "qcom,crypto-v5.1";
230 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
231 <&gcc GCC_CRYPTO_AXI_CLK>,
232 <&gcc GCC_CRYPTO_CLK>;
233 clock-names = "iface", "bus", "core";
235 dma-names = "rx", "tx";
240 compatible = "qcom,ipq8074-pinctrl";
243 gpio-controller;
244 gpio-ranges = <&tlmm 0 0 70>;
245 #gpio-cells = <0x2>;
246 interrupt-controller;
247 #interrupt-cells = <0x2>;
249 serial_4_pins: serial4-pinmux {
252 drive-strength = <8>;
253 bias-disable;
256 i2c_0_pins: i2c-0-pinmux {
259 drive-strength = <8>;
260 bias-disable;
263 spi_0_pins: spi-0-pins {
266 drive-strength = <8>;
267 bias-disable;
270 hsuart_pins: hsuart-pins {
273 drive-strength = <8>;
274 bias-disable;
277 qpic_pins: qpic-pins {
284 drive-strength = <8>;
285 bias-disable;
289 gcc: gcc@1800000 { label
290 compatible = "qcom,gcc-ipq8074";
292 #clock-cells = <0x1>;
293 #reset-cells = <0x1>;
297 compatible = "qcom,sdhci-msm-v4";
299 reg-names = "hc_mem", "core_mem";
303 interrupt-names = "hc_irq", "pwr_irq";
306 <&gcc GCC_SDCC1_AHB_CLK>,
307 <&gcc GCC_SDCC1_APPS_CLK>;
308 clock-names = "xo", "iface", "core";
309 max-frequency = <384000000>;
310 mmc-ddr-1_8v;
311 mmc-hs200-1_8v;
312 mmc-hs400-1_8v;
313 bus-width = <8>;
318 blsp_dma: dma-controller@7884000 {
319 compatible = "qcom,bam-v1.7.0";
322 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
323 clock-names = "bam_clk";
324 #dma-cells = <1>;
329 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
332 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
333 <&gcc GCC_BLSP1_AHB_CLK>;
334 clock-names = "core", "iface";
339 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
342 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
343 <&gcc GCC_BLSP1_AHB_CLK>;
344 clock-names = "core", "iface";
347 dma-names = "tx", "rx";
348 pinctrl-0 = <&hsuart_pins>;
349 pinctrl-names = "default";
354 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
357 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
358 <&gcc GCC_BLSP1_AHB_CLK>;
359 clock-names = "core", "iface";
360 pinctrl-0 = <&serial_4_pins>;
361 pinctrl-names = "default";
366 compatible = "qcom,spi-qup-v2.2.1";
367 #address-cells = <1>;
368 #size-cells = <0>;
371 spi-max-frequency = <50000000>;
372 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
373 <&gcc GCC_BLSP1_AHB_CLK>;
374 clock-names = "core", "iface";
376 dma-names = "tx", "rx";
377 pinctrl-0 = <&spi_0_pins>;
378 pinctrl-names = "default";
383 compatible = "qcom,i2c-qup-v2.2.1";
384 #address-cells = <1>;
385 #size-cells = <0>;
388 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
389 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
390 clock-names = "iface", "core";
391 clock-frequency = <400000>;
393 dma-names = "rx", "tx";
394 pinctrl-0 = <&i2c_0_pins>;
395 pinctrl-names = "default";
400 compatible = "qcom,i2c-qup-v2.2.1";
401 #address-cells = <1>;
402 #size-cells = <0>;
405 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
406 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
407 clock-names = "iface", "core";
408 clock-frequency = <100000>;
410 dma-names = "rx", "tx";
415 compatible = "qcom,i2c-qup-v2.2.1";
416 #address-cells = <1>;
417 #size-cells = <0>;
420 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
421 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
422 clock-names = "iface", "core";
423 clock-frequency = <100000>;
425 dma-names = "rx", "tx";
429 qpic_bam: dma-controller@7984000 {
430 compatible = "qcom,bam-v1.7.0";
433 clocks = <&gcc GCC_QPIC_AHB_CLK>;
434 clock-names = "bam_clk";
435 #dma-cells = <1>;
441 compatible = "qcom,ipq8074-nand";
443 #address-cells = <1>;
444 #size-cells = <0>;
445 clocks = <&gcc GCC_QPIC_CLK>,
446 <&gcc GCC_QPIC_AHB_CLK>;
447 clock-names = "core", "aon";
452 dma-names = "tx", "rx", "cmd";
453 pinctrl-0 = <&qpic_pins>;
454 pinctrl-names = "default";
461 #address-cells = <1>;
462 #size-cells = <1>;
465 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
466 <&gcc GCC_USB0_MASTER_CLK>,
467 <&gcc GCC_USB0_SLEEP_CLK>,
468 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
469 clock-names = "sys_noc_axi",
474 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
475 <&gcc GCC_USB0_MASTER_CLK>,
476 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
477 assigned-clock-rates = <133330000>,
481 resets = <&gcc GCC_USB0_BCR>;
489 phy-names = "usb2-phy", "usb3-phy";
490 snps,is-utmi-l1-suspend;
491 snps,hird-threshold = /bits/ 8 <0x0>;
501 #address-cells = <1>;
502 #size-cells = <1>;
505 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
506 <&gcc GCC_USB1_MASTER_CLK>,
507 <&gcc GCC_USB1_SLEEP_CLK>,
508 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
509 clock-names = "sys_noc_axi",
514 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
515 <&gcc GCC_USB1_MASTER_CLK>,
516 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
517 assigned-clock-rates = <133330000>,
521 resets = <&gcc GCC_USB1_BCR>;
529 phy-names = "usb2-phy", "usb3-phy";
530 snps,is-utmi-l1-suspend;
531 snps,hird-threshold = /bits/ 8 <0x0>;
538 intc: interrupt-controller@b000000 {
539 compatible = "qcom,msm-qgic2";
540 interrupt-controller;
541 #interrupt-cells = <0x3>;
546 compatible = "arm,armv8-timer";
554 compatible = "qcom,kpss-wdt";
558 timeout-sec = <30>;
562 #address-cells = <1>;
563 #size-cells = <1>;
565 compatible = "arm,armv7-timer-mem";
567 clock-frequency = <19200000>;
570 frame-number = <0>;
578 frame-number = <1>;
585 frame-number = <2>;
592 frame-number = <3>;
599 frame-number = <4>;
606 frame-number = <5>;
613 frame-number = <6>;
621 compatible = "qcom,pcie-ipq8074";
626 reg-names = "dbi", "elbi", "parf", "config";
628 linux,pci-domain = <1>;
629 bus-range = <0x00 0xff>;
630 num-lanes = <1>;
631 #address-cells = <3>;
632 #size-cells = <2>;
635 phy-names = "pciephy";
640 0 0xd00000>; /* non-prefetchable memory */
643 interrupt-names = "msi";
644 #interrupt-cells = <1>;
645 interrupt-map-mask = <0 0 0 0x7>;
646 interrupt-map = <0 0 0 1 &intc 0 142
655 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
656 <&gcc GCC_PCIE1_AXI_M_CLK>,
657 <&gcc GCC_PCIE1_AXI_S_CLK>,
658 <&gcc GCC_PCIE1_AHB_CLK>,
659 <&gcc GCC_PCIE1_AUX_CLK>;
660 clock-names = "iface",
665 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
666 <&gcc GCC_PCIE1_SLEEP_ARES>,
667 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
668 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
669 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
670 <&gcc GCC_PCIE1_AHB_ARES>,
671 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
672 reset-names = "pipe",
683 compatible = "qcom,pcie-ipq8074";
688 reg-names = "dbi", "elbi", "parf", "config";
690 linux,pci-domain = <0>;
691 bus-range = <0x00 0xff>;
692 num-lanes = <1>;
693 #address-cells = <3>;
694 #size-cells = <2>;
697 phy-names = "pciephy";
702 0 0xd00000>; /* non-prefetchable memory */
705 interrupt-names = "msi";
706 #interrupt-cells = <1>;
707 interrupt-map-mask = <0 0 0 0x7>;
708 interrupt-map = <0 0 0 1 &intc 0 75
717 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
718 <&gcc GCC_PCIE0_AXI_M_CLK>,
719 <&gcc GCC_PCIE0_AXI_S_CLK>,
720 <&gcc GCC_PCIE0_AHB_CLK>,
721 <&gcc GCC_PCIE0_AUX_CLK>;
723 clock-names = "iface",
728 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
729 <&gcc GCC_PCIE0_SLEEP_ARES>,
730 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
731 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
732 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
733 <&gcc GCC_PCIE0_AHB_ARES>,
734 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
735 reset-names = "pipe",