Lines Matching +full:phy +full:- +full:qcom +full:- +full:qusb2
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
11 #include <dt-bindings/clock/qcom,apss-ipq.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&intc>;
19 sleep_clk: sleep-clk {
20 compatible = "fixed-clock";
21 clock-frequency = <32000>;
22 #clock-cells = <0>;
26 compatible = "fixed-clock";
27 clock-frequency = <24000000>;
28 #clock-cells = <0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
38 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 next-level-cache = <&L2_0>;
43 clock-names = "cpu";
44 operating-points-v2 = <&cpu_opp_table>;
45 cpu-supply = <&ipq6018_s2>;
50 compatible = "arm,cortex-a53";
51 enable-method = "psci";
53 next-level-cache = <&L2_0>;
55 clock-names = "cpu";
56 operating-points-v2 = <&cpu_opp_table>;
57 cpu-supply = <&ipq6018_s2>;
62 compatible = "arm,cortex-a53";
63 enable-method = "psci";
65 next-level-cache = <&L2_0>;
67 clock-names = "cpu";
68 operating-points-v2 = <&cpu_opp_table>;
69 cpu-supply = <&ipq6018_s2>;
74 compatible = "arm,cortex-a53";
75 enable-method = "psci";
77 next-level-cache = <&L2_0>;
79 clock-names = "cpu";
80 operating-points-v2 = <&cpu_opp_table>;
81 cpu-supply = <&ipq6018_s2>;
84 L2_0: l2-cache {
86 cache-level = <0x2>;
91 compatible = "operating-points-v2";
92 opp-shared;
94 opp-864000000 {
95 opp-hz = /bits/ 64 <864000000>;
96 opp-microvolt = <725000>;
97 clock-latency-ns = <200000>;
99 opp-1056000000 {
100 opp-hz = /bits/ 64 <1056000000>;
101 opp-microvolt = <787500>;
102 clock-latency-ns = <200000>;
104 opp-1320000000 {
105 opp-hz = /bits/ 64 <1320000000>;
106 opp-microvolt = <862500>;
107 clock-latency-ns = <200000>;
109 opp-1440000000 {
110 opp-hz = /bits/ 64 <1440000000>;
111 opp-microvolt = <925000>;
112 clock-latency-ns = <200000>;
114 opp-1608000000 {
115 opp-hz = /bits/ 64 <1608000000>;
116 opp-microvolt = <987500>;
117 clock-latency-ns = <200000>;
119 opp-1800000000 {
120 opp-hz = /bits/ 64 <1800000000>;
121 opp-microvolt = <1062500>;
122 clock-latency-ns = <200000>;
128 compatible = "qcom,scm";
133 compatible = "qcom,tcsr-mutex";
135 #hwlock-cells = <1>;
139 compatible = "arm,cortex-a53-pmu";
145 compatible = "arm,psci-1.0";
149 reserved-memory {
150 #address-cells = <2>;
151 #size-cells = <2>;
156 no-map;
161 no-map;
166 no-map;
171 no-map;
176 compatible = "qcom,smem";
177 memory-region = <&smem_region>;
182 #address-cells = <2>;
183 #size-cells = <2>;
185 dma-ranges;
186 compatible = "simple-bus";
189 compatible = "qcom,prng-ee";
192 clock-names = "core";
195 cryptobam: dma-controller@704000 {
196 compatible = "qcom,bam-v1.7.0";
200 clock-names = "bam_clk";
201 #dma-cells = <1>;
202 qcom,ee = <1>;
203 qcom,controlled-remotely = <1>;
204 qcom,config-pipe-trust-reg = <0>;
208 compatible = "qcom,crypto-v5.1";
213 clock-names = "iface", "bus", "core";
215 dma-names = "rx", "tx";
219 compatible = "qcom,ipq6018-pinctrl";
222 gpio-controller;
223 #gpio-cells = <2>;
224 gpio-ranges = <&tlmm 0 80>;
225 interrupt-controller;
226 #interrupt-cells = <2>;
228 serial_3_pins: serial3-pinmux {
231 drive-strength = <8>;
232 bias-pull-down;
235 qpic_pins: qpic-pins {
242 drive-strength = <8>;
243 bias-disable;
248 compatible = "qcom,gcc-ipq6018";
251 clock-names = "xo", "sleep_clk";
252 #clock-cells = <1>;
253 #reset-cells = <1>;
266 blsp_dma: dma-controller@7884000 {
267 compatible = "qcom,bam-v1.7.0";
271 clock-names = "bam_clk";
272 #dma-cells = <1>;
273 qcom,ee = <0>;
277 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
282 clock-names = "core", "iface";
287 compatible = "qcom,spi-qup-v2.2.1";
288 #address-cells = <1>;
289 #size-cells = <0>;
292 spi-max-frequency = <50000000>;
295 clock-names = "core", "iface";
297 dma-names = "tx", "rx";
302 compatible = "qcom,spi-qup-v2.2.1";
303 #address-cells = <1>;
304 #size-cells = <0>;
307 spi-max-frequency = <50000000>;
310 clock-names = "core", "iface";
312 dma-names = "tx", "rx";
317 compatible = "qcom,i2c-qup-v2.2.1";
318 #address-cells = <1>;
319 #size-cells = <0>;
324 clock-names = "iface", "core";
325 clock-frequency = <400000>;
327 dma-names = "rx", "tx";
332 compatible = "qcom,i2c-qup-v2.2.1";
333 #address-cells = <1>;
334 #size-cells = <0>;
339 clock-names = "iface", "core";
340 clock-frequency = <400000>;
342 dma-names = "rx", "tx";
346 qpic_bam: dma-controller@7984000 {
347 compatible = "qcom,bam-v1.7.0";
352 clock-names = "iface_clk", "bam_clk";
353 #dma-cells = <1>;
354 qcom,ee = <0>;
359 compatible = "qcom,ipq6018-nand";
361 #address-cells = <1>;
362 #size-cells = <0>;
365 clock-names = "core", "aon";
370 dma-names = "tx", "rx", "cmd";
371 pinctrl-0 = <&qpic_pins>;
372 pinctrl-names = "default";
376 intc: interrupt-controller@b000000 {
377 compatible = "qcom,msm-qgic2";
378 interrupt-controller;
379 #interrupt-cells = <0x3>;
387 pcie_phy: phy@84000 {
388 compatible = "qcom,ipq6018-qmp-pcie-phy";
391 #address-cells = <2>;
392 #size-cells = <2>;
397 clock-names = "aux", "cfg_ahb";
401 reset-names = "phy",
408 #phy-cells = <0>;
411 clock-names = "pipe0";
412 clock-output-names = "gcc_pcie0_pipe_clk_src";
413 #clock-cells = <0>;
418 compatible = "qcom,pcie-ipq6018";
424 reg-names = "dbi", "elbi", "atu", "parf", "config";
427 linux,pci-domain = <0>;
428 bus-range = <0x00 0xff>;
429 num-lanes = <1>;
430 #address-cells = <3>;
431 #size-cells = <2>;
434 phy-names = "pciephy";
439 0 0xfde0000>; /* non-prefetchable memory */
442 interrupt-names = "msi";
444 #interrupt-cells = <1>;
445 interrupt-map-mask = <0 0 0 0x7>;
446 interrupt-map = <0 0 0 1 &intc 0 75
460 clock-names = "iface",
474 reset-names = "pipe",
487 compatible = "qcom,kpss-wdt";
491 timeout-sec = <10>;
495 compatible = "qcom,ipq6018-apcs-apps-global";
497 #clock-cells = <1>;
499 clock-names = "pll", "xo";
500 #mbox-cells = <1>;
504 compatible = "qcom,ipq6018-a53pll";
506 #clock-cells = <0>;
508 clock-names = "xo";
512 compatible = "arm,armv8-timer";
520 #address-cells = <2>;
521 #size-cells = <2>;
523 compatible = "arm,armv7-timer-mem";
525 clock-frequency = <19200000>;
528 frame-number = <0>;
536 frame-number = <1>;
543 frame-number = <2>;
550 frame-number = <3>;
557 frame-number = <4>;
564 frame-number = <5>;
571 frame-number = <6>;
579 compatible = "qcom,ipq6018-wcss-pil";
582 reg-names = "qdsp6",
584 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
589 interrupt-names = "wdog",
593 "stop-ack";
599 reset-names = "wcss_aon_reset",
604 clock-names = "prng";
606 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
608 qcom,smem-states = <&wcss_smp2p_out 0>,
610 qcom,smem-state-names = "shutdown",
613 memory-region = <&q6_region>;
615 glink-edge {
617 qcom,remote-pid = <1>;
621 qcom,glink-channels = "IPCRTR";
627 compatible = "qcom,ipq6018-qusb2-phy";
629 #phy-cells = <0>;
633 clock-names = "cfg_ahb", "ref";
640 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
642 #address-cells = <2>;
643 #size-cells = <2>;
648 clock-names = "master",
652 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
654 assigned-clock-rates = <133330000>,
664 phy-names = "usb2-phy";
665 tx-fifo-resize;
666 snps,is-utmi-l1-suspend;
667 snps,hird-threshold = /bits/ 8 <0x0>;
676 wcss: wcss-smp2p {
677 compatible = "qcom,smp2p";
678 qcom,smem = <435>, <428>;
680 interrupt-parent = <&intc>;
685 qcom,local-pid = <0>;
686 qcom,remote-pid = <1>;
688 wcss_smp2p_out: master-kernel {
689 qcom,entry-name = "master-kernel";
690 #qcom,smem-state-cells = <1>;
693 wcss_smp2p_in: slave-kernel {
694 qcom,entry-name = "slave-kernel";
695 interrupt-controller;
696 #interrupt-cells = <2>;
700 rpm-glink {
701 compatible = "qcom,glink-rpm";
703 qcom,rpm-msg-ram = <&rpm_msg_ram>;
706 rpm_requests: glink-channel {
707 compatible = "qcom,rpm-ipq6018";
708 qcom,glink-channels = "rpm_requests";
711 compatible = "qcom,rpm-mp5496-regulators";
714 regulator-min-microvolt = <725000>;
715 regulator-max-microvolt = <1062500>;
716 regulator-always-on;