Lines Matching full:gcc
9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
191 clocks = <&gcc GCC_PRNG_AHB_CLK>;
199 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
210 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
211 <&gcc GCC_CRYPTO_AXI_CLK>,
212 <&gcc GCC_CRYPTO_CLK>;
247 gcc: gcc@1800000 { label
248 compatible = "qcom,gcc-ipq6018";
270 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
280 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
281 <&gcc GCC_BLSP1_AHB_CLK>;
293 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
294 <&gcc GCC_BLSP1_AHB_CLK>;
308 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
309 <&gcc GCC_BLSP1_AHB_CLK>;
322 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
323 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
337 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
338 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
350 clocks = <&gcc GCC_QPIC_CLK>,
351 <&gcc GCC_QPIC_AHB_CLK>;
363 clocks = <&gcc GCC_QPIC_CLK>,
364 <&gcc GCC_QPIC_AHB_CLK>;
395 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
396 <&gcc GCC_PCIE0_AHB_CLK>;
399 resets = <&gcc GCC_PCIE0_PHY_BCR>,
400 <&gcc GCC_PCIE0PHY_PHY_BCR>;
410 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
455 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
456 <&gcc GCC_PCIE0_AXI_M_CLK>,
457 <&gcc GCC_PCIE0_AXI_S_CLK>,
458 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
459 <&gcc PCIE0_RCHNG_CLK>;
466 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
467 <&gcc GCC_PCIE0_SLEEP_ARES>,
468 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
469 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
470 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
471 <&gcc GCC_PCIE0_AHB_ARES>,
472 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
473 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
595 resets = <&gcc GCC_WCSSAON_RESET>,
596 <&gcc GCC_WCSS_BCR>,
597 <&gcc GCC_WCSS_Q6_BCR>;
603 clocks = <&gcc GCC_PRNG_AHB_CLK>;
631 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
635 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
645 clocks = <&gcc GCC_USB1_MASTER_CLK>,
646 <&gcc GCC_USB1_SLEEP_CLK>,
647 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
652 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
653 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
656 resets = <&gcc GCC_USB1_BCR>;