Lines Matching +full:non +full:- +full:prefetchable
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include <dt-bindings/power/tegra194-powergate.h>
8 #include <dt-bindings/reset/tegra194-reset.h>
9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
10 #include <dt-bindings/memory/tegra194-mc.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
20 compatible = "simple-bus";
21 #address-cells = <1>;
22 #size-cells = <1>;
26 compatible = "nvidia,tegra194-misc";
32 compatible = "nvidia,tegra194-gpio";
33 reg-names = "security", "gpio";
42 #interrupt-cells = <2>;
43 interrupt-controller;
44 #gpio-cells = <2>;
45 gpio-controller;
49 compatible = "nvidia,tegra194-eqos",
50 "nvidia,tegra186-eqos",
51 "snps,dwc-qos-ethernet-4.10";
59 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
61 reset-names = "eqos";
64 interconnect-names = "dma-mem", "write";
68 snps,write-requests = <1>;
69 snps,read-requests = <3>;
70 snps,burst-map = <0x7>;
76 compatible = "nvidia,tegra194-aconnect",
77 "nvidia,tegra210-aconnect";
80 clock-names = "ape", "apb2ape";
81 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
82 #address-cells = <1>;
83 #size-cells = <1>;
87 adma: dma-controller@2930000 {
88 compatible = "nvidia,tegra194-adma",
89 "nvidia,tegra186-adma";
91 interrupt-parent = <&agic>;
124 #dma-cells = <1>;
126 clock-names = "d_audio";
130 agic: interrupt-controller@2a40000 {
131 compatible = "nvidia,tegra194-agic",
132 "nvidia,tegra210-agic";
133 #interrupt-cells = <3>;
134 interrupt-controller;
141 clock-names = "clk";
146 compatible = "nvidia,tegra194-ahub",
147 "nvidia,tegra186-ahub";
150 clock-names = "ahub";
151 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
152 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
153 #address-cells = <1>;
154 #size-cells = <1>;
159 compatible = "nvidia,tegra194-admaif",
160 "nvidia,tegra186-admaif";
182 dma-names = "rx1", "tx1",
206 compatible = "nvidia,tegra194-i2s",
207 "nvidia,tegra210-i2s";
211 clock-names = "i2s", "sync_input";
212 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
213 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
214 assigned-clock-rates = <1536000>;
215 sound-name-prefix = "I2S1";
220 compatible = "nvidia,tegra194-i2s",
221 "nvidia,tegra210-i2s";
225 clock-names = "i2s", "sync_input";
226 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
227 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
228 assigned-clock-rates = <1536000>;
229 sound-name-prefix = "I2S2";
234 compatible = "nvidia,tegra194-i2s",
235 "nvidia,tegra210-i2s";
239 clock-names = "i2s", "sync_input";
240 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
241 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
242 assigned-clock-rates = <1536000>;
243 sound-name-prefix = "I2S3";
248 compatible = "nvidia,tegra194-i2s",
249 "nvidia,tegra210-i2s";
253 clock-names = "i2s", "sync_input";
254 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
255 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
256 assigned-clock-rates = <1536000>;
257 sound-name-prefix = "I2S4";
262 compatible = "nvidia,tegra194-i2s",
263 "nvidia,tegra210-i2s";
267 clock-names = "i2s", "sync_input";
268 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
269 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
270 assigned-clock-rates = <1536000>;
271 sound-name-prefix = "I2S5";
276 compatible = "nvidia,tegra194-i2s",
277 "nvidia,tegra210-i2s";
281 clock-names = "i2s", "sync_input";
282 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
283 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
284 assigned-clock-rates = <1536000>;
285 sound-name-prefix = "I2S6";
290 compatible = "nvidia,tegra194-dmic",
291 "nvidia,tegra210-dmic";
294 clock-names = "dmic";
295 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
296 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
297 assigned-clock-rates = <3072000>;
298 sound-name-prefix = "DMIC1";
303 compatible = "nvidia,tegra194-dmic",
304 "nvidia,tegra210-dmic";
307 clock-names = "dmic";
308 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
309 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
310 assigned-clock-rates = <3072000>;
311 sound-name-prefix = "DMIC2";
316 compatible = "nvidia,tegra194-dmic",
317 "nvidia,tegra210-dmic";
320 clock-names = "dmic";
321 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
322 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
323 assigned-clock-rates = <3072000>;
324 sound-name-prefix = "DMIC3";
329 compatible = "nvidia,tegra194-dmic",
330 "nvidia,tegra210-dmic";
333 clock-names = "dmic";
334 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
335 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
336 assigned-clock-rates = <3072000>;
337 sound-name-prefix = "DMIC4";
342 compatible = "nvidia,tegra194-dspk",
343 "nvidia,tegra186-dspk";
346 clock-names = "dspk";
347 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
348 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
349 assigned-clock-rates = <12288000>;
350 sound-name-prefix = "DSPK1";
355 compatible = "nvidia,tegra194-dspk",
356 "nvidia,tegra186-dspk";
359 clock-names = "dspk";
360 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
361 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
362 assigned-clock-rates = <12288000>;
363 sound-name-prefix = "DSPK2";
370 compatible = "nvidia,tegra194-pinmux";
381 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
382 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
393 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
394 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
401 mc: memory-controller@2c00000 {
402 compatible = "nvidia,tegra194-mc";
407 #interconnect-cells = <1>;
410 #address-cells = <2>;
411 #size-cells = <2>;
432 dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
434 emc: external-memory-controller@2c60000 {
435 compatible = "nvidia,tegra194-emc";
439 clock-names = "emc";
441 #interconnect-cells = <0>;
448 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
450 reg-shift = <2>;
453 clock-names = "serial";
455 reset-names = "serial";
460 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
462 reg-shift = <2>;
465 clock-names = "serial";
467 reset-names = "serial";
472 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
474 reg-shift = <2>;
477 clock-names = "serial";
479 reset-names = "serial";
484 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
486 reg-shift = <2>;
489 clock-names = "serial";
491 reset-names = "serial";
496 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
498 reg-shift = <2>;
501 clock-names = "serial";
503 reset-names = "serial";
508 compatible = "nvidia,tegra194-i2c";
511 #address-cells = <1>;
512 #size-cells = <0>;
514 clock-names = "div-clk";
516 reset-names = "i2c";
521 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
523 reg-shift = <2>;
526 clock-names = "serial";
528 reset-names = "serial";
533 compatible = "nvidia,tegra194-i2c";
536 #address-cells = <1>;
537 #size-cells = <0>;
539 clock-names = "div-clk";
541 reset-names = "i2c";
547 compatible = "nvidia,tegra194-i2c";
550 #address-cells = <1>;
551 #size-cells = <0>;
553 clock-names = "div-clk";
555 reset-names = "i2c";
556 pinctrl-0 = <&state_dpaux1_i2c>;
557 pinctrl-1 = <&state_dpaux1_off>;
558 pinctrl-names = "default", "idle";
564 compatible = "nvidia,tegra194-i2c";
567 #address-cells = <1>;
568 #size-cells = <0>;
570 clock-names = "div-clk";
572 reset-names = "i2c";
573 pinctrl-0 = <&state_dpaux0_i2c>;
574 pinctrl-1 = <&state_dpaux0_off>;
575 pinctrl-names = "default", "idle";
581 compatible = "nvidia,tegra194-i2c";
584 #address-cells = <1>;
585 #size-cells = <0>;
587 clock-names = "div-clk";
589 reset-names = "i2c";
590 pinctrl-0 = <&state_dpaux2_i2c>;
591 pinctrl-1 = <&state_dpaux2_off>;
592 pinctrl-names = "default", "idle";
598 compatible = "nvidia,tegra194-i2c";
601 #address-cells = <1>;
602 #size-cells = <0>;
604 clock-names = "div-clk";
606 reset-names = "i2c";
607 pinctrl-0 = <&state_dpaux3_i2c>;
608 pinctrl-1 = <&state_dpaux3_off>;
609 pinctrl-names = "default", "idle";
614 compatible = "nvidia,tegra194-qspi";
617 #address-cells = <1>;
618 #size-cells = <0>;
621 clock-names = "qspi", "qspi_out";
623 reset-names = "qspi";
628 compatible = "nvidia,tegra194-qspi";
631 #address-cells = <1>;
632 #size-cells = <0>;
635 clock-names = "qspi", "qspi_out";
637 reset-names = "qspi";
642 compatible = "nvidia,tegra194-pwm",
643 "nvidia,tegra186-pwm";
646 clock-names = "pwm";
648 reset-names = "pwm";
650 #pwm-cells = <2>;
654 compatible = "nvidia,tegra194-pwm",
655 "nvidia,tegra186-pwm";
658 clock-names = "pwm";
660 reset-names = "pwm";
662 #pwm-cells = <2>;
666 compatible = "nvidia,tegra194-pwm",
667 "nvidia,tegra186-pwm";
670 clock-names = "pwm";
672 reset-names = "pwm";
674 #pwm-cells = <2>;
678 compatible = "nvidia,tegra194-pwm",
679 "nvidia,tegra186-pwm";
682 clock-names = "pwm";
684 reset-names = "pwm";
686 #pwm-cells = <2>;
690 compatible = "nvidia,tegra194-pwm",
691 "nvidia,tegra186-pwm";
694 clock-names = "pwm";
696 reset-names = "pwm";
698 #pwm-cells = <2>;
702 compatible = "nvidia,tegra194-pwm",
703 "nvidia,tegra186-pwm";
706 clock-names = "pwm";
708 reset-names = "pwm";
710 #pwm-cells = <2>;
714 compatible = "nvidia,tegra194-pwm",
715 "nvidia,tegra186-pwm";
718 clock-names = "pwm";
720 reset-names = "pwm";
722 #pwm-cells = <2>;
726 compatible = "nvidia,tegra194-sdhci";
731 clock-names = "sdhci", "tmclk";
733 reset-names = "sdhci";
736 interconnect-names = "dma-mem", "write";
738 nvidia,pad-autocal-pull-up-offset-3v3-timeout =
740 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
742 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
743 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
745 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
746 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
747 nvidia,default-tap = <0x9>;
748 nvidia,default-trim = <0x5>;
753 compatible = "nvidia,tegra194-sdhci";
758 clock-names = "sdhci", "tmclk";
760 reset-names = "sdhci";
763 interconnect-names = "dma-mem", "write";
765 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
766 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
767 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
768 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
770 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
771 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
773 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
774 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
775 nvidia,default-tap = <0x9>;
776 nvidia,default-trim = <0x5>;
781 compatible = "nvidia,tegra194-sdhci";
786 clock-names = "sdhci", "tmclk";
787 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
789 assigned-clock-parents =
792 reset-names = "sdhci";
795 interconnect-names = "dma-mem", "write";
797 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
798 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
799 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
800 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
802 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
803 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
805 nvidia,default-tap = <0x8>;
806 nvidia,default-trim = <0x14>;
807 nvidia,dqs-trim = <40>;
808 supports-cqe;
813 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
819 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
823 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
824 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
827 interconnect-names = "dma-mem", "write";
833 compatible = "nvidia,tegra194-xusb-padctl";
836 reg-names = "padctl", "ao";
840 reset-names = "padctl";
847 clock-names = "trk";
850 usb2-0 {
853 #phy-cells = <0>;
856 usb2-1 {
859 #phy-cells = <0>;
862 usb2-2 {
865 #phy-cells = <0>;
868 usb2-3 {
871 #phy-cells = <0>;
878 usb3-0 {
881 #phy-cells = <0>;
884 usb3-1 {
887 #phy-cells = <0>;
890 usb3-2 {
893 #phy-cells = <0>;
896 usb3-3 {
899 #phy-cells = <0>;
906 usb2-0 {
910 usb2-1 {
914 usb2-2 {
918 usb2-3 {
922 usb3-0 {
926 usb3-1 {
930 usb3-2 {
934 usb3-3 {
941 compatible = "nvidia,tegra194-xudc";
944 reg-names = "base", "fpci";
950 clock-names = "dev", "ss", "ss_src", "fs_src";
953 interconnect-names = "dma-mem", "write";
955 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
957 power-domain-names = "dev", "ss";
958 nvidia,xusb-padctl = <&xusb_padctl>;
963 compatible = "nvidia,tegra194-xusb";
966 reg-names = "hcd", "fpci";
980 clock-names = "xusb_host", "xusb_falcon_src",
986 interconnect-names = "dma-mem", "write";
989 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
991 power-domain-names = "xusb_host", "xusb_ss";
993 nvidia,xusb-padctl = <&xusb_padctl>;
998 compatible = "nvidia,tegra194-efuse";
1001 clock-names = "fuse";
1004 gic: interrupt-controller@3881000 {
1005 compatible = "arm,gic-400";
1006 #interrupt-cells = <3>;
1007 interrupt-controller;
1014 interrupt-parent = <&gic>;
1018 compatible = "nvidia,tegra194-cec";
1022 clock-names = "cec";
1027 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
1038 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1041 #mbox-cells = <2>;
1045 compatible = "nvidia,tegra194-p2u";
1047 reg-names = "ctl";
1049 #phy-cells = <0>;
1053 compatible = "nvidia,tegra194-p2u";
1055 reg-names = "ctl";
1057 #phy-cells = <0>;
1061 compatible = "nvidia,tegra194-p2u";
1063 reg-names = "ctl";
1065 #phy-cells = <0>;
1069 compatible = "nvidia,tegra194-p2u";
1071 reg-names = "ctl";
1073 #phy-cells = <0>;
1077 compatible = "nvidia,tegra194-p2u";
1079 reg-names = "ctl";
1081 #phy-cells = <0>;
1085 compatible = "nvidia,tegra194-p2u";
1087 reg-names = "ctl";
1089 #phy-cells = <0>;
1093 compatible = "nvidia,tegra194-p2u";
1095 reg-names = "ctl";
1097 #phy-cells = <0>;
1101 compatible = "nvidia,tegra194-p2u";
1103 reg-names = "ctl";
1105 #phy-cells = <0>;
1109 compatible = "nvidia,tegra194-p2u";
1111 reg-names = "ctl";
1113 #phy-cells = <0>;
1117 compatible = "nvidia,tegra194-p2u";
1119 reg-names = "ctl";
1121 #phy-cells = <0>;
1125 compatible = "nvidia,tegra194-p2u";
1127 reg-names = "ctl";
1129 #phy-cells = <0>;
1133 compatible = "nvidia,tegra194-p2u";
1135 reg-names = "ctl";
1137 #phy-cells = <0>;
1141 compatible = "nvidia,tegra194-p2u";
1143 reg-names = "ctl";
1145 #phy-cells = <0>;
1149 compatible = "nvidia,tegra194-p2u";
1151 reg-names = "ctl";
1153 #phy-cells = <0>;
1157 compatible = "nvidia,tegra194-p2u";
1159 reg-names = "ctl";
1161 #phy-cells = <0>;
1165 compatible = "nvidia,tegra194-p2u";
1167 reg-names = "ctl";
1169 #phy-cells = <0>;
1173 compatible = "nvidia,tegra194-p2u";
1175 reg-names = "ctl";
1177 #phy-cells = <0>;
1181 compatible = "nvidia,tegra194-p2u";
1183 reg-names = "ctl";
1185 #phy-cells = <0>;
1189 compatible = "nvidia,tegra194-p2u";
1191 reg-names = "ctl";
1193 #phy-cells = <0>;
1197 compatible = "nvidia,tegra194-p2u";
1199 reg-names = "ctl";
1201 #phy-cells = <0>;
1205 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
1215 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1216 #mbox-cells = <2>;
1220 compatible = "nvidia,tegra194-i2c";
1223 #address-cells = <1>;
1224 #size-cells = <0>;
1226 clock-names = "div-clk";
1228 reset-names = "i2c";
1233 compatible = "nvidia,tegra194-i2c";
1236 #address-cells = <1>;
1237 #size-cells = <0>;
1239 clock-names = "div-clk";
1241 reset-names = "i2c";
1246 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1248 reg-shift = <2>;
1251 clock-names = "serial";
1253 reset-names = "serial";
1258 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1260 reg-shift = <2>;
1263 clock-names = "serial";
1265 reset-names = "serial";
1270 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1272 interrupt-parent = <&pmc>;
1275 clock-names = "rtc";
1280 compatible = "nvidia,tegra194-gpio-aon";
1281 reg-names = "security", "gpio";
1285 gpio-controller;
1286 #gpio-cells = <2>;
1287 interrupt-controller;
1288 #interrupt-cells = <2>;
1292 compatible = "nvidia,tegra194-pwm",
1293 "nvidia,tegra186-pwm";
1296 clock-names = "pwm";
1298 reset-names = "pwm";
1300 #pwm-cells = <2>;
1304 compatible = "nvidia,tegra194-pmc";
1310 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1312 #interrupt-cells = <2>;
1313 interrupt-controller;
1317 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1386 stream-match-mask = <0x7f80>;
1387 #global-interrupts = <2>;
1388 #iommu-cells = <1>;
1390 nvidia,memory-controller = <&mc>;
1395 compatible = "nvidia,tegra194-host1x";
1398 reg-names = "hypervisor", "vm";
1401 interrupt-names = "syncpt", "host1x";
1403 clock-names = "host1x";
1405 reset-names = "host1x";
1407 #address-cells = <1>;
1408 #size-cells = <1>;
1412 interconnect-names = "dma-mem";
1415 display-hub@15200000 {
1416 compatible = "nvidia,tegra194-display";
1425 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1429 clock-names = "disp", "hub";
1432 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1434 #address-cells = <1>;
1435 #size-cells = <1>;
1440 compatible = "nvidia,tegra194-dc";
1444 clock-names = "dc";
1446 reset-names = "dc";
1448 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1451 interconnect-names = "dma-mem", "read-1";
1458 compatible = "nvidia,tegra194-dc";
1462 clock-names = "dc";
1464 reset-names = "dc";
1466 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1469 interconnect-names = "dma-mem", "read-1";
1476 compatible = "nvidia,tegra194-dc";
1480 clock-names = "dc";
1482 reset-names = "dc";
1484 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1487 interconnect-names = "dma-mem", "read-1";
1494 compatible = "nvidia,tegra194-dc";
1498 clock-names = "dc";
1500 reset-names = "dc";
1502 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1505 interconnect-names = "dma-mem", "read-1";
1513 compatible = "nvidia,tegra194-vic";
1517 clock-names = "vic";
1519 reset-names = "vic";
1521 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
1524 interconnect-names = "dma-mem", "write";
1529 compatible = "nvidia,tegra194-dpaux";
1534 clock-names = "dpaux", "parent";
1536 reset-names = "dpaux";
1539 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1541 state_dpaux0_aux: pinmux-aux {
1542 groups = "dpaux-io";
1546 state_dpaux0_i2c: pinmux-i2c {
1547 groups = "dpaux-io";
1551 state_dpaux0_off: pinmux-off {
1552 groups = "dpaux-io";
1556 i2c-bus {
1557 #address-cells = <1>;
1558 #size-cells = <0>;
1563 compatible = "nvidia,tegra194-dpaux";
1568 clock-names = "dpaux", "parent";
1570 reset-names = "dpaux";
1573 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1575 state_dpaux1_aux: pinmux-aux {
1576 groups = "dpaux-io";
1580 state_dpaux1_i2c: pinmux-i2c {
1581 groups = "dpaux-io";
1585 state_dpaux1_off: pinmux-off {
1586 groups = "dpaux-io";
1590 i2c-bus {
1591 #address-cells = <1>;
1592 #size-cells = <0>;
1597 compatible = "nvidia,tegra194-dpaux";
1602 clock-names = "dpaux", "parent";
1604 reset-names = "dpaux";
1607 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1609 state_dpaux2_aux: pinmux-aux {
1610 groups = "dpaux-io";
1614 state_dpaux2_i2c: pinmux-i2c {
1615 groups = "dpaux-io";
1619 state_dpaux2_off: pinmux-off {
1620 groups = "dpaux-io";
1624 i2c-bus {
1625 #address-cells = <1>;
1626 #size-cells = <0>;
1631 compatible = "nvidia,tegra194-dpaux";
1636 clock-names = "dpaux", "parent";
1638 reset-names = "dpaux";
1641 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1643 state_dpaux3_aux: pinmux-aux {
1644 groups = "dpaux-io";
1648 state_dpaux3_i2c: pinmux-i2c {
1649 groups = "dpaux-io";
1653 state_dpaux3_off: pinmux-off {
1654 groups = "dpaux-io";
1658 i2c-bus {
1659 #address-cells = <1>;
1660 #size-cells = <0>;
1665 compatible = "nvidia,tegra194-sor";
1674 clock-names = "sor", "out", "parent", "dp", "safe",
1677 reset-names = "sor";
1678 pinctrl-0 = <&state_dpaux0_aux>;
1679 pinctrl-1 = <&state_dpaux0_i2c>;
1680 pinctrl-2 = <&state_dpaux0_off>;
1681 pinctrl-names = "aux", "i2c", "off";
1684 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1689 compatible = "nvidia,tegra194-sor";
1698 clock-names = "sor", "out", "parent", "dp", "safe",
1701 reset-names = "sor";
1702 pinctrl-0 = <&state_dpaux1_aux>;
1703 pinctrl-1 = <&state_dpaux1_i2c>;
1704 pinctrl-2 = <&state_dpaux1_off>;
1705 pinctrl-names = "aux", "i2c", "off";
1708 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1713 compatible = "nvidia,tegra194-sor";
1722 clock-names = "sor", "out", "parent", "dp", "safe",
1725 reset-names = "sor";
1726 pinctrl-0 = <&state_dpaux2_aux>;
1727 pinctrl-1 = <&state_dpaux2_i2c>;
1728 pinctrl-2 = <&state_dpaux2_off>;
1729 pinctrl-names = "aux", "i2c", "off";
1732 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1737 compatible = "nvidia,tegra194-sor";
1746 clock-names = "sor", "out", "parent", "dp", "safe",
1749 reset-names = "sor";
1750 pinctrl-0 = <&state_dpaux3_aux>;
1751 pinctrl-1 = <&state_dpaux3_i2c>;
1752 pinctrl-2 = <&state_dpaux3_off>;
1753 pinctrl-names = "aux", "i2c", "off";
1756 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1767 interrupt-names = "stall", "nonstall";
1771 clock-names = "gpu", "pwr", "fuse";
1773 reset-names = "gpu";
1774 dma-coherent;
1776 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
1789 interconnect-names = "dma-mem", "read-0-hp", "write-0",
1790 "read-1", "read-1-hp", "write-1",
1791 "read-2", "read-2-hp", "write-2",
1792 "read-3", "read-3-hp", "write-3";
1797 compatible = "nvidia,tegra194-pcie";
1798 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1803 reg-names = "appl", "config", "atu_dma", "dbi";
1807 #address-cells = <3>;
1808 #size-cells = <2>;
1810 num-lanes = <1>;
1811 num-viewport = <8>;
1812 linux,pci-domain = <1>;
1815 clock-names = "core";
1819 reset-names = "apb", "core";
1823 interrupt-names = "intr", "msi";
1825 #interrupt-cells = <1>;
1826 interrupt-map-mask = <0 0 0 0>;
1827 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1831 nvidia,aspm-cmrt-us = <60>;
1832 nvidia,aspm-pwr-on-t-us = <20>;
1833 nvidia,aspm-l0s-entrance-latency-us = <3>;
1835 bus-range = <0x0 0xff>;
1837 …ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 …
1838 …000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 K…
1843 interconnect-names = "dma-mem", "write";
1845 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
1846 iommu-map-mask = <0x0>;
1847 dma-coherent;
1851 compatible = "nvidia,tegra194-pcie";
1852 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1857 reg-names = "appl", "config", "atu_dma", "dbi";
1861 #address-cells = <3>;
1862 #size-cells = <2>;
1864 num-lanes = <1>;
1865 num-viewport = <8>;
1866 linux,pci-domain = <2>;
1869 clock-names = "core";
1873 reset-names = "apb", "core";
1877 interrupt-names = "intr", "msi";
1879 #interrupt-cells = <1>;
1880 interrupt-map-mask = <0 0 0 0>;
1881 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1885 nvidia,aspm-cmrt-us = <60>;
1886 nvidia,aspm-pwr-on-t-us = <20>;
1887 nvidia,aspm-l0s-entrance-latency-us = <3>;
1889 bus-range = <0x0 0xff>;
1891 …ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 …
1892 …000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 K…
1897 interconnect-names = "dma-mem", "write";
1899 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
1900 iommu-map-mask = <0x0>;
1901 dma-coherent;
1905 compatible = "nvidia,tegra194-pcie";
1906 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1911 reg-names = "appl", "config", "atu_dma", "dbi";
1915 #address-cells = <3>;
1916 #size-cells = <2>;
1918 num-lanes = <1>;
1919 num-viewport = <8>;
1920 linux,pci-domain = <3>;
1923 clock-names = "core";
1927 reset-names = "apb", "core";
1931 interrupt-names = "intr", "msi";
1933 #interrupt-cells = <1>;
1934 interrupt-map-mask = <0 0 0 0>;
1935 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1939 nvidia,aspm-cmrt-us = <60>;
1940 nvidia,aspm-pwr-on-t-us = <20>;
1941 nvidia,aspm-l0s-entrance-latency-us = <3>;
1943 bus-range = <0x0 0xff>;
1945 …ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 …
1946 …<0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB +…
1951 interconnect-names = "dma-mem", "write";
1953 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
1954 iommu-map-mask = <0x0>;
1955 dma-coherent;
1959 compatible = "nvidia,tegra194-pcie";
1960 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1965 reg-names = "appl", "config", "atu_dma", "dbi";
1969 #address-cells = <3>;
1970 #size-cells = <2>;
1972 num-lanes = <4>;
1973 num-viewport = <8>;
1974 linux,pci-domain = <4>;
1977 clock-names = "core";
1981 reset-names = "apb", "core";
1985 interrupt-names = "intr", "msi";
1987 #interrupt-cells = <1>;
1988 interrupt-map-mask = <0 0 0 0>;
1989 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1993 nvidia,aspm-cmrt-us = <60>;
1994 nvidia,aspm-pwr-on-t-us = <20>;
1995 nvidia,aspm-l0s-entrance-latency-us = <3>;
1997 bus-range = <0x0 0xff>;
1999 …ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 G…
2000 …2000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 Ki…
2005 interconnect-names = "dma-mem", "write";
2007 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2008 iommu-map-mask = <0x0>;
2009 dma-coherent;
2013 compatible = "nvidia,tegra194-pcie";
2014 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2019 reg-names = "appl", "config", "atu_dma", "dbi";
2023 #address-cells = <3>;
2024 #size-cells = <2>;
2026 num-lanes = <8>;
2027 num-viewport = <8>;
2028 linux,pci-domain = <0>;
2031 clock-names = "core";
2035 reset-names = "apb", "core";
2039 interrupt-names = "intr", "msi";
2041 #interrupt-cells = <1>;
2042 interrupt-map-mask = <0 0 0 0>;
2043 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2047 nvidia,aspm-cmrt-us = <60>;
2048 nvidia,aspm-pwr-on-t-us = <20>;
2049 nvidia,aspm-l0s-entrance-latency-us = <3>;
2051 bus-range = <0x0 0xff>;
2053 …ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 G…
2054 …2000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 Ki…
2059 interconnect-names = "dma-mem", "write";
2061 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2062 iommu-map-mask = <0x0>;
2063 dma-coherent;
2067 compatible = "nvidia,tegra194-pcie";
2068 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2073 reg-names = "appl", "config", "atu_dma", "dbi";
2077 #address-cells = <3>;
2078 #size-cells = <2>;
2080 num-lanes = <8>;
2081 num-viewport = <8>;
2082 linux,pci-domain = <5>;
2084 pinctrl-names = "default";
2085 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
2089 clock-names = "core", "core_m";
2093 reset-names = "apb", "core";
2097 interrupt-names = "intr", "msi";
2101 #interrupt-cells = <1>;
2102 interrupt-map-mask = <0 0 0 0>;
2103 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2105 nvidia,aspm-cmrt-us = <60>;
2106 nvidia,aspm-pwr-on-t-us = <20>;
2107 nvidia,aspm-l0s-entrance-latency-us = <3>;
2109 bus-range = <0x0 0xff>;
2111 …ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 G…
2112 …2000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 Ki…
2117 interconnect-names = "dma-mem", "write";
2119 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2120 iommu-map-mask = <0x0>;
2121 dma-coherent;
2125 compatible = "nvidia,tegra194-pcie-ep";
2126 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2131 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2135 num-lanes = <4>;
2136 num-ib-windows = <2>;
2137 num-ob-windows = <8>;
2140 clock-names = "core";
2144 reset-names = "apb", "core";
2147 interrupt-names = "intr";
2151 nvidia,aspm-cmrt-us = <60>;
2152 nvidia,aspm-pwr-on-t-us = <20>;
2153 nvidia,aspm-l0s-entrance-latency-us = <3>;
2157 interconnect-names = "dma-mem", "write";
2159 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2160 iommu-map-mask = <0x0>;
2161 dma-coherent;
2165 compatible = "nvidia,tegra194-pcie-ep";
2166 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2171 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2175 num-lanes = <8>;
2176 num-ib-windows = <2>;
2177 num-ob-windows = <8>;
2180 clock-names = "core";
2184 reset-names = "apb", "core";
2187 interrupt-names = "intr";
2191 nvidia,aspm-cmrt-us = <60>;
2192 nvidia,aspm-pwr-on-t-us = <20>;
2193 nvidia,aspm-l0s-entrance-latency-us = <3>;
2197 interconnect-names = "dma-mem", "write";
2199 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2200 iommu-map-mask = <0x0>;
2201 dma-coherent;
2205 compatible = "nvidia,tegra194-pcie-ep";
2206 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2211 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2215 num-lanes = <8>;
2216 num-ib-windows = <2>;
2217 num-ob-windows = <8>;
2219 pinctrl-names = "default";
2220 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
2223 clock-names = "core";
2227 reset-names = "apb", "core";
2230 interrupt-names = "intr";
2234 nvidia,aspm-cmrt-us = <60>;
2235 nvidia,aspm-pwr-on-t-us = <20>;
2236 nvidia,aspm-l0s-entrance-latency-us = <3>;
2240 interconnect-names = "dma-mem", "write";
2242 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2243 iommu-map-mask = <0x0>;
2244 dma-coherent;
2248 compatible = "nvidia,tegra194-sysram", "mmio-sram";
2250 #address-cells = <1>;
2251 #size-cells = <1>;
2256 label = "cpu-bpmp-tx";
2262 label = "cpu-bpmp-rx";
2268 compatible = "nvidia,tegra186-bpmp";
2272 #clock-cells = <1>;
2273 #reset-cells = <1>;
2274 #power-domain-cells = <1>;
2279 interconnect-names = "read", "write", "dma-mem", "dma-write";
2283 compatible = "nvidia,tegra186-bpmp-i2c";
2284 nvidia,bpmp-bus-id = <5>;
2285 #address-cells = <1>;
2286 #size-cells = <0>;
2290 compatible = "nvidia,tegra186-bpmp-thermal";
2291 #thermal-sensor-cells = <1>;
2296 compatible = "nvidia,tegra194-ccplex";
2298 #address-cells = <1>;
2299 #size-cells = <0>;
2302 compatible = "nvidia,tegra194-carmel";
2305 enable-method = "psci";
2306 i-cache-size = <131072>;
2307 i-cache-line-size = <64>;
2308 i-cache-sets = <512>;
2309 d-cache-size = <65536>;
2310 d-cache-line-size = <64>;
2311 d-cache-sets = <256>;
2312 next-level-cache = <&l2c_0>;
2316 compatible = "nvidia,tegra194-carmel";
2319 enable-method = "psci";
2320 i-cache-size = <131072>;
2321 i-cache-line-size = <64>;
2322 i-cache-sets = <512>;
2323 d-cache-size = <65536>;
2324 d-cache-line-size = <64>;
2325 d-cache-sets = <256>;
2326 next-level-cache = <&l2c_0>;
2330 compatible = "nvidia,tegra194-carmel";
2333 enable-method = "psci";
2334 i-cache-size = <131072>;
2335 i-cache-line-size = <64>;
2336 i-cache-sets = <512>;
2337 d-cache-size = <65536>;
2338 d-cache-line-size = <64>;
2339 d-cache-sets = <256>;
2340 next-level-cache = <&l2c_1>;
2344 compatible = "nvidia,tegra194-carmel";
2347 enable-method = "psci";
2348 i-cache-size = <131072>;
2349 i-cache-line-size = <64>;
2350 i-cache-sets = <512>;
2351 d-cache-size = <65536>;
2352 d-cache-line-size = <64>;
2353 d-cache-sets = <256>;
2354 next-level-cache = <&l2c_1>;
2358 compatible = "nvidia,tegra194-carmel";
2361 enable-method = "psci";
2362 i-cache-size = <131072>;
2363 i-cache-line-size = <64>;
2364 i-cache-sets = <512>;
2365 d-cache-size = <65536>;
2366 d-cache-line-size = <64>;
2367 d-cache-sets = <256>;
2368 next-level-cache = <&l2c_2>;
2372 compatible = "nvidia,tegra194-carmel";
2375 enable-method = "psci";
2376 i-cache-size = <131072>;
2377 i-cache-line-size = <64>;
2378 i-cache-sets = <512>;
2379 d-cache-size = <65536>;
2380 d-cache-line-size = <64>;
2381 d-cache-sets = <256>;
2382 next-level-cache = <&l2c_2>;
2386 compatible = "nvidia,tegra194-carmel";
2389 enable-method = "psci";
2390 i-cache-size = <131072>;
2391 i-cache-line-size = <64>;
2392 i-cache-sets = <512>;
2393 d-cache-size = <65536>;
2394 d-cache-line-size = <64>;
2395 d-cache-sets = <256>;
2396 next-level-cache = <&l2c_3>;
2400 compatible = "nvidia,tegra194-carmel";
2403 enable-method = "psci";
2404 i-cache-size = <131072>;
2405 i-cache-line-size = <64>;
2406 i-cache-sets = <512>;
2407 d-cache-size = <65536>;
2408 d-cache-line-size = <64>;
2409 d-cache-sets = <256>;
2410 next-level-cache = <&l2c_3>;
2413 cpu-map {
2455 l2c_0: l2-cache0 {
2456 cache-size = <2097152>;
2457 cache-line-size = <64>;
2458 cache-sets = <2048>;
2459 next-level-cache = <&l3c>;
2462 l2c_1: l2-cache1 {
2463 cache-size = <2097152>;
2464 cache-line-size = <64>;
2465 cache-sets = <2048>;
2466 next-level-cache = <&l3c>;
2469 l2c_2: l2-cache2 {
2470 cache-size = <2097152>;
2471 cache-line-size = <64>;
2472 cache-sets = <2048>;
2473 next-level-cache = <&l3c>;
2476 l2c_3: l2-cache3 {
2477 cache-size = <2097152>;
2478 cache-line-size = <64>;
2479 cache-sets = <2048>;
2480 next-level-cache = <&l3c>;
2483 l3c: l3-cache {
2484 cache-size = <4194304>;
2485 cache-line-size = <64>;
2486 cache-sets = <4096>;
2491 compatible = "arm,armv8-pmuv3";
2500 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
2505 compatible = "arm,psci-1.0";
2515 clock-names = "pll_a", "plla_out0";
2516 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>,
2519 assigned-clock-parents = <0>,
2527 assigned-clock-rates = <258000000>;
2531 interconnect-names = "dma-mem", "write";
2536 compatible = "nvidia,tegra194-tcu";
2539 mbox-names = "rx", "tx";
2542 thermal-zones {
2544 thermal-sensors = <&{/bpmp/thermal}
2550 thermal-sensors = <&{/bpmp/thermal}
2556 thermal-sensors = <&{/bpmp/thermal}
2562 thermal-sensors = <&{/bpmp/thermal}
2568 thermal-sensors = <&{/bpmp/thermal}
2574 thermal-sensors = <&{/bpmp/thermal}
2581 compatible = "arm,armv8-timer";
2590 interrupt-parent = <&gic>;
2591 always-on;