Lines Matching +full:0 +full:x34000000
19 bus@0 {
23 ranges = <0x0 0x0 0x0 0x40000000>;
27 reg = <0x00100000 0xf000>,
28 <0x0010f000 0x1000>;
34 reg = <0x2200000 0x10000>,
35 <0x2210000 0x10000>;
52 reg = <0x02490000 0x10000>;
70 snps,burst-map = <0x7>;
84 ranges = <0x02900000 0x02900000 0x200000>;
90 reg = <0x02930000 0x20000>;
92 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
135 reg = <0x02a41000 0x1000>,
136 <0x02a42000 0x2000>;
148 reg = <0x02900800 0x800>;
155 ranges = <0x02900800 0x02900800 0x11800>;
161 reg = <0x0290f000 0x1000>;
208 reg = <0x2901000 0x100>;
222 reg = <0x2901100 0x100>;
236 reg = <0x2901200 0x100>;
250 reg = <0x2901300 0x100>;
264 reg = <0x2901400 0x100>;
278 reg = <0x2901500 0x100>;
292 reg = <0x2904000 0x100>;
305 reg = <0x2904100 0x100>;
318 reg = <0x2904200 0x100>;
331 reg = <0x2904300 0x100>;
344 reg = <0x2905000 0x100>;
357 reg = <0x2905100 0x100>;
371 reg = <0x2430000 0x17000>,
372 <0xc300000 0x4000>;
403 reg = <0x02c00000 0x100000>,
404 <0x02b80000 0x040000>,
405 <0x01700000 0x100000>;
413 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
414 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
415 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
430 * Limit the DMA range for memory clients to [38:0].
432 dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
436 reg = <0x0 0x02c60000 0x0 0x90000>,
437 <0x0 0x01780000 0x0 0x80000>;
441 #interconnect-cells = <0>;
449 reg = <0x03100000 0x40>;
461 reg = <0x03110000 0x40>;
473 reg = <0x03130000 0x40>;
485 reg = <0x03140000 0x40>;
497 reg = <0x03150000 0x40>;
509 reg = <0x03160000 0x10000>;
512 #size-cells = <0>;
522 reg = <0x03170000 0x40>;
534 reg = <0x03180000 0x10000>;
537 #size-cells = <0>;
548 reg = <0x03190000 0x10000>;
551 #size-cells = <0>;
556 pinctrl-0 = <&state_dpaux1_i2c>;
565 reg = <0x031b0000 0x10000>;
568 #size-cells = <0>;
573 pinctrl-0 = <&state_dpaux0_i2c>;
582 reg = <0x031c0000 0x10000>;
585 #size-cells = <0>;
590 pinctrl-0 = <&state_dpaux2_i2c>;
599 reg = <0x031e0000 0x10000>;
602 #size-cells = <0>;
607 pinctrl-0 = <&state_dpaux3_i2c>;
615 reg = <0x3270000 0x1000>;
618 #size-cells = <0>;
629 reg = <0x3300000 0x1000>;
632 #size-cells = <0>;
644 reg = <0x3280000 0x10000>;
656 reg = <0x3290000 0x10000>;
668 reg = <0x32a0000 0x10000>;
680 reg = <0x32c0000 0x10000>;
692 reg = <0x32d0000 0x10000>;
704 reg = <0x32e0000 0x10000>;
716 reg = <0x32f0000 0x10000>;
727 reg = <0x03400000 0x10000>;
739 <0x07>;
741 <0x07>;
742 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
744 <0x07>;
745 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
746 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
747 nvidia,default-tap = <0x9>;
748 nvidia,default-trim = <0x5>;
754 reg = <0x03440000 0x10000>;
765 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
766 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
767 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
769 <0x07>;
770 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
772 <0x07>;
773 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
774 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
775 nvidia,default-tap = <0x9>;
776 nvidia,default-trim = <0x5>;
782 reg = <0x03460000 0x10000>;
797 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
798 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
799 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
801 <0x0a>;
802 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
804 <0x0a>;
805 nvidia,default-tap = <0x8>;
806 nvidia,default-trim = <0x14>;
814 reg = <0x3510000 0x10000>;
834 reg = <0x03520000 0x1000>,
835 <0x03540000 0x1000>;
850 usb2-0 {
853 #phy-cells = <0>;
859 #phy-cells = <0>;
865 #phy-cells = <0>;
871 #phy-cells = <0>;
878 usb3-0 {
881 #phy-cells = <0>;
887 #phy-cells = <0>;
893 #phy-cells = <0>;
899 #phy-cells = <0>;
906 usb2-0 {
922 usb3-0 {
942 reg = <0x03550000 0x8000>,
943 <0x03558000 0x1000>;
964 reg = <0x03610000 0x40000>,
965 <0x03600000 0x10000>;
999 reg = <0x03820000 0x10000>;
1008 reg = <0x03881000 0x1000>,
1009 <0x03882000 0x2000>,
1010 <0x03884000 0x2000>,
1011 <0x03886000 0x2000>;
1019 reg = <0x03960000 0x10000>;
1028 reg = <0x03c00000 0xa0000>;
1046 reg = <0x03e10000 0x10000>;
1049 #phy-cells = <0>;
1054 reg = <0x03e20000 0x10000>;
1057 #phy-cells = <0>;
1062 reg = <0x03e30000 0x10000>;
1065 #phy-cells = <0>;
1070 reg = <0x03e40000 0x10000>;
1073 #phy-cells = <0>;
1078 reg = <0x03e50000 0x10000>;
1081 #phy-cells = <0>;
1086 reg = <0x03e60000 0x10000>;
1089 #phy-cells = <0>;
1094 reg = <0x03e70000 0x10000>;
1097 #phy-cells = <0>;
1102 reg = <0x03e80000 0x10000>;
1105 #phy-cells = <0>;
1110 reg = <0x03e90000 0x10000>;
1113 #phy-cells = <0>;
1118 reg = <0x03ea0000 0x10000>;
1121 #phy-cells = <0>;
1126 reg = <0x03eb0000 0x10000>;
1129 #phy-cells = <0>;
1134 reg = <0x03ec0000 0x10000>;
1137 #phy-cells = <0>;
1142 reg = <0x03ed0000 0x10000>;
1145 #phy-cells = <0>;
1150 reg = <0x03ee0000 0x10000>;
1153 #phy-cells = <0>;
1158 reg = <0x03ef0000 0x10000>;
1161 #phy-cells = <0>;
1166 reg = <0x03f00000 0x10000>;
1169 #phy-cells = <0>;
1174 reg = <0x03f10000 0x10000>;
1177 #phy-cells = <0>;
1182 reg = <0x03f20000 0x10000>;
1185 #phy-cells = <0>;
1190 reg = <0x03f30000 0x10000>;
1193 #phy-cells = <0>;
1198 reg = <0x03f40000 0x10000>;
1201 #phy-cells = <0>;
1206 reg = <0x0c150000 0x90000>;
1212 * Shared interrupt 0 is routed only to AON/SPE, so
1221 reg = <0x0c240000 0x10000>;
1224 #size-cells = <0>;
1234 reg = <0x0c250000 0x10000>;
1237 #size-cells = <0>;
1247 reg = <0x0c280000 0x40>;
1259 reg = <0x0c290000 0x40>;
1271 reg = <0x0c2a0000 0x10000>;
1282 reg = <0xc2f0000 0x1000>,
1283 <0xc2f1000 0x1000>;
1294 reg = <0xc340000 0x10000>;
1305 reg = <0x0c360000 0x10000>,
1306 <0x0c370000 0x10000>,
1307 <0x0c380000 0x10000>,
1308 <0x0c390000 0x10000>,
1309 <0x0c3a0000 0x10000>;
1318 reg = <0x12000000 0x800000>,
1319 <0x11000000 0x800000>;
1386 stream-match-mask = <0x7f80>;
1396 reg = <0x13e00000 0x10000>,
1397 <0x13e10000 0x10000>;
1410 ranges = <0x15000000 0x15000000 0x01000000>;
1417 reg = <0x15200000 0x00040000>;
1437 ranges = <0x15200000 0x15200000 0x40000>;
1441 reg = <0x15200000 0x10000>;
1454 nvidia,head = <0>;
1459 reg = <0x15210000 0x10000>;
1477 reg = <0x15220000 0x10000>;
1495 reg = <0x15230000 0x10000>;
1514 reg = <0x15340000 0x00040000>;
1530 reg = <0x155c0000 0x10000>;
1558 #size-cells = <0>;
1564 reg = <0x155d0000 0x10000>;
1592 #size-cells = <0>;
1598 reg = <0x155e0000 0x10000>;
1626 #size-cells = <0>;
1632 reg = <0x155f0000 0x10000>;
1660 #size-cells = <0>;
1666 reg = <0x15b00000 0x40000>;
1678 pinctrl-0 = <&state_dpaux0_aux>;
1685 nvidia,interface = <0>;
1690 reg = <0x15b40000 0x40000>;
1702 pinctrl-0 = <&state_dpaux1_aux>;
1714 reg = <0x15b80000 0x40000>;
1726 pinctrl-0 = <&state_dpaux2_aux>;
1738 reg = <0x15bc0000 0x40000>;
1750 pinctrl-0 = <&state_dpaux3_aux>;
1763 reg = <0x17000000 0x1000000>,
1764 <0x18000000 0x1000000>;
1789 interconnect-names = "dma-mem", "read-0-hp", "write-0",
1799 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
1800 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
1801 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1802 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
1826 interrupt-map-mask = <0 0 0 0>;
1827 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1835 bus-range = <0x0 0xff>;
1837 …ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 …
1838 …<0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB -…
1839 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1845 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
1846 iommu-map-mask = <0x0>;
1853 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
1854 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
1855 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1856 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
1880 interrupt-map-mask = <0 0 0 0>;
1881 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1889 bus-range = <0x0 0xff>;
1891 …ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 …
1892 …<0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB -…
1893 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1899 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
1900 iommu-map-mask = <0x0>;
1907 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
1908 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
1909 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1910 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
1934 interrupt-map-mask = <0 0 0 0>;
1935 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1943 bus-range = <0x0 0xff>;
1945 …ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 …
1946 …<0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB +…
1947 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1953 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
1954 iommu-map-mask = <0x0>;
1961 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
1962 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
1963 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1964 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
1988 interrupt-map-mask = <0 0 0 0>;
1989 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1997 bus-range = <0x0 0xff>;
1999 …ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 G…
2000 …<0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 6…
2001 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2007 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2008 iommu-map-mask = <0x0>;
2015 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2016 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
2017 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2018 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
2028 linux,pci-domain = <0>;
2042 interrupt-map-mask = <0 0 0 0>;
2043 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2045 nvidia,bpmp = <&bpmp 0>;
2051 bus-range = <0x0 0xff>;
2053 …ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 G…
2054 …<0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 6…
2055 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2061 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2062 iommu-map-mask = <0x0>;
2069 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2070 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2071 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2072 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
2085 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
2102 interrupt-map-mask = <0 0 0 0>;
2103 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2109 bus-range = <0x0 0xff>;
2111 …ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 G…
2112 …<0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 6…
2113 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2119 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2120 iommu-map-mask = <0x0>;
2127 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
2128 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2129 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
2130 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2159 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2160 iommu-map-mask = <0x0>;
2167 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2168 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2169 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
2170 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2189 nvidia,bpmp = <&bpmp 0>;
2199 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2200 iommu-map-mask = <0x0>;
2207 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2208 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2209 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2210 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2220 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
2242 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2243 iommu-map-mask = <0x0>;
2249 reg = <0x0 0x40000000 0x0 0x50000>;
2252 ranges = <0x0 0x0 0x40000000 0x50000>;
2255 reg = <0x4e000 0x1000>;
2261 reg = <0x4f000 0x1000>;
2286 #size-cells = <0>;
2299 #size-cells = <0>;
2301 cpu0_0: cpu@0 {
2304 reg = <0x000>;
2318 reg = <0x001>;
2332 reg = <0x100>;
2346 reg = <0x101>;
2360 reg = <0x200>;
2374 reg = <0x201>;
2388 reg = <0x300>;
2402 reg = <0x301>;
2519 assigned-clock-parents = <0>,
2537 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,