Lines Matching +full:exit +full:- +full:latency +full:- +full:us
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <26000000>;
22 clock-output-names = "clk26m";
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <32768>;
29 clock-output-names = "clk32k";
33 #address-cells = <1>;
34 #size-cells = <0>;
38 compatible = "arm,cortex-a55";
40 enable-method = "psci";
41 clock-frequency = <1701000000>;
42 cpu-idle-states = <&cpuoff_l &clusteroff_l>;
43 next-level-cache = <&l2_0>;
44 capacity-dmips-mhz = <530>;
49 compatible = "arm,cortex-a55";
51 enable-method = "psci";
52 clock-frequency = <1701000000>;
53 cpu-idle-states = <&cpuoff_l &clusteroff_l>;
54 next-level-cache = <&l2_0>;
55 capacity-dmips-mhz = <530>;
60 compatible = "arm,cortex-a55";
62 enable-method = "psci";
63 clock-frequency = <1701000000>;
64 cpu-idle-states = <&cpuoff_l &clusteroff_l>;
65 next-level-cache = <&l2_0>;
66 capacity-dmips-mhz = <530>;
71 compatible = "arm,cortex-a55";
73 enable-method = "psci";
74 clock-frequency = <1701000000>;
75 cpu-idle-states = <&cpuoff_l &clusteroff_l>;
76 next-level-cache = <&l2_0>;
77 capacity-dmips-mhz = <530>;
82 compatible = "arm,cortex-a76";
84 enable-method = "psci";
85 clock-frequency = <2171000000>;
86 cpu-idle-states = <&cpuoff_b &clusteroff_b>;
87 next-level-cache = <&l2_1>;
88 capacity-dmips-mhz = <1024>;
93 compatible = "arm,cortex-a76";
95 enable-method = "psci";
96 clock-frequency = <2171000000>;
97 cpu-idle-states = <&cpuoff_b &clusteroff_b>;
98 next-level-cache = <&l2_1>;
99 capacity-dmips-mhz = <1024>;
104 compatible = "arm,cortex-a76";
106 enable-method = "psci";
107 clock-frequency = <2171000000>;
108 cpu-idle-states = <&cpuoff_b &clusteroff_b>;
109 next-level-cache = <&l2_1>;
110 capacity-dmips-mhz = <1024>;
115 compatible = "arm,cortex-a76";
117 enable-method = "psci";
118 clock-frequency = <2171000000>;
119 cpu-idle-states = <&cpuoff_b &clusteroff_b>;
120 next-level-cache = <&l2_1>;
121 capacity-dmips-mhz = <1024>;
124 cpu-map {
156 l2_0: l2-cache0 {
158 next-level-cache = <&l3_0>;
161 l2_1: l2-cache1 {
163 next-level-cache = <&l3_0>;
166 l3_0: l3-cache {
170 idle-states {
171 entry-method = "arm,psci";
173 compatible = "arm,idle-state";
174 arm,psci-suspend-param = <0x00010001>;
175 local-timer-stop;
176 entry-latency-us = <55>;
177 exit-latency-us = <140>;
178 min-residency-us = <780>;
181 compatible = "arm,idle-state";
182 arm,psci-suspend-param = <0x00010001>;
183 local-timer-stop;
184 entry-latency-us = <35>;
185 exit-latency-us = <145>;
186 min-residency-us = <720>;
189 compatible = "arm,idle-state";
190 arm,psci-suspend-param = <0x01010002>;
191 local-timer-stop;
192 entry-latency-us = <60>;
193 exit-latency-us = <155>;
194 min-residency-us = <860>;
197 compatible = "arm,idle-state";
198 arm,psci-suspend-param = <0x01010002>;
199 local-timer-stop;
200 entry-latency-us = <40>;
201 exit-latency-us = <155>;
202 min-residency-us = <780>;
207 pmu-a55 {
208 compatible = "arm,cortex-a55-pmu";
209 interrupt-parent = <&gic>;
213 pmu-a76 {
214 compatible = "arm,cortex-a76-pmu";
215 interrupt-parent = <&gic>;
220 compatible = "arm,psci-1.0";
225 compatible = "arm,armv8-timer";
226 interrupt-parent = <&gic>;
231 clock-frequency = <13000000>;
235 #address-cells = <2>;
236 #size-cells = <2>;
237 compatible = "simple-bus";
240 gic: interrupt-controller@c000000 {
241 compatible = "arm,gic-v3";
242 #interrupt-cells = <4>;
243 #redistributor-regions = <1>;
244 interrupt-parent = <&gic>;
245 interrupt-controller;
250 ppi-partitions {
251 ppi_cluster0: interrupt-partition-0 {
254 ppi_cluster1: interrupt-partition-1 {
261 compatible = "mediatek,mt8192-pinctrl";
273 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
277 gpio-controller;
278 #gpio-cells = <2>;
279 gpio-ranges = <&pio 0 0 220>;
280 interrupt-controller;
282 #interrupt-cells = <2>;
286 compatible = "mediatek,mt8192-timer",
287 "mediatek,mt6765-timer";
291 clock-names = "clk13m";
295 compatible = "mediatek,mt8192-uart",
296 "mediatek,mt6577-uart";
300 clock-names = "baud", "bus";
305 compatible = "mediatek,mt8192-uart",
306 "mediatek,mt6577-uart";
310 clock-names = "baud", "bus";
315 compatible = "mediatek,mt8192-spi",
316 "mediatek,mt6765-spi";
317 #address-cells = <1>;
318 #size-cells = <0>;
324 clock-names = "parent-clk", "sel-clk", "spi-clk";
329 compatible = "mediatek,mt8192-spi",
330 "mediatek,mt6765-spi";
331 #address-cells = <1>;
332 #size-cells = <0>;
338 clock-names = "parent-clk", "sel-clk", "spi-clk";
343 compatible = "mediatek,mt8192-spi",
344 "mediatek,mt6765-spi";
345 #address-cells = <1>;
346 #size-cells = <0>;
352 clock-names = "parent-clk", "sel-clk", "spi-clk";
357 compatible = "mediatek,mt8192-spi",
358 "mediatek,mt6765-spi";
359 #address-cells = <1>;
360 #size-cells = <0>;
366 clock-names = "parent-clk", "sel-clk", "spi-clk";
371 compatible = "mediatek,mt8192-spi",
372 "mediatek,mt6765-spi";
373 #address-cells = <1>;
374 #size-cells = <0>;
380 clock-names = "parent-clk", "sel-clk", "spi-clk";
385 compatible = "mediatek,mt8192-spi",
386 "mediatek,mt6765-spi";
387 #address-cells = <1>;
388 #size-cells = <0>;
394 clock-names = "parent-clk", "sel-clk", "spi-clk";
399 compatible = "mediatek,mt8192-spi",
400 "mediatek,mt6765-spi";
401 #address-cells = <1>;
402 #size-cells = <0>;
408 clock-names = "parent-clk", "sel-clk", "spi-clk";
413 compatible = "mediatek,mt8192-spi",
414 "mediatek,mt6765-spi";
415 #address-cells = <1>;
416 #size-cells = <0>;
422 clock-names = "parent-clk", "sel-clk", "spi-clk";
427 compatible = "mediatek,mt8192-nor";
433 clock-names = "spi", "sf", "axi";
434 #address-cells = <1>;
435 #size-cells = <0>;
440 compatible = "mediatek,mt8192-i2c";
445 clock-names = "main", "dma";
446 clock-div = <1>;
447 #address-cells = <1>;
448 #size-cells = <0>;
453 compatible = "mediatek,mt8192-i2c";
458 clock-names = "main", "dma";
459 clock-div = <1>;
460 #address-cells = <1>;
461 #size-cells = <0>;
466 compatible = "mediatek,mt8192-i2c";
471 clock-names = "main", "dma";
472 clock-div = <1>;
473 #address-cells = <1>;
474 #size-cells = <0>;
479 compatible = "mediatek,mt8192-i2c";
484 clock-names = "main", "dma";
485 clock-div = <1>;
486 #address-cells = <1>;
487 #size-cells = <0>;
492 compatible = "mediatek,mt8192-i2c";
497 clock-names = "main", "dma";
498 clock-div = <1>;
499 #address-cells = <1>;
500 #size-cells = <0>;
505 compatible = "mediatek,mt8192-i2c";
510 clock-names = "main", "dma";
511 clock-div = <1>;
512 #address-cells = <1>;
513 #size-cells = <0>;
518 compatible = "mediatek,mt8192-i2c";
523 clock-names = "main", "dma";
524 clock-div = <1>;
525 #address-cells = <1>;
526 #size-cells = <0>;
531 compatible = "mediatek,mt8192-i2c";
536 clock-names = "main", "dma";
537 clock-div = <1>;
538 #address-cells = <1>;
539 #size-cells = <0>;
544 compatible = "mediatek,mt8192-i2c";
549 clock-names = "main", "dma";
550 clock-div = <1>;
551 #address-cells = <1>;
552 #size-cells = <0>;
557 compatible = "mediatek,mt8192-i2c";
562 clock-names = "main", "dma";
563 clock-div = <1>;
564 #address-cells = <1>;
565 #size-cells = <0>;