Lines Matching +full:psci +full:- +full:suspend +full:- +full:param
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/gce/mt8183-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8183-larb-port.h>
13 #include <dt-bindings/power/mt8183-power.h>
14 #include <dt-bindings/reset-controller/mt8183-resets.h>
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/thermal/thermal.h>
17 #include <dt-bindings/pinctrl/mt8183-pinfunc.h>
21 interrupt-parent = <&sysirq>;
22 #address-cells = <2>;
23 #size-cells = <2>;
39 ovl-2l0 = &ovl_2l0;
40 ovl-2l1 = &ovl_2l1;
46 #address-cells = <1>;
47 #size-cells = <0>;
49 cpu-map {
83 compatible = "arm,cortex-a53";
85 enable-method = "psci";
86 capacity-dmips-mhz = <741>;
87 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
88 dynamic-power-coefficient = <84>;
89 #cooling-cells = <2>;
94 compatible = "arm,cortex-a53";
96 enable-method = "psci";
97 capacity-dmips-mhz = <741>;
98 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
99 dynamic-power-coefficient = <84>;
100 #cooling-cells = <2>;
105 compatible = "arm,cortex-a53";
107 enable-method = "psci";
108 capacity-dmips-mhz = <741>;
109 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
110 dynamic-power-coefficient = <84>;
111 #cooling-cells = <2>;
116 compatible = "arm,cortex-a53";
118 enable-method = "psci";
119 capacity-dmips-mhz = <741>;
120 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
121 dynamic-power-coefficient = <84>;
122 #cooling-cells = <2>;
127 compatible = "arm,cortex-a73";
129 enable-method = "psci";
130 capacity-dmips-mhz = <1024>;
131 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
132 dynamic-power-coefficient = <211>;
133 #cooling-cells = <2>;
138 compatible = "arm,cortex-a73";
140 enable-method = "psci";
141 capacity-dmips-mhz = <1024>;
142 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
143 dynamic-power-coefficient = <211>;
144 #cooling-cells = <2>;
149 compatible = "arm,cortex-a73";
151 enable-method = "psci";
152 capacity-dmips-mhz = <1024>;
153 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
154 dynamic-power-coefficient = <211>;
155 #cooling-cells = <2>;
160 compatible = "arm,cortex-a73";
162 enable-method = "psci";
163 capacity-dmips-mhz = <1024>;
164 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
165 dynamic-power-coefficient = <211>;
166 #cooling-cells = <2>;
169 idle-states {
170 entry-method = "psci";
172 CPU_SLEEP: cpu-sleep {
173 compatible = "arm,idle-state";
174 local-timer-stop;
175 arm,psci-suspend-param = <0x00010001>;
176 entry-latency-us = <200>;
177 exit-latency-us = <200>;
178 min-residency-us = <800>;
181 CLUSTER_SLEEP0: cluster-sleep-0 {
182 compatible = "arm,idle-state";
183 local-timer-stop;
184 arm,psci-suspend-param = <0x01010001>;
185 entry-latency-us = <250>;
186 exit-latency-us = <400>;
187 min-residency-us = <1000>;
189 CLUSTER_SLEEP1: cluster-sleep-1 {
190 compatible = "arm,idle-state";
191 local-timer-stop;
192 arm,psci-suspend-param = <0x01010001>;
193 entry-latency-us = <250>;
194 exit-latency-us = <400>;
195 min-residency-us = <1300>;
201 compatible = "operating-points-v2";
202 opp-shared;
204 opp-300000000 {
205 opp-hz = /bits/ 64 <300000000>;
206 opp-microvolt = <625000>, <850000>;
209 opp-320000000 {
210 opp-hz = /bits/ 64 <320000000>;
211 opp-microvolt = <631250>, <850000>;
214 opp-340000000 {
215 opp-hz = /bits/ 64 <340000000>;
216 opp-microvolt = <637500>, <850000>;
219 opp-360000000 {
220 opp-hz = /bits/ 64 <360000000>;
221 opp-microvolt = <643750>, <850000>;
224 opp-380000000 {
225 opp-hz = /bits/ 64 <380000000>;
226 opp-microvolt = <650000>, <850000>;
229 opp-400000000 {
230 opp-hz = /bits/ 64 <400000000>;
231 opp-microvolt = <656250>, <850000>;
234 opp-420000000 {
235 opp-hz = /bits/ 64 <420000000>;
236 opp-microvolt = <662500>, <850000>;
239 opp-460000000 {
240 opp-hz = /bits/ 64 <460000000>;
241 opp-microvolt = <675000>, <850000>;
244 opp-500000000 {
245 opp-hz = /bits/ 64 <500000000>;
246 opp-microvolt = <687500>, <850000>;
249 opp-540000000 {
250 opp-hz = /bits/ 64 <540000000>;
251 opp-microvolt = <700000>, <850000>;
254 opp-580000000 {
255 opp-hz = /bits/ 64 <580000000>;
256 opp-microvolt = <712500>, <850000>;
259 opp-620000000 {
260 opp-hz = /bits/ 64 <620000000>;
261 opp-microvolt = <725000>, <850000>;
264 opp-653000000 {
265 opp-hz = /bits/ 64 <653000000>;
266 opp-microvolt = <743750>, <850000>;
269 opp-698000000 {
270 opp-hz = /bits/ 64 <698000000>;
271 opp-microvolt = <768750>, <868750>;
274 opp-743000000 {
275 opp-hz = /bits/ 64 <743000000>;
276 opp-microvolt = <793750>, <893750>;
279 opp-800000000 {
280 opp-hz = /bits/ 64 <800000000>;
281 opp-microvolt = <825000>, <925000>;
285 pmu-a53 {
286 compatible = "arm,cortex-a53-pmu";
287 interrupt-parent = <&gic>;
291 pmu-a73 {
292 compatible = "arm,cortex-a73-pmu";
293 interrupt-parent = <&gic>;
297 psci {
298 compatible = "arm,psci-1.0";
303 compatible = "fixed-clock";
304 #clock-cells = <0>;
305 clock-frequency = <26000000>;
306 clock-output-names = "clk26m";
310 compatible = "arm,armv8-timer";
311 interrupt-parent = <&gic>;
319 #address-cells = <2>;
320 #size-cells = <2>;
321 compatible = "simple-bus";
325 compatible = "mediatek,mt8183-efuse",
328 #address-cells = <1>;
329 #size-cells = <1>;
333 gic: interrupt-controller@c000000 {
334 compatible = "arm,gic-v3";
335 #interrupt-cells = <4>;
336 interrupt-parent = <&gic>;
337 interrupt-controller;
345 ppi-partitions {
346 ppi_cluster0: interrupt-partition-0 {
349 ppi_cluster1: interrupt-partition-1 {
356 compatible = "mediatek,mt8183-mcucfg", "syscon";
358 #clock-cells = <1>;
361 sysirq: interrupt-controller@c530a80 {
362 compatible = "mediatek,mt8183-sysirq",
363 "mediatek,mt6577-sysirq";
364 interrupt-controller;
365 #interrupt-cells = <3>;
366 interrupt-parent = <&gic>;
371 compatible = "mediatek,mt8183-topckgen", "syscon";
373 #clock-cells = <1>;
377 compatible = "mediatek,mt8183-infracfg", "syscon";
379 #clock-cells = <1>;
380 #reset-cells = <1>;
384 compatible = "mediatek,mt8183-pericfg", "syscon";
386 #clock-cells = <1>;
390 compatible = "mediatek,mt8183-pinctrl";
401 reg-names = "iocfg0", "iocfg1", "iocfg2",
405 gpio-controller;
406 #gpio-cells = <2>;
407 gpio-ranges = <&pio 0 0 192>;
408 interrupt-controller;
410 #interrupt-cells = <2>;
414 compatible = "syscon", "simple-mfd";
416 #power-domain-cells = <1>;
419 spm: power-controller {
420 compatible = "mediatek,mt8183-power-controller";
421 #address-cells = <1>;
422 #size-cells = <0>;
423 #power-domain-cells = <1>;
426 power-domain@MT8183_POWER_DOMAIN_AUDIO {
431 clock-names = "audio", "audio1", "audio2";
432 #power-domain-cells = <0>;
435 power-domain@MT8183_POWER_DOMAIN_CONN {
438 #power-domain-cells = <0>;
441 power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC {
444 clock-names = "mfg";
445 #address-cells = <1>;
446 #size-cells = <0>;
447 #power-domain-cells = <1>;
449 mfg: power-domain@MT8183_POWER_DOMAIN_MFG {
451 #address-cells = <1>;
452 #size-cells = <0>;
453 #power-domain-cells = <1>;
455 power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 {
457 #power-domain-cells = <0>;
460 power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 {
462 #power-domain-cells = <0>;
465 power-domain@MT8183_POWER_DOMAIN_MFG_2D {
468 #power-domain-cells = <0>;
473 power-domain@MT8183_POWER_DOMAIN_DISP {
486 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3",
487 "mm-4", "mm-5", "mm-6", "mm-7",
488 "mm-8", "mm-9";
491 #address-cells = <1>;
492 #size-cells = <0>;
493 #power-domain-cells = <1>;
495 power-domain@MT8183_POWER_DOMAIN_CAM {
505 clock-names = "cam", "cam-0", "cam-1",
506 "cam-2", "cam-3", "cam-4",
507 "cam-5", "cam-6";
510 #power-domain-cells = <0>;
513 power-domain@MT8183_POWER_DOMAIN_ISP {
518 clock-names = "isp", "isp-0", "isp-1";
521 #power-domain-cells = <0>;
524 power-domain@MT8183_POWER_DOMAIN_VDEC {
527 #power-domain-cells = <0>;
530 power-domain@MT8183_POWER_DOMAIN_VENC {
533 #power-domain-cells = <0>;
536 power-domain@MT8183_POWER_DOMAIN_VPU_TOP {
546 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1",
547 "vpu-2", "vpu-3", "vpu-4", "vpu-5";
550 #address-cells = <1>;
551 #size-cells = <0>;
552 #power-domain-cells = <1>;
554 power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 {
557 clock-names = "vpu2";
559 #power-domain-cells = <0>;
562 power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 {
565 clock-names = "vpu3";
567 #power-domain-cells = <0>;
575 compatible = "mediatek,mt8183-wdt";
577 #reset-cells = <1>;
581 compatible = "mediatek,mt8183-apmixedsys", "syscon";
583 #clock-cells = <1>;
587 compatible = "mediatek,mt8183-pwrap";
589 reg-names = "pwrap";
593 clock-names = "spi", "wrap";
597 compatible = "mediatek,mt8183-scp";
600 reg-names = "sram", "cfg";
603 clock-names = "main";
604 memory-region = <&scp_mem_reserved>;
609 compatible = "mediatek,mt8183-timer",
610 "mediatek,mt6765-timer";
614 clock-names = "clk13m";
618 compatible = "mediatek,mt8183-m4u";
623 #iommu-cells = <1>;
627 compatible = "mediatek,mt8183-gce";
630 #mbox-cells = <2>;
632 clock-names = "gce";
636 compatible = "mediatek,mt8183-auxadc",
637 "mediatek,mt8173-auxadc";
640 clock-names = "main";
641 #io-channel-cells = <1>;
646 compatible = "mediatek,mt8183-uart",
647 "mediatek,mt6577-uart";
651 clock-names = "baud", "bus";
656 compatible = "mediatek,mt8183-uart",
657 "mediatek,mt6577-uart";
661 clock-names = "baud", "bus";
666 compatible = "mediatek,mt8183-uart",
667 "mediatek,mt6577-uart";
671 clock-names = "baud", "bus";
676 compatible = "mediatek,mt8183-i2c";
682 clock-names = "main", "dma";
683 clock-div = <1>;
684 #address-cells = <1>;
685 #size-cells = <0>;
690 compatible = "mediatek,mt8183-i2c";
696 clock-names = "main", "dma";
697 clock-div = <1>;
698 #address-cells = <1>;
699 #size-cells = <0>;
704 compatible = "mediatek,mt8183-i2c";
711 clock-names = "main", "dma","arb";
712 clock-div = <1>;
713 #address-cells = <1>;
714 #size-cells = <0>;
719 compatible = "mediatek,mt8183-i2c";
726 clock-names = "main", "dma", "arb";
727 clock-div = <1>;
728 #address-cells = <1>;
729 #size-cells = <0>;
734 compatible = "mediatek,mt8183-spi";
735 #address-cells = <1>;
736 #size-cells = <0>;
742 clock-names = "parent-clk", "sel-clk", "spi-clk";
747 #thermal-sensor-cells = <1>;
748 compatible = "mediatek,mt8183-thermal";
752 clock-names = "therm", "auxadc";
757 nvmem-cells = <&thermal_calibration>;
758 nvmem-cell-names = "calibration-data";
761 thermal_zones: thermal-zones {
763 polling-delay-passive = <100>;
764 polling-delay = <500>;
765 thermal-sensors = <&thermal 0>;
766 sustainable-power = <5000>;
769 threshold: trip-point0 {
775 target: trip-point1 {
781 cpu_crit: cpu-crit {
788 cooling-maps {
791 cooling-device = <&cpu0
807 cooling-device = <&cpu4
828 polling-delay-passive = <0>;
829 polling-delay = <0>;
830 thermal-sensors = <&thermal 1>;
831 sustainable-power = <5000>;
833 cooling-maps {};
837 polling-delay-passive = <0>;
838 polling-delay = <0>;
839 thermal-sensors = <&thermal 2>;
840 sustainable-power = <5000>;
842 cooling-maps {};
846 polling-delay-passive = <0>;
847 polling-delay = <0>;
848 thermal-sensors = <&thermal 3>;
849 sustainable-power = <5000>;
851 cooling-maps {};
855 polling-delay-passive = <0>;
856 polling-delay = <0>;
857 thermal-sensors = <&thermal 4>;
858 sustainable-power = <5000>;
860 cooling-maps {};
864 polling-delay-passive = <0>;
865 polling-delay = <0>;
866 thermal-sensors = <&thermal 5>;
867 sustainable-power = <5000>;
869 cooling-maps {};
873 polling-delay-passive = <0>;
874 polling-delay = <0>;
875 thermal-sensors = <&thermal 6>;
876 sustainable-power = <5000>;
878 cooling-maps {};
883 compatible = "mediatek,mt8183-disp-pwm";
886 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
887 #pwm-cells = <2>;
890 clock-names = "main", "mm";
894 compatible = "mediatek,mt8183-pwm";
896 #pwm-cells = <2>;
903 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
908 compatible = "mediatek,mt8183-i2c";
914 clock-names = "main", "dma";
915 clock-div = <1>;
916 #address-cells = <1>;
917 #size-cells = <0>;
922 compatible = "mediatek,mt8183-spi";
923 #address-cells = <1>;
924 #size-cells = <0>;
930 clock-names = "parent-clk", "sel-clk", "spi-clk";
935 compatible = "mediatek,mt8183-i2c";
941 clock-names = "main", "dma";
942 clock-div = <1>;
943 #address-cells = <1>;
944 #size-cells = <0>;
949 compatible = "mediatek,mt8183-spi";
950 #address-cells = <1>;
951 #size-cells = <0>;
957 clock-names = "parent-clk", "sel-clk", "spi-clk";
962 compatible = "mediatek,mt8183-spi";
963 #address-cells = <1>;
964 #size-cells = <0>;
970 clock-names = "parent-clk", "sel-clk", "spi-clk";
975 compatible = "mediatek,mt8183-i2c";
982 clock-names = "main", "dma", "arb";
983 clock-div = <1>;
984 #address-cells = <1>;
985 #size-cells = <0>;
990 compatible = "mediatek,mt8183-i2c";
997 clock-names = "main", "dma", "arb";
998 clock-div = <1>;
999 #address-cells = <1>;
1000 #size-cells = <0>;
1005 compatible = "mediatek,mt8183-i2c";
1012 clock-names = "main", "dma", "arb";
1013 clock-div = <1>;
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1020 compatible = "mediatek,mt8183-i2c";
1027 clock-names = "main", "dma", "arb";
1028 clock-div = <1>;
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1035 compatible = "mediatek,mt8183-spi";
1036 #address-cells = <1>;
1037 #size-cells = <0>;
1043 clock-names = "parent-clk", "sel-clk", "spi-clk";
1048 compatible = "mediatek,mt8183-spi";
1049 #address-cells = <1>;
1050 #size-cells = <0>;
1056 clock-names = "parent-clk", "sel-clk", "spi-clk";
1061 compatible = "mediatek,mt8183-i2c";
1067 clock-names = "main", "dma";
1068 clock-div = <1>;
1069 #address-cells = <1>;
1070 #size-cells = <0>;
1075 compatible = "mediatek,mt8183-i2c";
1081 clock-names = "main", "dma";
1082 clock-div = <1>;
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1089 compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
1092 reg-names = "mac", "ippc";
1098 clock-names = "sys_ck", "ref_ck";
1099 mediatek,syscon-wakeup = <&pericfg 0x420 101>;
1100 #address-cells = <2>;
1101 #size-cells = <2>;
1106 compatible = "mediatek,mt8183-xhci",
1107 "mediatek,mtk-xhci";
1109 reg-names = "mac";
1113 clock-names = "sys_ck", "ref_ck";
1119 compatible = "mediatek,mt8183-audiosys", "syscon";
1121 #clock-cells = <1>;
1125 compatible = "mediatek,mt8183-mmc";
1132 clock-names = "source", "hclk", "source_cg";
1137 compatible = "mediatek,mt8183-mmc";
1144 clock-names = "source", "hclk", "source_cg";
1148 mipi_tx0: dsi-phy@11e50000 {
1149 compatible = "mediatek,mt8183-mipi-tx";
1152 #clock-cells = <0>;
1153 #phy-cells = <0>;
1154 clock-output-names = "mipi_tx0_pll";
1155 nvmem-cells = <&mipi_tx_calibration>;
1156 nvmem-cell-names = "calibration-data";
1160 compatible = "mediatek,mt8183-efuse",
1163 #address-cells = <1>;
1164 #size-cells = <1>;
1174 u3phy: t-phy@11f40000 {
1175 compatible = "mediatek,mt8183-tphy",
1176 "mediatek,generic-tphy-v2";
1177 #address-cells = <1>;
1178 #size-cells = <1>;
1182 u2port0: usb-phy@0 {
1185 clock-names = "ref";
1186 #phy-cells = <1>;
1191 u3port0: usb-phy@700 {
1194 clock-names = "ref";
1195 #phy-cells = <1>;
1201 compatible = "mediatek,mt8183-mfgcfg", "syscon";
1203 #clock-cells = <1>;
1207 compatible = "mediatek,mt8183-mali", "arm,mali-bifrost";
1213 interrupt-names = "job", "mmu", "gpu";
1217 power-domains =
1221 power-domain-names = "core0", "core1", "core2";
1223 operating-points-v2 = <&gpu_opp_table>;
1227 compatible = "mediatek,mt8183-mmsys", "syscon";
1229 #clock-cells = <1>;
1232 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1236 compatible = "mediatek,mt8183-disp-ovl";
1239 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1243 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1247 compatible = "mediatek,mt8183-disp-ovl-2l";
1250 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1254 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1258 compatible = "mediatek,mt8183-disp-ovl-2l";
1261 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1265 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1269 compatible = "mediatek,mt8183-disp-rdma";
1272 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1276 mediatek,rdma-fifo-size = <5120>;
1277 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1281 compatible = "mediatek,mt8183-disp-rdma";
1284 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1288 mediatek,rdma-fifo-size = <2048>;
1289 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1293 compatible = "mediatek,mt8183-disp-color",
1294 "mediatek,mt8173-disp-color";
1297 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1299 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1303 compatible = "mediatek,mt8183-disp-ccorr";
1306 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1308 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1312 compatible = "mediatek,mt8183-disp-aal",
1313 "mediatek,mt8173-disp-aal";
1316 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1318 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1322 compatible = "mediatek,mt8183-disp-gamma";
1325 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1327 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1331 compatible = "mediatek,mt8183-disp-dither";
1334 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1336 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1340 compatible = "mediatek,mt8183-dsi";
1343 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1344 mediatek,syscon-dsi = <&mmsys 0x140>;
1348 clock-names = "engine", "digital", "hs";
1350 phy-names = "dphy";
1354 compatible = "mediatek,mt8183-disp-mutex";
1357 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1358 mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
1363 compatible = "mediatek,mt8183-smi-larb";
1368 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1369 clock-names = "apb", "smi";
1373 compatible = "mediatek,mt8183-smi-common";
1379 clock-names = "apb", "smi", "gals0", "gals1";
1380 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1384 compatible = "mediatek,mt8183-imgsys", "syscon";
1386 #clock-cells = <1>;
1390 compatible = "mediatek,mt8183-smi-larb";
1395 clock-names = "apb", "smi", "gals";
1396 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
1400 compatible = "mediatek,mt8183-smi-larb";
1405 clock-names = "apb", "smi", "gals";
1406 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
1410 compatible = "mediatek,mt8183-vdecsys", "syscon";
1412 #clock-cells = <1>;
1416 compatible = "mediatek,mt8183-smi-larb";
1420 clock-names = "apb", "smi";
1421 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
1425 compatible = "mediatek,mt8183-vencsys", "syscon";
1427 #clock-cells = <1>;
1431 compatible = "mediatek,mt8183-smi-larb";
1436 clock-names = "apb", "smi";
1437 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
1441 compatible = "mediatek,mt8183-ipu_conn", "syscon";
1443 #clock-cells = <1>;
1447 compatible = "mediatek,mt8183-ipu_adl", "syscon";
1449 #clock-cells = <1>;
1453 compatible = "mediatek,mt8183-ipu_core0", "syscon";
1455 #clock-cells = <1>;
1459 compatible = "mediatek,mt8183-ipu_core1", "syscon";
1461 #clock-cells = <1>;
1465 compatible = "mediatek,mt8183-camsys", "syscon";
1467 #clock-cells = <1>;
1471 compatible = "mediatek,mt8183-smi-larb";
1476 clock-names = "apb", "smi", "gals";
1477 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
1481 compatible = "mediatek,mt8183-smi-larb";
1486 clock-names = "apb", "smi", "gals";
1487 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;