Lines Matching +full:hs400 +full:- +full:ds +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
15 compatible = "mediatek,mt8183-pumpkin", "mediatek,mt8183";
27 stdout-path = "serial0:921600n8";
30 reserved-memory {
31 #address-cells = <2>;
32 #size-cells = <2>;
36 compatible = "shared-dma-pool";
38 no-map;
43 compatible = "gpio-leds";
45 led-red {
48 default-state = "off";
51 led-green {
54 default-state = "off";
60 pullup-uv = <1800000>;
61 pullup-ohm = <390000>;
62 pulldown-ohm = <0>;
63 io-channels = <&auxadc 0>;
72 mali-supply = <&mt6358_vgpu_reg>;
73 sram-supply = <&mt6358_vsram_gpu_reg>;
77 pinctrl-names = "default";
78 pinctrl-0 = <&i2c_pins_0>;
80 clock-frequency = <100000>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&i2c_pins_1>;
87 clock-frequency = <100000>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&i2c_pins_2>;
94 clock-frequency = <100000>;
98 pinctrl-names = "default";
99 pinctrl-0 = <&i2c_pins_3>;
101 clock-frequency = <100000>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&i2c_pins_4>;
108 clock-frequency = <100000>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&i2c_pins_5>;
115 clock-frequency = <100000>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&i2c6_pins>;
122 clock-frequency = <100000>;
127 pinctrl-names = "default", "state_uhs";
128 pinctrl-0 = <&mmc0_pins_default>;
129 pinctrl-1 = <&mmc0_pins_uhs>;
130 bus-width = <8>;
131 max-frequency = <200000000>;
132 cap-mmc-highspeed;
133 mmc-hs200-1_8v;
134 mmc-hs400-1_8v;
135 cap-mmc-hw-reset;
136 no-sdio;
137 no-sd;
138 hs400-ds-delay = <0x12814>;
139 vmmc-supply = <&mt6358_vemc_reg>;
140 vqmmc-supply = <&mt6358_vio18_reg>;
141 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
142 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
143 non-removable;
148 pinctrl-names = "default", "state_uhs";
149 pinctrl-0 = <&mmc1_pins_default>;
150 pinctrl-1 = <&mmc1_pins_uhs>;
151 bus-width = <4>;
152 max-frequency = <200000000>;
153 cap-sd-highspeed;
154 sd-uhs-sdr50;
155 sd-uhs-sdr104;
156 cap-sdio-irq;
157 no-mmc;
158 no-sd;
159 vmmc-supply = <&mt6358_vmch_reg>;
160 vqmmc-supply = <&mt6358_vmc_reg>;
161 keep-power-in-suspend;
162 enable-sdio-wakeup;
163 non-removable;
171 mediatek,pull-up-adv = <3>;
172 mediatek,drive-strength-adv = <00>;
180 mediatek,pull-up-adv = <3>;
181 mediatek,drive-strength-adv = <00>;
189 mediatek,pull-up-adv = <3>;
190 mediatek,drive-strength-adv = <00>;
198 mediatek,pull-up-adv = <3>;
199 mediatek,drive-strength-adv = <00>;
207 mediatek,pull-up-adv = <3>;
208 mediatek,drive-strength-adv = <00>;
216 mediatek,pull-up-adv = <3>;
217 mediatek,drive-strength-adv = <00>;
225 mediatek,pull-up-adv = <3>;
229 mmc0_pins_default: mmc0-pins-default {
240 input-enable;
241 drive-strength = <MTK_DRIVE_14mA>;
242 mediatek,pull-up-adv = <01>;
247 drive-strength = <MTK_DRIVE_14mA>;
248 mediatek,pull-down-adv = <10>;
253 drive-strength = <MTK_DRIVE_14mA>;
254 mediatek,pull-down-adv = <01>;
258 mmc0_pins_uhs: mmc0-pins-uhs {
269 input-enable;
270 drive-strength = <MTK_DRIVE_14mA>;
271 mediatek,pull-up-adv = <01>;
276 drive-strength = <MTK_DRIVE_14mA>;
277 mediatek,pull-down-adv = <10>;
282 drive-strength = <MTK_DRIVE_14mA>;
283 mediatek,pull-down-adv = <10>;
288 drive-strength = <MTK_DRIVE_14mA>;
289 mediatek,pull-up-adv = <01>;
293 mmc1_pins_default: mmc1-pins-default {
300 input-enable;
301 mediatek,pull-up-adv = <10>;
306 input-enable;
307 mediatek,pull-down-adv = <10>;
312 output-high;
316 mmc1_pins_uhs: mmc1-pins-uhs {
323 drive-strength = <MTK_DRIVE_6mA>;
324 input-enable;
325 mediatek,pull-up-adv = <10>;
330 drive-strength = <MTK_DRIVE_8mA>;
331 mediatek,pull-down-adv = <10>;
332 input-enable;
338 domain-supply = <&mt6358_vgpu_reg>;
342 proc-supply = <&mt6358_vproc12_reg>;
346 proc-supply = <&mt6358_vproc12_reg>;
350 proc-supply = <&mt6358_vproc12_reg>;
354 proc-supply = <&mt6358_vproc12_reg>;
358 proc-supply = <&mt6358_vproc11_reg>;
362 proc-supply = <&mt6358_vproc11_reg>;
366 proc-supply = <&mt6358_vproc11_reg>;
370 proc-supply = <&mt6358_vproc11_reg>;