Lines Matching +full:hs400 +full:- +full:ds +full:- +full:delay
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
14 compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
26 stdout-path = "serial0:921600n8";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
34 compatible = "shared-dma-pool";
36 no-map;
46 mali-supply = <&mt6358_vgpu_reg>;
47 sram-supply = <&mt6358_vsram_gpu_reg>;
51 pinctrl-names = "default";
52 pinctrl-0 = <&i2c_pins_0>;
54 clock-frequency = <100000>;
58 pinctrl-names = "default";
59 pinctrl-0 = <&i2c_pins_1>;
61 clock-frequency = <100000>;
65 pinctrl-names = "default";
66 pinctrl-0 = <&i2c_pins_2>;
68 clock-frequency = <100000>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&i2c_pins_3>;
75 clock-frequency = <100000>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&i2c_pins_4>;
82 clock-frequency = <1000000>;
86 pinctrl-names = "default";
87 pinctrl-0 = <&i2c_pins_5>;
89 clock-frequency = <1000000>;
94 pinctrl-names = "default", "state_uhs";
95 pinctrl-0 = <&mmc0_pins_default>;
96 pinctrl-1 = <&mmc0_pins_uhs>;
97 bus-width = <8>;
98 max-frequency = <200000000>;
99 cap-mmc-highspeed;
100 mmc-hs200-1_8v;
101 mmc-hs400-1_8v;
102 cap-mmc-hw-reset;
103 no-sdio;
104 no-sd;
105 hs400-ds-delay = <0x12814>;
106 vmmc-supply = <&mt6358_vemc_reg>;
107 vqmmc-supply = <&mt6358_vio18_reg>;
108 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
109 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
110 non-removable;
115 pinctrl-names = "default", "state_uhs";
116 pinctrl-0 = <&mmc1_pins_default>;
117 pinctrl-1 = <&mmc1_pins_uhs>;
118 bus-width = <4>;
119 max-frequency = <200000000>;
120 cap-sd-highspeed;
121 sd-uhs-sdr50;
122 sd-uhs-sdr104;
123 cap-sdio-irq;
124 no-mmc;
125 no-sd;
126 vmmc-supply = <&mt6358_vmch_reg>;
127 vqmmc-supply = <&mt6358_vmc_reg>;
128 keep-power-in-suspend;
129 enable-sdio-wakeup;
130 non-removable;
138 mediatek,pull-up-adv = <3>;
139 mediatek,drive-strength-adv = <00>;
147 mediatek,pull-up-adv = <3>;
148 mediatek,drive-strength-adv = <00>;
156 mediatek,pull-up-adv = <3>;
157 mediatek,drive-strength-adv = <00>;
165 mediatek,pull-up-adv = <3>;
166 mediatek,drive-strength-adv = <00>;
174 mediatek,pull-up-adv = <3>;
175 mediatek,drive-strength-adv = <00>;
183 mediatek,pull-up-adv = <3>;
184 mediatek,drive-strength-adv = <00>;
194 bias-disable;
209 input-enable;
210 bias-pull-up;
215 bias-pull-down;
220 bias-pull-up;
235 input-enable;
236 drive-strength = <MTK_DRIVE_10mA>;
237 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
242 drive-strength = <MTK_DRIVE_10mA>;
243 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
248 drive-strength = <MTK_DRIVE_10mA>;
249 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
254 drive-strength = <MTK_DRIVE_10mA>;
255 bias-pull-up;
266 input-enable;
267 bias-pull-up;
272 input-enable;
273 bias-pull-down;
279 output-high;
290 drive-strength = <MTK_DRIVE_6mA>;
291 input-enable;
292 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
297 drive-strength = <MTK_DRIVE_6mA>;
298 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
299 input-enable;
309 bias-disable;
319 bias-disable;
329 bias-disable;
339 bias-disable;
349 bias-disable;
361 domain-supply = <&mt6358_vgpu_reg>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&spi_pins_0>;
367 mediatek,pad-select = <0>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&spi_pins_1>;
374 mediatek,pad-select = <0>;
379 pinctrl-names = "default";
380 pinctrl-0 = <&spi_pins_2>;
381 mediatek,pad-select = <0>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&spi_pins_3>;
388 mediatek,pad-select = <0>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&spi_pins_4>;
395 mediatek,pad-select = <0>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&spi_pins_5>;
402 mediatek,pad-select = <0>;
413 pinctrl-0 = <&pwm_pins_1>;
414 pinctrl-names = "default";