Lines Matching +full:power +full:- +full:domain +full:- +full:names
14 #include <dt-bindings/clock/mt8173-clk.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/memory/mt8173-larb-port.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/power/mt8173-power.h>
20 #include <dt-bindings/reset/mt8173-resets.h>
21 #include <dt-bindings/gce/mt8173-gce.h>
22 #include <dt-bindings/thermal/thermal.h>
23 #include "mt8173-pinfunc.h"
27 interrupt-parent = <&sysirq>;
28 #address-cells = <2>;
29 #size-cells = <2>;
46 mdp-rdma0 = &mdp_rdma0;
47 mdp-rdma1 = &mdp_rdma1;
48 mdp-rsz0 = &mdp_rsz0;
49 mdp-rsz1 = &mdp_rsz1;
50 mdp-rsz2 = &mdp_rsz2;
51 mdp-wdma0 = &mdp_wdma0;
52 mdp-wrot0 = &mdp_wrot0;
53 mdp-wrot1 = &mdp_wrot1;
61 compatible = "operating-points-v2";
62 opp-shared;
63 opp-507000000 {
64 opp-hz = /bits/ 64 <507000000>;
65 opp-microvolt = <859000>;
67 opp-702000000 {
68 opp-hz = /bits/ 64 <702000000>;
69 opp-microvolt = <908000>;
71 opp-1001000000 {
72 opp-hz = /bits/ 64 <1001000000>;
73 opp-microvolt = <983000>;
75 opp-1105000000 {
76 opp-hz = /bits/ 64 <1105000000>;
77 opp-microvolt = <1009000>;
79 opp-1209000000 {
80 opp-hz = /bits/ 64 <1209000000>;
81 opp-microvolt = <1034000>;
83 opp-1300000000 {
84 opp-hz = /bits/ 64 <1300000000>;
85 opp-microvolt = <1057000>;
87 opp-1508000000 {
88 opp-hz = /bits/ 64 <1508000000>;
89 opp-microvolt = <1109000>;
91 opp-1703000000 {
92 opp-hz = /bits/ 64 <1703000000>;
93 opp-microvolt = <1125000>;
98 compatible = "operating-points-v2";
99 opp-shared;
100 opp-507000000 {
101 opp-hz = /bits/ 64 <507000000>;
102 opp-microvolt = <828000>;
104 opp-702000000 {
105 opp-hz = /bits/ 64 <702000000>;
106 opp-microvolt = <867000>;
108 opp-1001000000 {
109 opp-hz = /bits/ 64 <1001000000>;
110 opp-microvolt = <927000>;
112 opp-1209000000 {
113 opp-hz = /bits/ 64 <1209000000>;
114 opp-microvolt = <968000>;
116 opp-1404000000 {
117 opp-hz = /bits/ 64 <1404000000>;
118 opp-microvolt = <1007000>;
120 opp-1612000000 {
121 opp-hz = /bits/ 64 <1612000000>;
122 opp-microvolt = <1049000>;
124 opp-1807000000 {
125 opp-hz = /bits/ 64 <1807000000>;
126 opp-microvolt = <1089000>;
128 opp-2106000000 {
129 opp-hz = /bits/ 64 <2106000000>;
130 opp-microvolt = <1125000>;
135 #address-cells = <1>;
136 #size-cells = <0>;
138 cpu-map {
160 compatible = "arm,cortex-a53";
162 enable-method = "psci";
163 cpu-idle-states = <&CPU_SLEEP_0>;
164 #cooling-cells = <2>;
165 dynamic-power-coefficient = <263>;
168 clock-names = "cpu", "intermediate";
169 operating-points-v2 = <&cluster0_opp>;
170 capacity-dmips-mhz = <740>;
175 compatible = "arm,cortex-a53";
177 enable-method = "psci";
178 cpu-idle-states = <&CPU_SLEEP_0>;
179 #cooling-cells = <2>;
180 dynamic-power-coefficient = <263>;
183 clock-names = "cpu", "intermediate";
184 operating-points-v2 = <&cluster0_opp>;
185 capacity-dmips-mhz = <740>;
190 compatible = "arm,cortex-a72";
192 enable-method = "psci";
193 cpu-idle-states = <&CPU_SLEEP_0>;
194 #cooling-cells = <2>;
195 dynamic-power-coefficient = <530>;
198 clock-names = "cpu", "intermediate";
199 operating-points-v2 = <&cluster1_opp>;
200 capacity-dmips-mhz = <1024>;
205 compatible = "arm,cortex-a72";
207 enable-method = "psci";
208 cpu-idle-states = <&CPU_SLEEP_0>;
209 #cooling-cells = <2>;
210 dynamic-power-coefficient = <530>;
213 clock-names = "cpu", "intermediate";
214 operating-points-v2 = <&cluster1_opp>;
215 capacity-dmips-mhz = <1024>;
218 idle-states {
219 entry-method = "psci";
221 CPU_SLEEP_0: cpu-sleep-0 {
222 compatible = "arm,idle-state";
223 local-timer-stop;
224 entry-latency-us = <639>;
225 exit-latency-us = <680>;
226 min-residency-us = <1088>;
227 arm,psci-suspend-param = <0x0010000>;
233 compatible = "arm,cortex-a53-pmu";
236 interrupt-affinity = <&cpu0>, <&cpu1>;
240 compatible = "arm,cortex-a72-pmu";
243 interrupt-affinity = <&cpu2>, <&cpu3>;
247 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
255 compatible = "fixed-clock";
256 #clock-cells = <0>;
257 clock-frequency = <26000000>;
258 clock-output-names = "clk26m";
262 compatible = "fixed-clock";
263 #clock-cells = <0>;
264 clock-frequency = <32000>;
265 clock-output-names = "clk32k";
269 compatible = "fixed-clock";
270 #clock-cells = <0>;
271 clock-frequency = <0>;
272 clock-output-names = "cpum_ck";
275 thermal-zones {
277 polling-delay-passive = <1000>; /* milliseconds */
278 polling-delay = <1000>; /* milliseconds */
280 thermal-sensors = <&thermal>;
281 sustainable-power = <1500>; /* milliwatts */
284 threshold: trip-point0 {
290 target: trip-point1 {
303 cooling-maps {
306 cooling-device = <&cpu0 THERMAL_NO_LIMIT
314 cooling-device = <&cpu2 THERMAL_NO_LIMIT
324 reserved-memory {
325 #address-cells = <2>;
326 #size-cells = <2>;
329 compatible = "shared-dma-pool";
332 no-map;
337 compatible = "arm,armv8-timer";
338 interrupt-parent = <&gic>;
347 arm,no-tick-in-suspend;
351 #address-cells = <2>;
352 #size-cells = <2>;
353 compatible = "simple-bus";
356 topckgen: clock-controller@10000000 {
357 compatible = "mediatek,mt8173-topckgen";
359 #clock-cells = <1>;
362 infracfg: power-controller@10001000 {
363 compatible = "mediatek,mt8173-infracfg", "syscon";
365 #clock-cells = <1>;
366 #reset-cells = <1>;
369 pericfg: power-controller@10003000 {
370 compatible = "mediatek,mt8173-pericfg", "syscon";
372 #clock-cells = <1>;
373 #reset-cells = <1>;
377 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
382 compatible = "mediatek,mt8173-pinctrl";
384 mediatek,pctl-regmap = <&syscfg_pctl_a>;
385 pins-are-numbered;
386 gpio-controller;
387 #gpio-cells = <2>;
388 interrupt-controller;
389 #interrupt-cells = <2>;
399 input-enable;
400 bias-pull-down;
408 bias-disable;
416 bias-disable;
424 bias-disable;
432 bias-disable;
440 bias-disable;
448 bias-disable;
454 compatible = "syscon", "simple-mfd";
456 #power-domain-cells = <1>;
458 /* System Power Manager */
459 spm: power-controller {
460 compatible = "mediatek,mt8173-power-controller";
461 #address-cells = <1>;
462 #size-cells = <0>;
463 #power-domain-cells = <1>;
465 /* power domains of the SoC */
466 power-domain@MT8173_POWER_DOMAIN_VDEC {
469 clock-names = "mm";
470 #power-domain-cells = <0>;
472 power-domain@MT8173_POWER_DOMAIN_VENC {
476 clock-names = "mm", "venc";
477 #power-domain-cells = <0>;
479 power-domain@MT8173_POWER_DOMAIN_ISP {
482 clock-names = "mm";
483 #power-domain-cells = <0>;
485 power-domain@MT8173_POWER_DOMAIN_MM {
488 clock-names = "mm";
489 #power-domain-cells = <0>;
492 power-domain@MT8173_POWER_DOMAIN_VENC_LT {
496 clock-names = "mm", "venclt";
497 #power-domain-cells = <0>;
499 power-domain@MT8173_POWER_DOMAIN_AUDIO {
501 #power-domain-cells = <0>;
503 power-domain@MT8173_POWER_DOMAIN_USB {
505 #power-domain-cells = <0>;
507 mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
510 clock-names = "mfg";
511 #address-cells = <1>;
512 #size-cells = <0>;
513 #power-domain-cells = <1>;
515 power-domain@MT8173_POWER_DOMAIN_MFG_2D {
517 #address-cells = <1>;
518 #size-cells = <0>;
519 #power-domain-cells = <1>;
521 power-domain@MT8173_POWER_DOMAIN_MFG {
523 #power-domain-cells = <0>;
532 compatible = "mediatek,mt8173-wdt",
533 "mediatek,mt6589-wdt";
538 compatible = "mediatek,mt8173-timer",
539 "mediatek,mt6577-timer";
547 compatible = "mediatek,mt8173-pwrap";
549 reg-names = "pwrap";
552 reset-names = "pwrap";
554 clock-names = "spi", "wrap";
558 compatible = "mediatek,mt8173-cec";
566 compatible = "mediatek,mt8173-vpu";
569 reg-names = "tcm", "cfg_reg";
572 clock-names = "main";
573 memory-region = <&vpu_dma_reserved>;
576 sysirq: intpol-controller@10200620 {
577 compatible = "mediatek,mt8173-sysirq",
578 "mediatek,mt6577-sysirq";
579 interrupt-controller;
580 #interrupt-cells = <3>;
581 interrupt-parent = <&gic>;
586 compatible = "mediatek,mt8173-m4u";
590 clock-names = "bclk";
593 #iommu-cells = <1>;
597 compatible = "mediatek,mt8173-efuse";
599 #address-cells = <1>;
600 #size-cells = <1>;
606 apmixedsys: clock-controller@10209000 {
607 compatible = "mediatek,mt8173-apmixedsys";
609 #clock-cells = <1>;
612 hdmi_phy: hdmi-phy@10209100 {
613 compatible = "mediatek,mt8173-hdmi-phy";
616 clock-names = "pll_ref";
617 clock-output-names = "hdmitx_dig_cts";
620 #clock-cells = <0>;
621 #phy-cells = <0>;
626 compatible = "mediatek,mt8173-gce";
630 clock-names = "gce";
631 #mbox-cells = <2>;
634 mipi_tx0: dsi-phy@10215000 {
635 compatible = "mediatek,mt8173-mipi-tx";
638 clock-output-names = "mipi_tx0_pll";
639 #clock-cells = <0>;
640 #phy-cells = <0>;
644 mipi_tx1: dsi-phy@10216000 {
645 compatible = "mediatek,mt8173-mipi-tx";
648 clock-output-names = "mipi_tx1_pll";
649 #clock-cells = <0>;
650 #phy-cells = <0>;
654 gic: interrupt-controller@10221000 {
655 compatible = "arm,gic-400";
656 #interrupt-cells = <3>;
657 interrupt-parent = <&gic>;
658 interrupt-controller;
668 compatible = "mediatek,mt8173-auxadc";
671 clock-names = "main";
672 #io-channel-cells = <1>;
676 compatible = "mediatek,mt8173-uart",
677 "mediatek,mt6577-uart";
681 clock-names = "baud", "bus";
686 compatible = "mediatek,mt8173-uart",
687 "mediatek,mt6577-uart";
691 clock-names = "baud", "bus";
696 compatible = "mediatek,mt8173-uart",
697 "mediatek,mt6577-uart";
701 clock-names = "baud", "bus";
706 compatible = "mediatek,mt8173-uart",
707 "mediatek,mt6577-uart";
711 clock-names = "baud", "bus";
716 compatible = "mediatek,mt8173-i2c";
720 clock-div = <16>;
723 clock-names = "main", "dma";
724 pinctrl-names = "default";
725 pinctrl-0 = <&i2c0_pins_a>;
726 #address-cells = <1>;
727 #size-cells = <0>;
732 compatible = "mediatek,mt8173-i2c";
736 clock-div = <16>;
739 clock-names = "main", "dma";
740 pinctrl-names = "default";
741 pinctrl-0 = <&i2c1_pins_a>;
742 #address-cells = <1>;
743 #size-cells = <0>;
748 compatible = "mediatek,mt8173-i2c";
752 clock-div = <16>;
755 clock-names = "main", "dma";
756 pinctrl-names = "default";
757 pinctrl-0 = <&i2c2_pins_a>;
758 #address-cells = <1>;
759 #size-cells = <0>;
764 compatible = "mediatek,mt8173-spi";
765 #address-cells = <1>;
766 #size-cells = <0>;
772 clock-names = "parent-clk", "sel-clk", "spi-clk";
777 #thermal-sensor-cells = <0>;
778 compatible = "mediatek,mt8173-thermal";
782 clock-names = "therm", "auxadc";
786 nvmem-cells = <&thermal_calibration>;
787 nvmem-cell-names = "calibration-data";
791 compatible = "mediatek,mt8173-nor";
795 clock-names = "spi", "sf";
796 #address-cells = <1>;
797 #size-cells = <0>;
802 compatible = "mediatek,mt8173-i2c";
806 clock-div = <16>;
809 clock-names = "main", "dma";
810 pinctrl-names = "default";
811 pinctrl-0 = <&i2c3_pins_a>;
812 #address-cells = <1>;
813 #size-cells = <0>;
818 compatible = "mediatek,mt8173-i2c";
822 clock-div = <16>;
825 clock-names = "main", "dma";
826 pinctrl-names = "default";
827 pinctrl-0 = <&i2c4_pins_a>;
828 #address-cells = <1>;
829 #size-cells = <0>;
834 compatible = "mediatek,mt8173-hdmi-ddc";
838 clock-names = "ddc-i2c";
842 compatible = "mediatek,mt8173-i2c";
846 clock-div = <16>;
849 clock-names = "main", "dma";
850 pinctrl-names = "default";
851 pinctrl-0 = <&i2c6_pins_a>;
852 #address-cells = <1>;
853 #size-cells = <0>;
857 afe: audio-controller@11220000 {
858 compatible = "mediatek,mt8173-afe-pcm";
861 power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>;
872 clock-names = "infra_sys_audio_clk",
882 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
884 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
889 compatible = "mediatek,mt8173-mmc";
894 clock-names = "source", "hclk";
899 compatible = "mediatek,mt8173-mmc";
904 clock-names = "source", "hclk";
909 compatible = "mediatek,mt8173-mmc";
914 clock-names = "source", "hclk";
919 compatible = "mediatek,mt8173-mmc";
924 clock-names = "source", "hclk";
929 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
932 reg-names = "mac", "ippc";
937 power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
939 clock-names = "sys_ck", "ref_ck";
940 mediatek,syscon-wakeup = <&pericfg 0x400 1>;
941 #address-cells = <2>;
942 #size-cells = <2>;
947 compatible = "mediatek,mt8173-xhci",
948 "mediatek,mtk-xhci";
950 reg-names = "mac";
952 power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
954 clock-names = "sys_ck", "ref_ck";
959 u3phy: t-phy@11290000 {
960 compatible = "mediatek,mt8173-u3phy";
962 #address-cells = <2>;
963 #size-cells = <2>;
967 u2port0: usb-phy@11290800 {
970 clock-names = "ref";
971 #phy-cells = <1>;
975 u3port0: usb-phy@11290900 {
978 clock-names = "ref";
979 #phy-cells = <1>;
983 u2port1: usb-phy@11291000 {
986 clock-names = "ref";
987 #phy-cells = <1>;
993 compatible = "mediatek,mt8173-mmsys", "syscon";
995 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
996 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
997 assigned-clock-rates = <400000000>;
998 #clock-cells = <1>;
1001 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1005 compatible = "mediatek,mt8173-mdp-rdma",
1006 "mediatek,mt8173-mdp";
1010 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1017 compatible = "mediatek,mt8173-mdp-rdma";
1021 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1027 compatible = "mediatek,mt8173-mdp-rsz";
1030 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1034 compatible = "mediatek,mt8173-mdp-rsz";
1037 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1041 compatible = "mediatek,mt8173-mdp-rsz";
1044 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1048 compatible = "mediatek,mt8173-mdp-wdma";
1051 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1057 compatible = "mediatek,mt8173-mdp-wrot";
1060 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1066 compatible = "mediatek,mt8173-mdp-wrot";
1069 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1075 compatible = "mediatek,mt8173-disp-ovl";
1078 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1082 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1086 compatible = "mediatek,mt8173-disp-ovl";
1089 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1093 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1097 compatible = "mediatek,mt8173-disp-rdma";
1100 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1104 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1108 compatible = "mediatek,mt8173-disp-rdma";
1111 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1115 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1119 compatible = "mediatek,mt8173-disp-rdma";
1122 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1126 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1130 compatible = "mediatek,mt8173-disp-wdma";
1133 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1137 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1141 compatible = "mediatek,mt8173-disp-wdma";
1144 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1148 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1152 compatible = "mediatek,mt8173-disp-color";
1155 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1157 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
1161 compatible = "mediatek,mt8173-disp-color";
1164 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1166 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1170 compatible = "mediatek,mt8173-disp-aal";
1173 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1175 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1179 compatible = "mediatek,mt8173-disp-gamma";
1182 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1184 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1188 compatible = "mediatek,mt8173-disp-merge";
1190 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1195 compatible = "mediatek,mt8173-disp-split";
1197 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1202 compatible = "mediatek,mt8173-disp-split";
1204 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1209 compatible = "mediatek,mt8173-disp-ufoe";
1212 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1217 compatible = "mediatek,mt8173-dsi";
1220 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1224 clock-names = "engine", "digital", "hs";
1226 phy-names = "dphy";
1231 compatible = "mediatek,mt8173-dsi";
1234 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1238 clock-names = "engine", "digital", "hs";
1240 phy-names = "dphy";
1245 compatible = "mediatek,mt8173-dpi";
1248 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1252 clock-names = "pixel", "engine", "pll";
1257 remote-endpoint = <&hdmi0_in>;
1263 compatible = "mediatek,mt8173-disp-pwm",
1264 "mediatek,mt6595-disp-pwm";
1266 #pwm-cells = <2>;
1269 clock-names = "main", "mm";
1274 compatible = "mediatek,mt8173-disp-pwm",
1275 "mediatek,mt6595-disp-pwm";
1277 #pwm-cells = <2>;
1280 clock-names = "main", "mm";
1285 compatible = "mediatek,mt8173-disp-mutex";
1288 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1290 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
1295 compatible = "mediatek,mt8173-smi-larb";
1298 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1301 clock-names = "apb", "smi";
1305 compatible = "mediatek,mt8173-smi-common";
1307 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1310 clock-names = "apb", "smi";
1314 compatible = "mediatek,mt8173-disp-od";
1320 compatible = "mediatek,mt8173-hdmi";
1327 clock-names = "pixel", "pll", "bclk", "spdif";
1328 pinctrl-names = "default";
1329 pinctrl-0 = <&hdmi_pin>;
1331 phy-names = "hdmi";
1332 mediatek,syscon-hdmi = <&mmsys 0x900>;
1333 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1334 assigned-clock-parents = <&hdmi_phy>;
1338 #address-cells = <1>;
1339 #size-cells = <0>;
1345 remote-endpoint = <&dpi0_out>;
1352 compatible = "mediatek,mt8173-smi-larb";
1355 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1358 clock-names = "apb", "smi";
1361 imgsys: clock-controller@15000000 {
1362 compatible = "mediatek,mt8173-imgsys", "syscon";
1364 #clock-cells = <1>;
1368 compatible = "mediatek,mt8173-smi-larb";
1371 power-domains = <&spm MT8173_POWER_DOMAIN_ISP>;
1374 clock-names = "apb", "smi";
1377 vdecsys: clock-controller@16000000 {
1378 compatible = "mediatek,mt8173-vdecsys", "syscon";
1380 #clock-cells = <1>;
1384 compatible = "mediatek,mt8173-vcodec-dec";
1408 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1417 clock-names = "vcodecpll",
1425 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
1430 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
1433 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
1437 compatible = "mediatek,mt8173-smi-larb";
1440 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1443 clock-names = "apb", "smi";
1446 vencsys: clock-controller@18000000 {
1447 compatible = "mediatek,mt8173-vencsys", "syscon";
1449 #clock-cells = <1>;
1453 compatible = "mediatek,mt8173-smi-larb";
1456 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1459 clock-names = "apb", "smi";
1463 compatible = "mediatek,mt8173-vcodec-enc";
1480 clock-names = "venc_sel";
1481 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1482 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
1486 compatible = "mediatek,mt8173-jpgdec";
1491 clock-names = "jpgdec-smi",
1493 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1499 vencltsys: clock-controller@19000000 {
1500 compatible = "mediatek,mt8173-vencltsys", "syscon";
1502 #clock-cells = <1>;
1506 compatible = "mediatek,mt8173-smi-larb";
1509 power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;
1512 clock-names = "apb", "smi";
1516 compatible = "mediatek,mt8173-vcodec-enc-vp8";
1531 clock-names = "venc_lt_sel";
1532 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1533 assigned-clock-parents =