Lines Matching +full:power +full:- +full:domain +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8167-clk.h>
9 #include <dt-bindings/memory/mt8167-larb-port.h>
10 #include <dt-bindings/power/mt8167-power.h>
12 #include "mt8167-pinfunc.h"
21 compatible = "mediatek,mt8167-topckgen", "syscon";
23 #clock-cells = <1>;
27 compatible = "mediatek,mt8167-infracfg", "syscon";
29 #clock-cells = <1>;
33 compatible = "mediatek,mt8167-apmixedsys", "syscon";
35 #clock-cells = <1>;
39 compatible = "syscon", "simple-mfd";
41 #power-domain-cells = <1>;
43 spm: power-controller {
44 compatible = "mediatek,mt8167-power-controller";
45 #address-cells = <1>;
46 #size-cells = <0>;
47 #power-domain-cells = <1>;
49 /* power domains of the SoC */
50 power-domain@MT8167_POWER_DOMAIN_MM {
53 clock-names = "mm";
54 #power-domain-cells = <0>;
58 power-domain@MT8167_POWER_DOMAIN_VDEC {
62 clock-names = "mm", "vdec";
63 #power-domain-cells = <0>;
66 power-domain@MT8167_POWER_DOMAIN_ISP {
69 clock-names = "mm";
70 #power-domain-cells = <0>;
73 power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC {
77 clock-names = "axi_mfg", "mfg";
78 #address-cells = <1>;
79 #size-cells = <0>;
80 #power-domain-cells = <1>;
83 power-domain@MT8167_POWER_DOMAIN_MFG_2D {
85 #address-cells = <1>;
86 #size-cells = <0>;
87 #power-domain-cells = <1>;
89 power-domain@MT8167_POWER_DOMAIN_MFG {
91 #power-domain-cells = <0>;
97 power-domain@MT8167_POWER_DOMAIN_CONN {
99 #power-domain-cells = <0>;
106 compatible = "mediatek,mt8167-imgsys", "syscon";
108 #clock-cells = <1>;
112 compatible = "mediatek,mt8167-vdecsys", "syscon";
114 #clock-cells = <1>;
118 compatible = "mediatek,mt8167-pinctrl";
120 mediatek,pctl-regmap = <&syscfg_pctl>;
121 pins-are-numbered;
122 gpio-controller;
123 #gpio-cells = <2>;
124 interrupt-controller;
125 #interrupt-cells = <2>;
130 compatible = "mediatek,mt8167-mmsys", "syscon";
132 #clock-cells = <1>;
136 compatible = "mediatek,mt8167-smi-common";
140 clock-names = "apb", "smi";
141 power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
145 compatible = "mediatek,mt8167-smi-larb";
150 clock-names = "apb", "smi";
151 power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
155 compatible = "mediatek,mt8167-smi-larb";
160 clock-names = "apb", "smi";
161 power-domains = <&spm MT8167_POWER_DOMAIN_ISP>;
165 compatible = "mediatek,mt8167-smi-larb";
170 clock-names = "apb", "smi";
171 power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>;
175 compatible = "mediatek,mt8167-m4u";
179 #iommu-cells = <1>;