Lines Matching +full:agilex +full:- +full:clkmgr
1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
23 compatible = "shared-dma-pool";
26 no-map;
31 #address-cells = <1>;
32 #size-cells = <0>;
35 compatible = "arm,cortex-a53";
37 enable-method = "psci";
42 compatible = "arm,cortex-a53";
44 enable-method = "psci";
49 compatible = "arm,cortex-a53";
51 enable-method = "psci";
56 compatible = "arm,cortex-a53";
58 enable-method = "psci";
64 compatible = "arm,armv8-pmuv3";
69 interrupt-affinity = <&cpu0>,
73 interrupt-parent = <&intc>;
77 compatible = "arm,psci-0.2";
81 intc: interrupt-controller@fffc1000 {
82 compatible = "arm,gic-400", "arm,cortex-a15-gic";
83 #interrupt-cells = <3>;
84 interrupt-controller;
92 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
93 #clock-cells = <0>;
94 compatible = "fixed-clock";
97 cb_intosc_ls_clk: cb-intosc-ls-clk {
98 #clock-cells = <0>;
99 compatible = "fixed-clock";
102 f2s_free_clk: f2s-free-clk {
103 #clock-cells = <0>;
104 compatible = "fixed-clock";
108 #clock-cells = <0>;
109 compatible = "fixed-clock";
112 qspi_clk: qspi-clk {
113 #clock-cells = <0>;
114 compatible = "fixed-clock";
115 clock-frequency = <200000000>;
120 compatible = "arm,armv8-timer";
121 interrupt-parent = <&intc>;
129 #phy-cells = <0>;
130 compatible = "usb-nop-xceiv";
134 #address-cells = <1>;
135 #size-cells = <1>;
136 compatible = "simple-bus";
138 interrupt-parent = <&intc>;
142 #address-cells = <0x1>;
143 #size-cells = <0x1>;
144 compatible = "fpga-region";
145 fpga-mgr = <&fpga_mgr>;
148 clkmgr: clock-controller@ffd10000 { label
149 compatible = "intel,agilex-clkmgr";
151 #clock-cells = <1>;
155 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
158 interrupt-names = "macirq";
159 mac-address = [00 00 00 00 00 00];
161 reset-names = "stmmaceth", "stmmaceth-ocp";
162 tx-fifo-depth = <16384>;
163 rx-fifo-depth = <16384>;
164 snps,multicast-filter-bins = <256>;
166 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
167 clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
168 clock-names = "stmmaceth", "ptp_ref";
173 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
176 interrupt-names = "macirq";
177 mac-address = [00 00 00 00 00 00];
179 reset-names = "stmmaceth", "stmmaceth-ocp";
180 tx-fifo-depth = <16384>;
181 rx-fifo-depth = <16384>;
182 snps,multicast-filter-bins = <256>;
184 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
185 clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
186 clock-names = "stmmaceth", "ptp_ref";
191 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
194 interrupt-names = "macirq";
195 mac-address = [00 00 00 00 00 00];
197 reset-names = "stmmaceth", "stmmaceth-ocp";
198 tx-fifo-depth = <16384>;
199 rx-fifo-depth = <16384>;
200 snps,multicast-filter-bins = <256>;
202 altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
203 clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
204 clock-names = "stmmaceth", "ptp_ref";
209 #address-cells = <1>;
210 #size-cells = <0>;
211 compatible = "snps,dw-apb-gpio";
216 porta: gpio-controller@0 {
217 compatible = "snps,dw-apb-gpio-port";
218 gpio-controller;
219 #gpio-cells = <2>;
220 snps,nr-gpios = <24>;
222 interrupt-controller;
223 #interrupt-cells = <2>;
229 #address-cells = <1>;
230 #size-cells = <0>;
231 compatible = "snps,dw-apb-gpio";
236 portb: gpio-controller@0 {
237 compatible = "snps,dw-apb-gpio-port";
238 gpio-controller;
239 #gpio-cells = <2>;
240 snps,nr-gpios = <24>;
242 interrupt-controller;
243 #interrupt-cells = <2>;
249 #address-cells = <1>;
250 #size-cells = <0>;
251 compatible = "snps,designware-i2c";
255 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
260 #address-cells = <1>;
261 #size-cells = <0>;
262 compatible = "snps,designware-i2c";
266 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
271 #address-cells = <1>;
272 #size-cells = <0>;
273 compatible = "snps,designware-i2c";
277 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
282 #address-cells = <1>;
283 #size-cells = <0>;
284 compatible = "snps,designware-i2c";
288 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
293 #address-cells = <1>;
294 #size-cells = <0>;
295 compatible = "snps,designware-i2c";
299 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
304 #address-cells = <1>;
305 #size-cells = <0>;
306 compatible = "altr,socfpga-dw-mshc";
309 fifo-depth = <0x400>;
311 reset-names = "reset";
312 clocks = <&clkmgr AGILEX_L4_MP_CLK>,
313 <&clkmgr AGILEX_SDMMC_CLK>;
314 clock-names = "biu", "ciu";
319 nand: nand-controller@ffb90000 {
320 #address-cells = <1>;
321 #size-cells = <0>;
322 compatible = "altr,socfpga-denali-nand";
325 reg-names = "nand_data", "denali_reg";
327 clocks = <&clkmgr AGILEX_NAND_CLK>,
328 <&clkmgr AGILEX_NAND_X_CLK>,
329 <&clkmgr AGILEX_NAND_ECC_CLK>;
330 clock-names = "nand", "nand_x", "ecc";
336 compatible = "mmio-sram";
352 #dma-cells = <1>;
353 #dma-channels = <8>;
354 #dma-requests = <32>;
356 reset-names = "dma", "dma-ocp";
357 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
358 clock-names = "apb_pclk";
362 #reset-cells = <1>;
363 compatible = "altr,stratix10-rst-mgr";
368 compatible = "arm,mmu-500", "arm,smmu-v2";
370 #global-interrupts = <2>;
371 #iommu-cells = <1>;
372 interrupt-parent = <&intc>;
375 /* Global Non-secure Fault */
377 /* Non-secure Context Interrupts (32) */
410 stream-match-mask = <0x7ff0>;
411 clocks = <&clkmgr AGILEX_MPU_CCU_CLK>,
412 <&clkmgr AGILEX_L3_MAIN_FREE_CLK>,
413 <&clkmgr AGILEX_L4_MAIN_CLK>;
418 compatible = "snps,dw-apb-ssi";
419 #address-cells = <1>;
420 #size-cells = <0>;
424 reset-names = "spi";
425 reg-io-width = <4>;
426 num-cs = <4>;
427 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
432 compatible = "snps,dw-apb-ssi";
433 #address-cells = <1>;
434 #size-cells = <0>;
438 reset-names = "spi";
439 reg-io-width = <4>;
440 num-cs = <4>;
441 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
446 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
451 compatible = "snps,dw-apb-timer";
454 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
455 clock-names = "timer";
459 compatible = "snps,dw-apb-timer";
462 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
463 clock-names = "timer";
467 compatible = "snps,dw-apb-timer";
470 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
471 clock-names = "timer";
475 compatible = "snps,dw-apb-timer";
478 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
479 clock-names = "timer";
483 compatible = "snps,dw-apb-uart";
486 reg-shift = <2>;
487 reg-io-width = <4>;
490 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
494 compatible = "snps,dw-apb-uart";
497 reg-shift = <2>;
498 reg-io-width = <4>;
500 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
509 phy-names = "usb2-phy";
511 reset-names = "dwc2", "dwc2-ecc";
512 clocks = <&clkmgr AGILEX_USB_CLK>;
522 phy-names = "usb2-phy";
524 reset-names = "dwc2", "dwc2-ecc";
526 clocks = <&clkmgr AGILEX_USB_CLK>;
531 compatible = "snps,dw-wdt";
535 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
540 compatible = "snps,dw-wdt";
544 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
549 compatible = "snps,dw-wdt";
553 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
558 compatible = "snps,dw-wdt";
562 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
567 compatible = "altr,sdr-ctl", "syscon";
572 compatible = "altr,socfpga-s10-ecc-manager",
573 "altr,socfpga-a10-ecc-manager";
574 altr,sysmgr-syscon = <&sysmgr>;
575 #address-cells = <1>;
576 #size-cells = <1>;
578 interrupt-controller;
579 #interrupt-cells = <2>;
583 compatible = "altr,sdram-edac-s10";
584 altr,sdr-syscon = <&sdr>;
588 ocram-ecc@ff8cc000 {
589 compatible = "altr,socfpga-s10-ocram-ecc",
590 "altr,socfpga-a10-ocram-ecc";
592 altr,ecc-parent = <&ocram>;
596 usb0-ecc@ff8c4000 {
597 compatible = "altr,socfpga-s10-usb-ecc",
598 "altr,socfpga-usb-ecc";
600 altr,ecc-parent = <&usb0>;
604 emac0-rx-ecc@ff8c0000 {
605 compatible = "altr,socfpga-s10-eth-mac-ecc",
606 "altr,socfpga-eth-mac-ecc";
608 altr,ecc-parent = <&gmac0>;
612 emac0-tx-ecc@ff8c0400 {
613 compatible = "altr,socfpga-s10-eth-mac-ecc",
614 "altr,socfpga-eth-mac-ecc";
616 altr,ecc-parent = <&gmac0>;
620 sdmmca-ecc@ff8c8c00 {
621 compatible = "altr,socfpga-s10-sdmmc-ecc",
622 "altr,socfpga-sdmmc-ecc";
624 altr,ecc-parent = <&mmc>;
631 compatible = "cdns,qspi-nor";
632 #address-cells = <1>;
633 #size-cells = <0>;
637 cdns,fifo-depth = <128>;
638 cdns,fifo-width = <4>;
639 cdns,trigger-address = <0x00000000>;
647 compatible = "intel,agilex-svc";
649 memory-region = <&service_reserved>;
651 fpga_mgr: fpga-mgr {
652 compatible = "intel,agilex-soc-fpga-mgr";