Lines Matching +full:imx8 +full:- +full:ddr +full:- +full:pmu
1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2020 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/clock/imx8-lpcg.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
15 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
52 #address-cells = <2>;
53 #size-cells = <0>;
55 /* We have 1 clusters with 4 Cortex-A35 cores */
58 compatible = "arm,cortex-a35";
60 enable-method = "psci";
61 next-level-cache = <&A35_L2>;
63 operating-points-v2 = <&a35_opp_table>;
64 #cooling-cells = <2>;
69 compatible = "arm,cortex-a35";
71 enable-method = "psci";
72 next-level-cache = <&A35_L2>;
74 operating-points-v2 = <&a35_opp_table>;
75 #cooling-cells = <2>;
80 compatible = "arm,cortex-a35";
82 enable-method = "psci";
83 next-level-cache = <&A35_L2>;
85 operating-points-v2 = <&a35_opp_table>;
86 #cooling-cells = <2>;
91 compatible = "arm,cortex-a35";
93 enable-method = "psci";
94 next-level-cache = <&A35_L2>;
96 operating-points-v2 = <&a35_opp_table>;
97 #cooling-cells = <2>;
100 A35_L2: l2-cache0 {
105 a35_opp_table: opp-table {
106 compatible = "operating-points-v2";
107 opp-shared;
109 opp-900000000 {
110 opp-hz = /bits/ 64 <900000000>;
111 opp-microvolt = <1000000>;
112 clock-latency-ns = <150000>;
115 opp-1200000000 {
116 opp-hz = /bits/ 64 <1200000000>;
117 opp-microvolt = <1100000>;
118 clock-latency-ns = <150000>;
119 opp-suspend;
123 gic: interrupt-controller@51a00000 {
124 compatible = "arm,gic-v3";
127 #interrupt-cells = <3>;
128 interrupt-controller;
132 reserved-memory {
133 #address-cells = <2>;
134 #size-cells = <2>;
139 no-map;
143 pmu {
144 compatible = "arm,cortex-a35-pmu";
149 compatible = "arm,psci-1.0";
154 compatible = "fsl,imx-scu";
155 mbox-names = "tx0",
162 pd: imx8qx-pd {
163 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
164 #power-domain-cells = <1>;
167 clk: clock-controller {
168 compatible = "fsl,imx8qxp-clk";
169 #clock-cells = <2>;
171 clock-names = "xtal_32KHz", "xtal_24Mhz";
175 compatible = "fsl,imx8qxp-iomuxc";
178 ocotp: imx8qx-ocotp {
179 compatible = "fsl,imx8qxp-scu-ocotp";
180 #address-cells = <1>;
181 #size-cells = <1>;
184 scu_key: scu-key {
185 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
191 compatible = "fsl,imx8qxp-sc-rtc";
195 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
196 timeout-sec = <60>;
199 tsens: thermal-sensor {
200 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
201 #thermal-sensor-cells = <1>;
206 compatible = "arm,armv8-timer";
208 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
213 xtal32k: clock-xtal32k {
214 compatible = "fixed-clock";
215 #clock-cells = <0>;
216 clock-frequency = <32768>;
217 clock-output-names = "xtal_32KHz";
220 xtal24m: clock-xtal24m {
221 compatible = "fixed-clock";
222 #clock-cells = <0>;
223 clock-frequency = <24000000>;
224 clock-output-names = "xtal_24MHz";
227 thermal_zones: thermal-zones {
228 cpu-thermal0 {
229 polling-delay-passive = <250>;
230 polling-delay = <2000>;
231 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
247 cooling-maps {
250 cooling-device =
261 #include "imx8-ss-img.dtsi"
262 #include "imx8-ss-adma.dtsi"
263 #include "imx8-ss-conn.dtsi"
264 #include "imx8-ss-ddr.dtsi"
265 #include "imx8-ss-lsio.dtsi"
268 #include "imx8qxp-ss-img.dtsi"
269 #include "imx8qxp-ss-adma.dtsi"
270 #include "imx8qxp-ss-conn.dtsi"
271 #include "imx8qxp-ss-lsio.dtsi"