Lines Matching +full:psci +full:- +full:0

1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/pads-imx8qm.h>
14 	interrupt-parent = <&gic>;
15 	#address-cells = <2>;
16 	#size-cells = <2>;
26 		#address-cells = <2>;
27 		#size-cells = <0>;
29 		cpu-map {
55 		A53_0: cpu@0 {
57 			compatible = "arm,cortex-a53", "arm,armv8";
58 			reg = <0x0 0x0>;
59 			enable-method = "psci";
60 			next-level-cache = <&A53_L2>;
65 			compatible = "arm,cortex-a53", "arm,armv8";
66 			reg = <0x0 0x1>;
67 			enable-method = "psci";
68 			next-level-cache = <&A53_L2>;
73 			compatible = "arm,cortex-a53", "arm,armv8";
74 			reg = <0x0 0x2>;
75 			enable-method = "psci";
76 			next-level-cache = <&A53_L2>;
81 			compatible = "arm,cortex-a53", "arm,armv8";
82 			reg = <0x0 0x3>;
83 			enable-method = "psci";
84 			next-level-cache = <&A53_L2>;
89 			compatible = "arm,cortex-a72", "arm,armv8";
90 			reg = <0x0 0x100>;
91 			enable-method = "psci";
92 			next-level-cache = <&A72_L2>;
97 			compatible = "arm,cortex-a72", "arm,armv8";
98 			reg = <0x0 0x101>;
99 			enable-method = "psci";
100 			next-level-cache = <&A72_L2>;
103 		A53_L2: l2-cache0 {
107 		A72_L2: l2-cache1 {
112 	gic: interrupt-controller@51a00000 {
113 		compatible = "arm,gic-v3";
114 		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
115 		      <0x0 0x51b00000 0 0xC0000>, /* GICR */
116 		      <0x0 0x52000000 0 0x2000>,  /* GICC */
117 		      <0x0 0x52010000 0 0x1000>,  /* GICH */
118 		      <0x0 0x52020000 0 0x20000>; /* GICV */
119 		#interrupt-cells = <3>;
120 		interrupt-controller;
122 		interrupt-parent = <&gic>;
126 		compatible = "arm,armv8-pmuv3";
130 	psci {
131 		compatible = "arm,psci-1.0";
136 		compatible = "arm,armv8-timer";
138 			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
144 		compatible = "fsl,imx-scu";
145 		mbox-names = "tx0",
148 		mboxes = <&lsio_mu1 0 0
149 			  &lsio_mu1 1 0
152 		pd: imx8qx-pd {
153 			compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
154 			#power-domain-cells = <1>;
157 		clk: clock-controller {
158 			compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
159 			#clock-cells = <2>;
163 			compatible = "fsl,imx8qm-iomuxc";
169 	#include "imx8-ss-img.dtsi"
170 	#include "imx8-ss-dma.dtsi"
171 	#include "imx8-ss-conn.dtsi"
172 	#include "imx8-ss-lsio.dtsi"
175 #include "imx8qm-ss-img.dtsi"
176 #include "imx8qm-ss-dma.dtsi"
177 #include "imx8qm-ss-conn.dtsi"
178 #include "imx8qm-ss-lsio.dtsi"