Lines Matching +full:imx7ulp +full:- +full:lpi2c

1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2018-2019 NXP
8 	uart4_lpcg: clock-controller@5a4a0000 {
9 		compatible = "fsl,imx8qxp-lpcg";
11 		#clock-cells = <1>;
14 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
15 		clock-output-names = "uart4_lpcg_baud_clk",
17 		power-domains = <&pd IMX_SC_R_UART_4>;
22 	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
26 	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
30 	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
34 	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
38 	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
42 	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
46 	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
50 	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";