Lines Matching +full:assigned +full:- +full:clock +full:- +full:rates
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interconnect/imx8mq.h>
15 #include "imx8mq-pinfunc.h"
18 interrupt-parent = <&gpc>;
20 #address-cells = <2>;
21 #size-cells = <2>;
45 ckil: clock-ckil {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <32768>;
49 clock-output-names = "ckil";
52 osc_25m: clock-osc-25m {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <25000000>;
56 clock-output-names = "osc_25m";
59 osc_27m: clock-osc-27m {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <27000000>;
63 clock-output-names = "osc_27m";
66 clk_ext1: clock-ext1 {
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <133000000>;
70 clock-output-names = "clk_ext1";
73 clk_ext2: clock-ext2 {
74 compatible = "fixed-clock";
75 #clock-cells = <0>;
76 clock-frequency = <133000000>;
77 clock-output-names = "clk_ext2";
80 clk_ext3: clock-ext3 {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <133000000>;
84 clock-output-names = "clk_ext3";
87 clk_ext4: clock-ext4 {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency= <133000000>;
91 clock-output-names = "clk_ext4";
95 #address-cells = <1>;
96 #size-cells = <0>;
100 compatible = "arm,cortex-a53";
102 clock-latency = <61036>; /* two CLK32 periods */
104 enable-method = "psci";
105 next-level-cache = <&A53_L2>;
106 operating-points-v2 = <&a53_opp_table>;
107 #cooling-cells = <2>;
108 nvmem-cells = <&cpu_speed_grade>;
109 nvmem-cell-names = "speed_grade";
114 compatible = "arm,cortex-a53";
116 clock-latency = <61036>; /* two CLK32 periods */
118 enable-method = "psci";
119 next-level-cache = <&A53_L2>;
120 operating-points-v2 = <&a53_opp_table>;
121 #cooling-cells = <2>;
126 compatible = "arm,cortex-a53";
128 clock-latency = <61036>; /* two CLK32 periods */
130 enable-method = "psci";
131 next-level-cache = <&A53_L2>;
132 operating-points-v2 = <&a53_opp_table>;
133 #cooling-cells = <2>;
138 compatible = "arm,cortex-a53";
140 clock-latency = <61036>; /* two CLK32 periods */
142 enable-method = "psci";
143 next-level-cache = <&A53_L2>;
144 operating-points-v2 = <&a53_opp_table>;
145 #cooling-cells = <2>;
148 A53_L2: l2-cache0 {
153 a53_opp_table: opp-table {
154 compatible = "operating-points-v2";
155 opp-shared;
157 opp-800000000 {
158 opp-hz = /bits/ 64 <800000000>;
159 opp-microvolt = <900000>;
161 opp-supported-hw = <0xf>, <0x4>;
162 clock-latency-ns = <150000>;
163 opp-suspend;
166 opp-1000000000 {
167 opp-hz = /bits/ 64 <1000000000>;
168 opp-microvolt = <900000>;
170 opp-supported-hw = <0xe>, <0x3>;
171 clock-latency-ns = <150000>;
172 opp-suspend;
175 opp-1300000000 {
176 opp-hz = /bits/ 64 <1300000000>;
177 opp-microvolt = <1000000>;
178 opp-supported-hw = <0xc>, <0x4>;
179 clock-latency-ns = <150000>;
180 opp-suspend;
183 opp-1500000000 {
184 opp-hz = /bits/ 64 <1500000000>;
185 opp-microvolt = <1000000>;
186 opp-supported-hw = <0x8>, <0x3>;
187 clock-latency-ns = <150000>;
188 opp-suspend;
193 compatible = "arm,cortex-a53-pmu";
195 interrupt-parent = <&gic>;
199 compatible = "arm,psci-1.0";
203 thermal-zones {
204 cpu_thermal: cpu-thermal {
205 polling-delay-passive = <250>;
206 polling-delay = <2000>;
207 thermal-sensors = <&tmu 0>;
210 cpu_alert: cpu-alert {
216 cpu-crit {
223 cooling-maps {
226 cooling-device =
235 gpu-thermal {
236 polling-delay-passive = <250>;
237 polling-delay = <2000>;
238 thermal-sensors = <&tmu 1>;
241 gpu_alert: gpu-alert {
247 gpu-crit {
254 cooling-maps {
257 cooling-device =
263 vpu-thermal {
264 polling-delay-passive = <250>;
265 polling-delay = <2000>;
266 thermal-sensors = <&tmu 2>;
269 vpu-crit {
279 compatible = "arm,armv8-timer";
281 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
284 interrupt-parent = <&gic>;
285 arm,no-tick-in-suspend;
289 compatible = "fsl,imx8mq-soc", "simple-bus";
290 #address-cells = <1>;
291 #size-cells = <1>;
293 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
294 nvmem-cells = <&imx8mq_uid>;
295 nvmem-cell-names = "soc_unique_id";
298 compatible = "fsl,aips-bus", "simple-bus";
300 #address-cells = <1>;
301 #size-cells = <1>;
305 #sound-dai-cells = <0>;
306 compatible = "fsl,imx8mq-sai";
312 clock-names = "bus", "mclk1", "mclk2", "mclk3";
314 dma-names = "rx", "tx";
319 #sound-dai-cells = <0>;
320 compatible = "fsl,imx8mq-sai";
326 clock-names = "bus", "mclk1", "mclk2", "mclk3";
328 dma-names = "rx", "tx";
333 #sound-dai-cells = <0>;
334 compatible = "fsl,imx8mq-sai";
340 clock-names = "bus", "mclk1", "mclk2", "mclk3";
342 dma-names = "rx", "tx";
347 #sound-dai-cells = <0>;
348 compatible = "fsl,imx8mq-sai";
354 clock-names = "bus", "mclk1", "mclk2", "mclk3";
356 dma-names = "rx", "tx";
361 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
366 gpio-controller;
367 #gpio-cells = <2>;
368 interrupt-controller;
369 #interrupt-cells = <2>;
370 gpio-ranges = <&iomuxc 0 10 30>;
374 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
379 gpio-controller;
380 #gpio-cells = <2>;
381 interrupt-controller;
382 #interrupt-cells = <2>;
383 gpio-ranges = <&iomuxc 0 40 21>;
387 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
392 gpio-controller;
393 #gpio-cells = <2>;
394 interrupt-controller;
395 #interrupt-cells = <2>;
396 gpio-ranges = <&iomuxc 0 61 26>;
400 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
405 gpio-controller;
406 #gpio-cells = <2>;
407 interrupt-controller;
408 #interrupt-cells = <2>;
409 gpio-ranges = <&iomuxc 0 87 32>;
413 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
418 gpio-controller;
419 #gpio-cells = <2>;
420 interrupt-controller;
421 #interrupt-cells = <2>;
422 gpio-ranges = <&iomuxc 0 119 30>;
426 compatible = "fsl,imx8mq-tmu";
430 little-endian;
431 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
432 fsl,tmu-calibration = <0x00000000 0x00000023
475 #thermal-sensor-cells = <1>;
479 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
487 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
495 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
503 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
508 clock-names = "ipg", "ahb";
509 #dma-cells = <3>;
510 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
513 lcdif: lcd-controller@30320000 {
514 compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
518 clock-names = "pix";
519 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
523 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
526 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
528 interconnect-names = "dram";
533 remote-endpoint = <&mipi_dsi_lcdif_in>;
539 compatible = "fsl,imx8mq-iomuxc";
544 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
545 "syscon", "simple-mfd";
548 mux: mux-controller {
549 compatible = "mmio-mux";
550 #mux-control-cells = <1>;
551 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
556 compatible = "fsl,imx8mq-ocotp", "syscon";
559 #address-cells = <1>;
560 #size-cells = <1>;
562 imx8mq_uid: soc-uid@410 {
566 cpu_speed_grade: speed-grade@10 {
570 fec_mac_address: mac-address@90 {
576 compatible = "fsl,imx8mq-anatop", "syscon";
582 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
585 snvs_rtc: snvs-rtc-lp{
586 compatible = "fsl,sec-v4.0-mon-rtc-lp";
592 clock-names = "snvs-rtc";
595 snvs_pwrkey: snvs-powerkey {
596 compatible = "fsl,sec-v4.0-pwrkey";
600 clock-names = "snvs-pwrkey";
602 wakeup-source;
607 clk: clock-controller@30380000 {
608 compatible = "fsl,imx8mq-ccm";
612 #clock-cells = <1>;
616 clock-names = "ckil", "osc_25m", "osc_27m",
619 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
627 assigned-clock-rates = <0>, <0>,
634 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
642 src: reset-controller@30390000 {
643 compatible = "fsl,imx8mq-src", "syscon";
646 #reset-cells = <1>;
650 compatible = "fsl,imx8mq-gpc";
653 interrupt-parent = <&gic>;
654 interrupt-controller;
655 #interrupt-cells = <3>;
658 #address-cells = <1>;
659 #size-cells = <0>;
661 pgc_mipi: power-domain@0 {
662 #power-domain-cells = <0>;
681 pgc_pcie: power-domain@1 {
682 #power-domain-cells = <0>;
684 power-domains = <&pgc_pcie2>;
687 pgc_otg1: power-domain@2 {
688 #power-domain-cells = <0>;
692 pgc_otg2: power-domain@3 {
693 #power-domain-cells = <0>;
697 pgc_ddr1: power-domain@4 {
698 #power-domain-cells = <0>;
702 pgc_gpu: power-domain@5 {
703 #power-domain-cells = <0>;
711 pgc_vpu: power-domain@6 {
712 #power-domain-cells = <0>;
717 pgc_disp: power-domain@7 {
718 #power-domain-cells = <0>;
722 pgc_mipi_csi1: power-domain@8 {
723 #power-domain-cells = <0>;
727 pgc_mipi_csi2: power-domain@9 {
728 #power-domain-cells = <0>;
732 pgc_pcie2: power-domain@a {
733 #power-domain-cells = <0>;
741 compatible = "fsl,aips-bus", "simple-bus";
743 #address-cells = <1>;
744 #size-cells = <1>;
748 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
753 clock-names = "ipg", "per";
754 #pwm-cells = <2>;
759 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
764 clock-names = "ipg", "per";
765 #pwm-cells = <2>;
770 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
775 clock-names = "ipg", "per";
776 #pwm-cells = <2>;
781 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
786 clock-names = "ipg", "per";
787 #pwm-cells = <2>;
792 compatible = "nxp,sysctr-timer";
796 clock-names = "per";
801 compatible = "fsl,aips-bus", "simple-bus";
803 #address-cells = <1>;
804 #size-cells = <1>;
809 compatible = "fsl,imx35-spdif";
822 clock-names = "core", "rxtx0",
828 dma-names = "rx", "tx";
833 #address-cells = <1>;
834 #size-cells = <0>;
835 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
840 clock-names = "ipg", "per";
842 dma-names = "rx", "tx";
847 #address-cells = <1>;
848 #size-cells = <0>;
849 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
854 clock-names = "ipg", "per";
856 dma-names = "rx", "tx";
861 #address-cells = <1>;
862 #size-cells = <0>;
863 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
868 clock-names = "ipg", "per";
870 dma-names = "rx", "tx";
875 compatible = "fsl,imx8mq-uart",
876 "fsl,imx6q-uart";
881 clock-names = "ipg", "per";
886 compatible = "fsl,imx8mq-uart",
887 "fsl,imx6q-uart";
892 clock-names = "ipg", "per";
897 compatible = "fsl,imx8mq-uart",
898 "fsl,imx6q-uart";
903 clock-names = "ipg", "per";
908 compatible = "fsl,imx35-spdif";
921 clock-names = "core", "rxtx0",
927 dma-names = "rx", "tx";
932 #sound-dai-cells = <0>;
933 compatible = "fsl,imx8mq-sai";
939 clock-names = "bus", "mclk1", "mclk2", "mclk3";
941 dma-names = "rx", "tx";
946 #sound-dai-cells = <0>;
947 compatible = "fsl,imx8mq-sai";
953 clock-names = "bus", "mclk1", "mclk2", "mclk3";
955 dma-names = "rx", "tx";
960 compatible = "fsl,sec-v4.0";
961 #address-cells = <1>;
962 #size-cells = <1>;
968 clock-names = "aclk", "ipg";
971 compatible = "fsl,sec-v4.0-job-ring";
977 compatible = "fsl,sec-v4.0-job-ring";
983 compatible = "fsl,sec-v4.0-job-ring";
989 mipi_dsi: mipi-dsi@30a00000 {
990 compatible = "fsl,imx8mq-nwl-dsi";
997 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
998 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
1001 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
1003 assigned-clock-rates = <80000000>, <266000000>, <20000000>;
1005 mux-controls = <&mux 0>;
1006 power-domains = <&pgc_mipi>;
1008 phy-names = "dphy";
1013 reset-names = "byte", "dpi", "esc", "pclk";
1017 #address-cells = <1>;
1018 #size-cells = <0>;
1022 #address-cells = <1>;
1023 #size-cells = <0>;
1026 remote-endpoint = <&lcdif_mipi_dsi>;
1033 compatible = "fsl,imx8mq-mipi-dphy";
1036 clock-names = "phy_ref";
1037 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
1041 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
1044 assigned-clock-rates = <0>, <0>, <24000000>, <594000000>;
1045 #phy-cells = <0>;
1046 power-domains = <&pgc_mipi>;
1051 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1055 #address-cells = <1>;
1056 #size-cells = <0>;
1061 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1071 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1075 #address-cells = <1>;
1076 #size-cells = <0>;
1081 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1085 #address-cells = <1>;
1086 #size-cells = <0>;
1091 compatible = "fsl,imx8mq-uart",
1092 "fsl,imx6q-uart";
1097 clock-names = "ipg", "per";
1102 compatible = "fsl,imx8mq-mipi-csi2";
1107 clock-names = "core", "esc", "ui";
1108 assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
1111 assigned-clock-rates = <266000000>, <333000000>, <66000000>;
1112 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1115 power-domains = <&pgc_mipi_csi1>;
1119 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
1121 interconnect-names = "dram";
1125 #address-cells = <1>;
1126 #size-cells = <0>;
1132 remote-endpoint = <&csi1_ep>;
1139 compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
1143 clock-names = "mclk";
1148 remote-endpoint = <&csi1_mipi_ep>;
1154 compatible = "fsl,imx8mq-mipi-csi2";
1159 clock-names = "core", "esc", "ui";
1160 assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
1163 assigned-clock-rates = <266000000>, <333000000>, <66000000>;
1164 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1167 power-domains = <&pgc_mipi_csi2>;
1171 fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
1173 interconnect-names = "dram";
1177 #address-cells = <1>;
1178 #size-cells = <0>;
1184 remote-endpoint = <&csi2_ep>;
1191 compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
1195 clock-names = "mclk";
1200 remote-endpoint = <&csi2_mipi_ep>;
1206 compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
1210 #mbox-cells = <2>;
1214 compatible = "fsl,imx8mq-usdhc",
1215 "fsl,imx7d-usdhc";
1221 clock-names = "ipg", "ahb", "per";
1222 fsl,tuning-start-tap = <20>;
1223 fsl,tuning-step = <2>;
1224 bus-width = <4>;
1229 compatible = "fsl,imx8mq-usdhc",
1230 "fsl,imx7d-usdhc";
1236 clock-names = "ipg", "ahb", "per";
1237 fsl,tuning-start-tap = <20>;
1238 fsl,tuning-step = <2>;
1239 bus-width = <4>;
1244 #address-cells = <1>;
1245 #size-cells = <0>;
1246 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
1249 reg-names = "QuadSPI", "QuadSPI-memory";
1253 clock-names = "qspi_en", "qspi";
1258 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
1263 clock-names = "ipg", "ahb";
1264 #dma-cells = <3>;
1265 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1269 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1280 clock-names = "ipg", "ahb", "ptp",
1282 assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>,
1286 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1290 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1291 fsl,num-tx-queues = <3>;
1292 fsl,num-rx-queues = <3>;
1293 nvmem-cells = <&fec_mac_address>;
1294 nvmem-cell-names = "mac-address";
1296 fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
1302 compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc";
1306 #interconnect-cells = <1>;
1307 operating-points-v2 = <&noc_opp_table>;
1309 noc_opp_table: opp-table {
1310 compatible = "operating-points-v2";
1312 opp-133M {
1313 opp-hz = /bits/ 64 <133333333>;
1316 opp-400M {
1317 opp-hz = /bits/ 64 <400000000>;
1320 opp-800M {
1321 opp-hz = /bits/ 64 <800000000>;
1327 compatible = "fsl,aips-bus", "simple-bus";
1329 #address-cells = <1>;
1330 #size-cells = <1>;
1333 irqsteer: interrupt-controller@32e2d000 {
1334 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
1338 clock-names = "ipg";
1340 fsl,num-irqs = <64>;
1341 interrupt-controller;
1342 #interrupt-cells = <1>;
1354 clock-names = "core", "shader", "bus", "reg";
1355 #cooling-cells = <2>;
1356 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
1361 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
1366 assigned-clock-rates = <800000000>, <800000000>,
1368 power-domains = <&pgc_gpu>;
1372 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1377 clock-names = "bus_early", "ref", "suspend";
1378 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1380 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1382 assigned-clock-rates = <500000000>, <100000000>;
1385 phy-names = "usb2-phy", "usb3-phy";
1386 power-domains = <&pgc_otg1>;
1387 usb3-resume-missing-cas;
1391 usb3_phy0: usb-phy@381f0040 {
1392 compatible = "fsl,imx8mq-usb-phy";
1395 clock-names = "phy";
1396 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1397 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1398 assigned-clock-rates = <100000000>;
1399 #phy-cells = <0>;
1404 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1409 clock-names = "bus_early", "ref", "suspend";
1410 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1412 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1414 assigned-clock-rates = <500000000>, <100000000>;
1417 phy-names = "usb2-phy", "usb3-phy";
1418 power-domains = <&pgc_otg2>;
1419 usb3-resume-missing-cas;
1423 usb3_phy1: usb-phy@382f0040 {
1424 compatible = "fsl,imx8mq-usb-phy";
1427 clock-names = "phy";
1428 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1429 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1430 assigned-clock-rates = <100000000>;
1431 #phy-cells = <0>;
1435 vpu: video-codec@38300000 {
1436 compatible = "nxp,imx8mq-vpu";
1440 reg-names = "g1", "g2", "ctrl";
1443 interrupt-names = "g1", "g2";
1447 clock-names = "g1", "g2", "bus";
1448 assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
1452 assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
1456 assigned-clock-rates = <600000000>, <600000000>,
1458 power-domains = <&pgc_vpu>;
1462 compatible = "fsl,imx8mq-pcie";
1465 reg-names = "dbi", "config";
1466 #address-cells = <3>;
1467 #size-cells = <2>;
1469 bus-range = <0x00 0xff>;
1471 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1472 num-lanes = <1>;
1473 num-viewport = <4>;
1475 interrupt-names = "msi";
1476 #interrupt-cells = <1>;
1477 interrupt-map-mask = <0 0 0 0x7>;
1478 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1482 fsl,max-link-speed = <2>;
1483 linux,pci-domain = <0>;
1484 power-domains = <&pgc_pcie>;
1488 reset-names = "pciephy", "apps", "turnoff";
1489 assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
1492 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1495 assigned-clock-rates = <250000000>, <100000000>,
1501 compatible = "fsl,imx8mq-pcie";
1504 reg-names = "dbi", "config";
1505 #address-cells = <3>;
1506 #size-cells = <2>;
1509 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1510 num-lanes = <1>;
1511 num-viewport = <4>;
1513 interrupt-names = "msi";
1514 #interrupt-cells = <1>;
1515 interrupt-map-mask = <0 0 0 0x7>;
1516 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1520 fsl,max-link-speed = <2>;
1521 linux,pci-domain = <1>;
1522 power-domains = <&pgc_pcie>;
1526 reset-names = "pciephy", "apps", "turnoff";
1527 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
1530 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1533 assigned-clock-rates = <250000000>, <100000000>,
1538 gic: interrupt-controller@38800000 {
1539 compatible = "arm,gic-v3";
1545 #interrupt-cells = <3>;
1546 interrupt-controller;
1548 interrupt-parent = <&gic>;
1551 ddrc: memory-controller@3d400000 {
1552 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
1554 clock-names = "core", "pll", "alt", "apb";
1561 ddr-pmu@3d800000 {
1562 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1564 interrupt-parent = <&gic>;