Lines Matching +full:0 +full:x00000067
47 #clock-cells = <0>;
54 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #clock-cells = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #size-cells = <0>;
98 A53_0: cpu@0 {
101 reg = <0x0>;
115 reg = <0x1>;
127 reg = <0x2>;
139 reg = <0x3>;
161 opp-supported-hw = <0xf>, <0x4>;
170 opp-supported-hw = <0xe>, <0x3>;
178 opp-supported-hw = <0xc>, <0x4>;
186 opp-supported-hw = <0x8>, <0x3>;
207 thermal-sensors = <&tmu 0>;
288 soc@0 {
292 ranges = <0x0 0x0 0x0 0x3e000000>;
293 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
299 reg = <0x30000000 0x400000>;
302 ranges = <0x30000000 0x30000000 0x400000>;
305 #sound-dai-cells = <0>;
307 reg = <0x30010000 0x10000>;
313 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
319 #sound-dai-cells = <0>;
321 reg = <0x30030000 0x10000>;
327 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
333 #sound-dai-cells = <0>;
335 reg = <0x30040000 0x10000>;
341 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
347 #sound-dai-cells = <0>;
349 reg = <0x30050000 0x10000>;
355 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
362 reg = <0x30200000 0x10000>;
370 gpio-ranges = <&iomuxc 0 10 30>;
375 reg = <0x30210000 0x10000>;
383 gpio-ranges = <&iomuxc 0 40 21>;
388 reg = <0x30220000 0x10000>;
396 gpio-ranges = <&iomuxc 0 61 26>;
401 reg = <0x30230000 0x10000>;
409 gpio-ranges = <&iomuxc 0 87 32>;
414 reg = <0x30240000 0x10000>;
422 gpio-ranges = <&iomuxc 0 119 30>;
427 reg = <0x30260000 0x10000>;
431 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
432 fsl,tmu-calibration = <0x00000000 0x00000023
433 0x00000001 0x00000029
434 0x00000002 0x0000002f
435 0x00000003 0x00000035
436 0x00000004 0x0000003d
437 0x00000005 0x00000043
438 0x00000006 0x0000004b
439 0x00000007 0x00000051
440 0x00000008 0x00000057
441 0x00000009 0x0000005f
442 0x0000000a 0x00000067
443 0x0000000b 0x0000006f
445 0x00010000 0x0000001b
446 0x00010001 0x00000023
447 0x00010002 0x0000002b
448 0x00010003 0x00000033
449 0x00010004 0x0000003b
450 0x00010005 0x00000043
451 0x00010006 0x0000004b
452 0x00010007 0x00000055
453 0x00010008 0x0000005d
454 0x00010009 0x00000067
455 0x0001000a 0x00000070
457 0x00020000 0x00000017
458 0x00020001 0x00000023
459 0x00020002 0x0000002d
460 0x00020003 0x00000037
461 0x00020004 0x00000041
462 0x00020005 0x0000004b
463 0x00020006 0x00000057
464 0x00020007 0x00000063
465 0x00020008 0x0000006f
467 0x00030000 0x00000015
468 0x00030001 0x00000021
469 0x00030002 0x0000002d
470 0x00030003 0x00000039
471 0x00030004 0x00000045
472 0x00030005 0x00000053
473 0x00030006 0x0000005f
474 0x00030007 0x00000071>;
480 reg = <0x30280000 0x10000>;
488 reg = <0x30290000 0x10000>;
496 reg = <0x302a0000 0x10000>;
504 reg = <0x302c0000 0x10000>;
515 reg = <0x30320000 0x10000>;
526 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
531 port@0 {
540 reg = <0x30330000 0x10000>;
546 reg = <0x30340000 0x10000>;
551 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
557 reg = <0x30350000 0x10000>;
563 reg = <0x4 0x8>;
567 reg = <0x10 4>;
571 reg = <0x90 6>;
577 reg = <0x30360000 0x10000>;
582 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
583 reg = <0x30370000 0x10000>;
586 compatible = "fsl,sec-v4.0-mon-rtc-lp";
588 offset = <0x34>;
596 compatible = "fsl,sec-v4.0-pwrkey";
609 reg = <0x30380000 0x10000>;
627 assigned-clock-rates = <0>, <0>,
629 <0>,
630 <0>,
631 <0>,
636 <0>,
644 reg = <0x30390000 0x10000>;
651 reg = <0x303a0000 0x10000>;
659 #size-cells = <0>;
661 pgc_mipi: power-domain@0 {
662 #power-domain-cells = <0>;
682 #power-domain-cells = <0>;
688 #power-domain-cells = <0>;
693 #power-domain-cells = <0>;
698 #power-domain-cells = <0>;
703 #power-domain-cells = <0>;
712 #power-domain-cells = <0>;
718 #power-domain-cells = <0>;
723 #power-domain-cells = <0>;
728 #power-domain-cells = <0>;
733 #power-domain-cells = <0>;
742 reg = <0x30400000 0x400000>;
745 ranges = <0x30400000 0x30400000 0x400000>;
749 reg = <0x30660000 0x10000>;
760 reg = <0x30670000 0x10000>;
771 reg = <0x30680000 0x10000>;
782 reg = <0x30690000 0x10000>;
793 reg = <0x306a0000 0x20000>;
802 reg = <0x30800000 0x400000>;
805 ranges = <0x30800000 0x30800000 0x400000>,
806 <0x08000000 0x08000000 0x10000000>;
810 reg = <0x30810000 0x10000>;
827 dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>;
834 #size-cells = <0>;
836 reg = <0x30820000 0x10000>;
841 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
848 #size-cells = <0>;
850 reg = <0x30830000 0x10000>;
862 #size-cells = <0>;
864 reg = <0x30840000 0x10000>;
877 reg = <0x30860000 0x10000>;
888 reg = <0x30880000 0x10000>;
899 reg = <0x30890000 0x10000>;
909 reg = <0x308a0000 0x10000>;
926 dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>;
932 #sound-dai-cells = <0>;
934 reg = <0x308b0000 0x10000>;
940 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
946 #sound-dai-cells = <0>;
948 reg = <0x308c0000 0x10000>;
954 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
960 compatible = "fsl,sec-v4.0";
963 reg = <0x30900000 0x40000>;
964 ranges = <0 0x30900000 0x40000>;
971 compatible = "fsl,sec-v4.0-job-ring";
972 reg = <0x1000 0x1000>;
977 compatible = "fsl,sec-v4.0-job-ring";
978 reg = <0x2000 0x1000>;
983 compatible = "fsl,sec-v4.0-job-ring";
984 reg = <0x3000 0x1000>;
991 reg = <0x30a00000 0x300>;
1005 mux-controls = <&mux 0>;
1018 #size-cells = <0>;
1020 port@0 {
1021 reg = <0>;
1023 #size-cells = <0>;
1024 mipi_dsi_lcdif_in: endpoint@0 {
1025 reg = <0>;
1034 reg = <0x30a00300 0x100>;
1044 assigned-clock-rates = <0>, <0>, <24000000>, <594000000>;
1045 #phy-cells = <0>;
1052 reg = <0x30a20000 0x10000>;
1056 #size-cells = <0>;
1062 reg = <0x30a30000 0x10000>;
1066 #size-cells = <0>;
1072 reg = <0x30a40000 0x10000>;
1076 #size-cells = <0>;
1082 reg = <0x30a50000 0x10000>;
1086 #size-cells = <0>;
1093 reg = <0x30a60000 0x10000>;
1103 reg = <0x30a70000 0x1000>;
1119 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
1126 #size-cells = <0>;
1128 port@0 {
1129 reg = <0>;
1140 reg = <0x30a90000 0x10000>;
1155 reg = <0x30b60000 0x1000>;
1171 fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
1178 #size-cells = <0>;
1180 port@0 {
1181 reg = <0>;
1192 reg = <0x30b80000 0x10000>;
1207 reg = <0x30aa0000 0x10000>;
1216 reg = <0x30b40000 0x10000>;
1231 reg = <0x30b50000 0x10000>;
1245 #size-cells = <0>;
1247 reg = <0x30bb0000 0x10000>,
1248 <0x08000000 0x10000000>;
1259 reg = <0x30bd0000 0x10000>;
1270 reg = <0x30be0000 0x10000>;
1290 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1296 fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
1303 reg = <0x32700000 0x100000>;
1328 reg = <0x32c00000 0x400000>;
1331 ranges = <0x32c00000 0x32c00000 0x400000>;
1335 reg = <0x32e2d000 0x1000>;
1339 fsl,channel = <0>;
1348 reg = <0x38000000 0x40000>;
1367 <800000000>, <800000000>, <0>;
1373 reg = <0x38100000 0x10000>;
1393 reg = <0x381f0040 0x40>;
1399 #phy-cells = <0>;
1405 reg = <0x38200000 0x10000>;
1425 reg = <0x382f0040 0x40>;
1431 #phy-cells = <0>;
1437 reg = <0x38300000 0x10000>,
1438 <0x38310000 0x10000>,
1439 <0x38320000 0x10000>;
1457 <800000000>, <0>;
1463 reg = <0x33800000 0x400000>,
1464 <0x1ff00000 0x80000>;
1469 bus-range = <0x00 0xff>;
1470 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
1471 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1477 interrupt-map-mask = <0 0 0 0x7>;
1478 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1479 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1480 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1481 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1483 linux,pci-domain = <0>;
1502 reg = <0x33c00000 0x400000>,
1503 <0x27f00000 0x80000>;
1508 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
1509 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1515 interrupt-map-mask = <0 0 0 0x7>;
1516 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1517 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1518 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1519 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1540 reg = <0x38800000 0x10000>, /* GIC Dist */
1541 <0x38880000 0xc0000>, /* GICR */
1542 <0x31000000 0x2000>, /* GICC */
1543 <0x31010000 0x2000>, /* GICV */
1544 <0x31020000 0x2000>; /* GICH */
1553 reg = <0x3d400000 0x400000>;
1563 reg = <0x3d800000 0x400000>;