Lines Matching +full:0 +full:xcd
21 pwms = <&pwm1 0 5000000>;
22 brightness-levels = <0 100>;
26 default-brightness-level = <0>;
37 pinctrl-0 = <&pinctrl_gpio_keys>;
66 pinctrl-0 = <&pinctrl_gpio_leds>;
77 #clock-cells = <0>;
133 pinctrl-0 = <&pinctrl_pwr_en>;
145 pinctrl-0 = <&pinctrl_usdhc2_pwr>;
156 #sound-dai-cells = <0>;
162 pinctrl-0 = <&pinctrl_micsel>;
170 pinctrl-0 = <&pinctrl_hpdet>;
220 pinctrl-0 = <&pinctrl_spkamp>;
229 pinctrl-0 = <&pinctrl_haptic>;
237 pinctrl-0 = <&pinctrl_wifi_pwr_en>;
269 pinctrl-0 = <&pinctrl_fec1>;
278 #size-cells = <0>;
290 pinctrl-0 = <&pinctrl_i2c1>;
295 reg = <0x4b>;
297 pinctrl-0 = <&pinctrl_pmic>;
300 #clock-cells = <0>;
437 reg = <0x52>;
439 pinctrl-0 = <&pinctrl_typec>;
461 #size-cells = <0>;
463 port@0 {
464 reg = <0>;
484 reg = <0x68>;
486 pinctrl-0 = <&pinctrl_rtc>;
493 reg = <0x6b>;
495 pinctrl-0 = <&pinctrl_charger>;
511 pinctrl-0 = <&pinctrl_i2c3>;
516 reg = <0x1e>;
518 pinctrl-0 = <&pinctrl_imu>;
531 #sound-dai-cells = <0>;
532 reg = <0x0a>;
540 reg = <0x5d>;
542 pinctrl-0 = <&pinctrl_ts>;
544 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
546 irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
555 reg = <0x60>;
556 pinctrl-0 = <&pinctrl_prox>;
561 reg = <0x6a>;
564 mount-matrix = "1", "0", "0",
565 "0", "1", "0",
566 "0", "0", "-1";
573 MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* DSI_BL_PWM */
579 MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 /* nBT_DISABLE */
580 MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10 /* BT_HOST_WAKE */
586 MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80 /* CHRG_nINT */
592 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
593 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
594 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
595 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
596 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
597 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
598 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
599 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
600 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
601 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
602 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
603 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
604 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
605 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
606 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
607 MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f
613 MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16 /* TOUCH INT */
614 MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* TOUCH RST */
620 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16
626 MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
627 MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16
628 MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */
634 MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0xc6 /* nHAPTIC */
640 MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0xC0 /* HP_DET */
646 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f
647 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f
653 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f
654 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f
660 MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8 /* IMU_INT */
666 MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc6 /* MIC_SEL */
672 MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x81 /* MUTE */
678 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80 /* PMIC intr */
684 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x80 /* prox intr */
690 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06
696 MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80 /* RTC intr */
702 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
703 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
704 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
705 MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
706 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
712 MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6
713 MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6
714 MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6
715 MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6
721 MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16
722 MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80
728 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
729 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
735 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
736 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
737 MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
738 MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
744 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
745 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
751 MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49
752 MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49
753 MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49
754 MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49
755 MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49
761 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
762 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
763 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
764 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
765 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
766 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
767 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
768 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
769 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
770 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
771 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
772 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
778 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
779 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
780 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
781 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
782 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
783 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
784 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
785 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
786 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
787 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
788 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
789 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
795 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
796 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
797 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
798 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
799 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
800 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
801 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
802 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
803 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
804 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
805 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
806 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
812 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
818 MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */
824 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
825 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
826 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
827 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
828 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
829 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
835 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
836 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
837 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
838 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
839 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
840 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
846 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
847 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf
848 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf
849 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf
850 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf
851 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf
857 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
863 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06
869 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09 /* nWWAN_DISABLE */
870 MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */
871 MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */
883 #size-cells = <0>;
885 panel@0 {
887 reg = <0>;
919 pinctrl-0 = <&pinctrl_bl>;
933 pinctrl-0 = <&pinctrl_sai2>;
942 pinctrl-0 = <&pinctrl_sai6>;
952 pinctrl-0 = <&pinctrl_uart1>;
958 pinctrl-0 = <&pinctrl_uart3>;
964 pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
981 #size-cells = <0>;
985 port@0 {
986 reg = <0>;
1011 pinctrl-0 = <&pinctrl_usdhc1>;
1023 pinctrl-0 = <&pinctrl_usdhc2>;
1039 pinctrl-0 = <&pinctrl_wdog>;