Lines Matching +full:imx35 +full:- +full:ccm
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8mp-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a53";
51 clock-latency = <61036>;
53 enable-method = "psci";
54 next-level-cache = <&A53_L2>;
55 #cooling-cells = <2>;
60 compatible = "arm,cortex-a53";
62 clock-latency = <61036>;
64 enable-method = "psci";
65 next-level-cache = <&A53_L2>;
66 #cooling-cells = <2>;
71 compatible = "arm,cortex-a53";
73 clock-latency = <61036>;
75 enable-method = "psci";
76 next-level-cache = <&A53_L2>;
77 #cooling-cells = <2>;
82 compatible = "arm,cortex-a53";
84 clock-latency = <61036>;
86 enable-method = "psci";
87 next-level-cache = <&A53_L2>;
88 #cooling-cells = <2>;
91 A53_L2: l2-cache0 {
96 osc_32k: clock-osc-32k {
97 compatible = "fixed-clock";
98 #clock-cells = <0>;
99 clock-frequency = <32768>;
100 clock-output-names = "osc_32k";
103 osc_24m: clock-osc-24m {
104 compatible = "fixed-clock";
105 #clock-cells = <0>;
106 clock-frequency = <24000000>;
107 clock-output-names = "osc_24m";
110 clk_ext1: clock-ext1 {
111 compatible = "fixed-clock";
112 #clock-cells = <0>;
113 clock-frequency = <133000000>;
114 clock-output-names = "clk_ext1";
117 clk_ext2: clock-ext2 {
118 compatible = "fixed-clock";
119 #clock-cells = <0>;
120 clock-frequency = <133000000>;
121 clock-output-names = "clk_ext2";
124 clk_ext3: clock-ext3 {
125 compatible = "fixed-clock";
126 #clock-cells = <0>;
127 clock-frequency = <133000000>;
128 clock-output-names = "clk_ext3";
131 clk_ext4: clock-ext4 {
132 compatible = "fixed-clock";
133 #clock-cells = <0>;
134 clock-frequency= <133000000>;
135 clock-output-names = "clk_ext4";
138 reserved-memory {
139 #address-cells = <2>;
140 #size-cells = <2>;
145 no-map;
150 compatible = "arm,cortex-a53-pmu";
156 compatible = "arm,psci-1.0";
160 thermal-zones {
161 cpu-thermal {
162 polling-delay-passive = <250>;
163 polling-delay = <2000>;
164 thermal-sensors = <&tmu 0>;
179 cooling-maps {
182 cooling-device =
191 soc-thermal {
192 polling-delay-passive = <250>;
193 polling-delay = <2000>;
194 thermal-sensors = <&tmu 1>;
209 cooling-maps {
212 cooling-device =
223 compatible = "arm,armv8-timer";
228 clock-frequency = <8000000>;
229 arm,no-tick-in-suspend;
233 compatible = "fsl,imx8mp-soc", "simple-bus";
234 #address-cells = <1>;
235 #size-cells = <1>;
237 nvmem-cells = <&imx8mp_uid>;
238 nvmem-cell-names = "soc_unique_id";
241 compatible = "fsl,aips-bus", "simple-bus";
243 #address-cells = <1>;
244 #size-cells = <1>;
248 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
253 gpio-controller;
254 #gpio-cells = <2>;
255 interrupt-controller;
256 #interrupt-cells = <2>;
257 gpio-ranges = <&iomuxc 0 5 30>;
261 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
266 gpio-controller;
267 #gpio-cells = <2>;
268 interrupt-controller;
269 #interrupt-cells = <2>;
270 gpio-ranges = <&iomuxc 0 35 21>;
274 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
279 gpio-controller;
280 #gpio-cells = <2>;
281 interrupt-controller;
282 #interrupt-cells = <2>;
283 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
287 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
292 gpio-controller;
293 #gpio-cells = <2>;
294 interrupt-controller;
295 #interrupt-cells = <2>;
296 gpio-ranges = <&iomuxc 0 82 32>;
300 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
305 gpio-controller;
306 #gpio-cells = <2>;
307 interrupt-controller;
308 #interrupt-cells = <2>;
309 gpio-ranges = <&iomuxc 0 114 30>;
313 compatible = "fsl,imx8mp-tmu";
316 #thermal-sensor-cells = <1>;
320 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
328 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
336 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
344 compatible = "fsl,imx8mp-iomuxc";
348 gpr: iomuxc-gpr@30340000 {
349 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
354 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
358 #address-cells = <1>;
359 #size-cells = <1>;
361 imx8mp_uid: unique-id@420 {
365 cpu_speed_grade: speed-grade@10 {
369 eth_mac1: mac-address@90 {
375 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
381 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
384 snvs_rtc: snvs-rtc-lp {
385 compatible = "fsl,sec-v4.0-mon-rtc-lp";
391 clock-names = "snvs-rtc";
394 snvs_pwrkey: snvs-powerkey {
395 compatible = "fsl,sec-v4.0-pwrkey";
399 clock-names = "snvs-pwrkey";
401 wakeup-source;
406 clk: clock-controller@30380000 {
407 compatible = "fsl,imx8mp-ccm";
409 #clock-cells = <1>;
412 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
414 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
423 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
430 assigned-clock-rates = <0>, <0>,
440 src: reset-controller@30390000 {
441 compatible = "fsl,imx8mp-src", "syscon";
444 #reset-cells = <1>;
449 compatible = "fsl,aips-bus", "simple-bus";
451 #address-cells = <1>;
452 #size-cells = <1>;
456 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
461 clock-names = "ipg", "per";
462 #pwm-cells = <2>;
467 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
472 clock-names = "ipg", "per";
473 #pwm-cells = <2>;
478 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
483 clock-names = "ipg", "per";
484 #pwm-cells = <2>;
489 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
494 clock-names = "ipg", "per";
495 #pwm-cells = <2>;
500 compatible = "nxp,sysctr-timer";
504 clock-names = "per";
509 compatible = "fsl,aips-bus", "simple-bus";
511 #address-cells = <1>;
512 #size-cells = <1>;
516 #address-cells = <1>;
517 #size-cells = <0>;
518 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
523 clock-names = "ipg", "per";
525 dma-names = "rx", "tx";
530 #address-cells = <1>;
531 #size-cells = <0>;
532 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
537 clock-names = "ipg", "per";
539 dma-names = "rx", "tx";
544 #address-cells = <1>;
545 #size-cells = <0>;
546 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
551 clock-names = "ipg", "per";
553 dma-names = "rx", "tx";
558 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
563 clock-names = "ipg", "per";
565 dma-names = "rx", "tx";
570 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
575 clock-names = "ipg", "per";
577 dma-names = "rx", "tx";
582 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
587 clock-names = "ipg", "per";
592 compatible = "fsl,imx8mp-flexcan";
597 clock-names = "ipg", "per";
598 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
599 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
600 assigned-clock-rates = <40000000>;
601 fsl,clk-source = /bits/ 8 <0>;
602 fsl,stop-mode = <&gpr 0x10 4>;
607 compatible = "fsl,imx8mp-flexcan";
612 clock-names = "ipg", "per";
613 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
614 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
615 assigned-clock-rates = <40000000>;
616 fsl,clk-source = /bits/ 8 <0>;
617 fsl,stop-mode = <&gpr 0x10 5>;
622 compatible = "fsl,sec-v4.0";
623 #address-cells = <1>;
624 #size-cells = <1>;
630 clock-names = "aclk", "ipg";
633 compatible = "fsl,sec-v4.0-job-ring";
639 compatible = "fsl,sec-v4.0-job-ring";
645 compatible = "fsl,sec-v4.0-job-ring";
652 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
653 #address-cells = <1>;
654 #size-cells = <0>;
662 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
663 #address-cells = <1>;
664 #size-cells = <0>;
672 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
673 #address-cells = <1>;
674 #size-cells = <0>;
682 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
683 #address-cells = <1>;
684 #size-cells = <0>;
692 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
697 clock-names = "ipg", "per";
699 dma-names = "rx", "tx";
704 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
708 #mbox-cells = <2>;
712 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
715 #mbox-cells = <2>;
720 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
721 #address-cells = <1>;
722 #size-cells = <0>;
730 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
731 #address-cells = <1>;
732 #size-cells = <0>;
740 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
746 clock-names = "ipg", "ahb", "per";
747 fsl,tuning-start-tap = <20>;
748 fsl,tuning-step= <2>;
749 bus-width = <4>;
754 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
760 clock-names = "ipg", "ahb", "per";
761 fsl,tuning-start-tap = <20>;
762 fsl,tuning-step= <2>;
763 bus-width = <4>;
768 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
774 clock-names = "ipg", "ahb", "per";
775 fsl,tuning-start-tap = <20>;
776 fsl,tuning-step= <2>;
777 bus-width = <4>;
782 compatible = "nxp,imx8mp-fspi";
784 reg-names = "fspi_base", "fspi_mmap";
788 clock-names = "fspi", "fspi_en";
789 assigned-clock-rates = <80000000>;
790 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
791 #address-cells = <1>;
792 #size-cells = <0>;
796 sdma1: dma-controller@30bd0000 {
797 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
802 clock-names = "ipg", "ahb";
803 #dma-cells = <3>;
804 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
808 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
819 clock-names = "ipg", "ahb", "ptp",
821 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
825 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
829 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
830 fsl,num-tx-queues = <3>;
831 fsl,num-rx-queues = <3>;
832 nvmem-cells = <ð_mac1>;
833 nvmem-cell-names = "mac-address";
834 fsl,stop-mode = <&gpr 0x10 3>;
840 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
844 interrupt-names = "macirq", "eth_wake_irq";
849 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
850 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
853 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
856 assigned-clock-rates = <0>, <100000000>, <125000000>;
862 gic: interrupt-controller@38800000 {
863 compatible = "arm,gic-v3";
866 #interrupt-cells = <3>;
867 interrupt-controller;
869 interrupt-parent = <&gic>;
872 ddr-pmu@3d800000 {
873 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
878 usb3_phy0: usb-phy@381f0040 {
879 compatible = "fsl,imx8mp-usb-phy";
882 clock-names = "phy";
883 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
884 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
885 #phy-cells = <0>;
890 compatible = "fsl,imx8mp-dwc3";
894 clock-names = "hsio", "suspend";
896 #address-cells = <1>;
897 #size-cells = <1>;
898 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
908 clock-names = "bus_early", "ref", "suspend";
909 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
910 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
911 assigned-clock-rates = <500000000>;
914 phy-names = "usb2-phy", "usb3-phy";
915 snps,dis-u2-freeclk-exists-quirk;
920 usb3_phy1: usb-phy@382f0040 {
921 compatible = "fsl,imx8mp-usb-phy";
924 clock-names = "phy";
925 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
926 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
927 #phy-cells = <0>;
931 compatible = "fsl,imx8mp-dwc3";
935 clock-names = "hsio", "suspend";
937 #address-cells = <1>;
938 #size-cells = <1>;
939 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
949 clock-names = "bus_early", "ref", "suspend";
950 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
951 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
952 assigned-clock-rates = <500000000>;
955 phy-names = "usb2-phy", "usb3-phy";
956 snps,dis-u2-freeclk-exists-quirk;
961 compatible = "fsl,imx8mp-dsp";
963 mbox-names = "txdb0", "txdb1",
967 memory-region = <&dsp_reserved>;