Lines Matching +full:0 +full:x3e000000
45 #size-cells = <0>;
47 A53_0: cpu@0 {
50 reg = <0x0>;
61 reg = <0x1>;
72 reg = <0x2>;
83 reg = <0x3>;
98 #clock-cells = <0>;
105 #clock-cells = <0>;
112 #clock-cells = <0>;
119 #clock-cells = <0>;
126 #clock-cells = <0>;
133 #clock-cells = <0>;
144 reg = <0 0x92400000 0 0x2000000>;
164 thermal-sensors = <&tmu 0>;
232 soc@0 {
236 ranges = <0x0 0x0 0x0 0x3e000000>;
242 reg = <0x30000000 0x400000>;
249 reg = <0x30200000 0x10000>;
257 gpio-ranges = <&iomuxc 0 5 30>;
262 reg = <0x30210000 0x10000>;
270 gpio-ranges = <&iomuxc 0 35 21>;
275 reg = <0x30220000 0x10000>;
283 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
288 reg = <0x30230000 0x10000>;
296 gpio-ranges = <&iomuxc 0 82 32>;
301 reg = <0x30240000 0x10000>;
309 gpio-ranges = <&iomuxc 0 114 30>;
314 reg = <0x30260000 0x10000>;
321 reg = <0x30280000 0x10000>;
329 reg = <0x30290000 0x10000>;
337 reg = <0x302a0000 0x10000>;
345 reg = <0x30330000 0x10000>;
350 reg = <0x30340000 0x10000>;
355 reg = <0x30350000 0x10000>;
362 reg = <0x8 0x8>;
366 reg = <0x10 4>;
370 reg = <0x90 6>;
377 reg = <0x30360000 0x10000>;
381 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
382 reg = <0x30370000 0x10000>;
385 compatible = "fsl,sec-v4.0-mon-rtc-lp";
387 offset = <0x34>;
395 compatible = "fsl,sec-v4.0-pwrkey";
408 reg = <0x30380000 0x10000>;
430 assigned-clock-rates = <0>, <0>,
442 reg = <0x30390000 0x10000>;
450 reg = <0x30400000 0x400000>;
457 reg = <0x30660000 0x10000>;
468 reg = <0x30670000 0x10000>;
479 reg = <0x30680000 0x10000>;
490 reg = <0x30690000 0x10000>;
501 reg = <0x306a0000 0x20000>;
510 reg = <0x30800000 0x400000>;
517 #size-cells = <0>;
519 reg = <0x30820000 0x10000>;
524 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
531 #size-cells = <0>;
533 reg = <0x30830000 0x10000>;
545 #size-cells = <0>;
547 reg = <0x30840000 0x10000>;
559 reg = <0x30860000 0x10000>;
564 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
571 reg = <0x30880000 0x10000>;
576 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
583 reg = <0x30890000 0x10000>;
593 reg = <0x308c0000 0x10000>;
601 fsl,clk-source = /bits/ 8 <0>;
602 fsl,stop-mode = <&gpr 0x10 4>;
608 reg = <0x308d0000 0x10000>;
616 fsl,clk-source = /bits/ 8 <0>;
617 fsl,stop-mode = <&gpr 0x10 5>;
622 compatible = "fsl,sec-v4.0";
625 reg = <0x30900000 0x40000>;
626 ranges = <0 0x30900000 0x40000>;
633 compatible = "fsl,sec-v4.0-job-ring";
634 reg = <0x1000 0x1000>;
639 compatible = "fsl,sec-v4.0-job-ring";
640 reg = <0x2000 0x1000>;
645 compatible = "fsl,sec-v4.0-job-ring";
646 reg = <0x3000 0x1000>;
654 #size-cells = <0>;
655 reg = <0x30a20000 0x10000>;
664 #size-cells = <0>;
665 reg = <0x30a30000 0x10000>;
674 #size-cells = <0>;
675 reg = <0x30a40000 0x10000>;
684 #size-cells = <0>;
685 reg = <0x30a50000 0x10000>;
693 reg = <0x30a60000 0x10000>;
698 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
705 reg = <0x30aa0000 0x10000>;
713 reg = <0x30e60000 0x10000>;
722 #size-cells = <0>;
723 reg = <0x30ad0000 0x10000>;
732 #size-cells = <0>;
733 reg = <0x30ae0000 0x10000>;
741 reg = <0x30b40000 0x10000>;
755 reg = <0x30b50000 0x10000>;
769 reg = <0x30b60000 0x10000>;
783 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
792 #size-cells = <0>;
798 reg = <0x30bd0000 0x10000>;
809 reg = <0x30be0000 0x10000>;
829 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
834 fsl,stop-mode = <&gpr 0x10 3>;
841 reg = <0x30bf0000 0x10000>;
856 assigned-clock-rates = <0>, <100000000>, <125000000>;
857 intf_mode = <&gpr 0x4>;
864 reg = <0x38800000 0x10000>,
865 <0x38880000 0xc0000>;
874 reg = <0x3d800000 0x400000>;
880 reg = <0x381f0040 0x40>;
885 #phy-cells = <0>;
891 reg = <0x32f10100 0x8>;
898 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
904 reg = <0x38100000 0x10000>;
922 reg = <0x382f0040 0x40>;
927 #phy-cells = <0>;
932 reg = <0x32f10108 0x8>;
939 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
945 reg = <0x38200000 0x10000>;
962 reg = <0x3b6e8000 0x88000>;
965 mboxes = <&mu2 2 0>, <&mu2 2 1>,
966 <&mu2 3 0>, <&mu2 3 1>;