Lines Matching +full:psci +full:- +full:suspend +full:- +full:param
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8mn-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
43 #address-cells = <1>;
44 #size-cells = <0>;
46 idle-states {
47 entry-method = "psci";
49 cpu_pd_wait: cpu-pd-wait {
50 compatible = "arm,idle-state";
51 arm,psci-suspend-param = <0x0010033>;
52 local-timer-stop;
53 entry-latency-us = <1000>;
54 exit-latency-us = <700>;
55 min-residency-us = <2700>;
61 compatible = "arm,cortex-a53";
63 clock-latency = <61036>;
65 enable-method = "psci";
66 next-level-cache = <&A53_L2>;
67 operating-points-v2 = <&a53_opp_table>;
68 nvmem-cells = <&cpu_speed_grade>;
69 nvmem-cell-names = "speed_grade";
70 cpu-idle-states = <&cpu_pd_wait>;
71 #cooling-cells = <2>;
76 compatible = "arm,cortex-a53";
78 clock-latency = <61036>;
80 enable-method = "psci";
81 next-level-cache = <&A53_L2>;
82 operating-points-v2 = <&a53_opp_table>;
83 cpu-idle-states = <&cpu_pd_wait>;
84 #cooling-cells = <2>;
89 compatible = "arm,cortex-a53";
91 clock-latency = <61036>;
93 enable-method = "psci";
94 next-level-cache = <&A53_L2>;
95 operating-points-v2 = <&a53_opp_table>;
96 cpu-idle-states = <&cpu_pd_wait>;
97 #cooling-cells = <2>;
102 compatible = "arm,cortex-a53";
104 clock-latency = <61036>;
106 enable-method = "psci";
107 next-level-cache = <&A53_L2>;
108 operating-points-v2 = <&a53_opp_table>;
109 cpu-idle-states = <&cpu_pd_wait>;
110 #cooling-cells = <2>;
113 A53_L2: l2-cache0 {
118 a53_opp_table: opp-table {
119 compatible = "operating-points-v2";
120 opp-shared;
122 opp-1200000000 {
123 opp-hz = /bits/ 64 <1200000000>;
124 opp-microvolt = <850000>;
125 opp-supported-hw = <0xb00>, <0x7>;
126 clock-latency-ns = <150000>;
127 opp-suspend;
130 opp-1400000000 {
131 opp-hz = /bits/ 64 <1400000000>;
132 opp-microvolt = <950000>;
133 opp-supported-hw = <0x300>, <0x7>;
134 clock-latency-ns = <150000>;
135 opp-suspend;
138 opp-1500000000 {
139 opp-hz = /bits/ 64 <1500000000>;
140 opp-microvolt = <1000000>;
141 opp-supported-hw = <0x100>, <0x3>;
142 clock-latency-ns = <150000>;
143 opp-suspend;
147 osc_32k: clock-osc-32k {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <32768>;
151 clock-output-names = "osc_32k";
154 osc_24m: clock-osc-24m {
155 compatible = "fixed-clock";
156 #clock-cells = <0>;
157 clock-frequency = <24000000>;
158 clock-output-names = "osc_24m";
161 clk_ext1: clock-ext1 {
162 compatible = "fixed-clock";
163 #clock-cells = <0>;
164 clock-frequency = <133000000>;
165 clock-output-names = "clk_ext1";
168 clk_ext2: clock-ext2 {
169 compatible = "fixed-clock";
170 #clock-cells = <0>;
171 clock-frequency = <133000000>;
172 clock-output-names = "clk_ext2";
175 clk_ext3: clock-ext3 {
176 compatible = "fixed-clock";
177 #clock-cells = <0>;
178 clock-frequency = <133000000>;
179 clock-output-names = "clk_ext3";
182 clk_ext4: clock-ext4 {
183 compatible = "fixed-clock";
184 #clock-cells = <0>;
185 clock-frequency= <133000000>;
186 clock-output-names = "clk_ext4";
190 compatible = "arm,cortex-a53-pmu";
195 psci {
196 compatible = "arm,psci-1.0";
200 thermal-zones {
201 cpu-thermal {
202 polling-delay-passive = <250>;
203 polling-delay = <2000>;
204 thermal-sensors = <&tmu>;
219 cooling-maps {
222 cooling-device =
233 compatible = "arm,armv8-timer";
238 clock-frequency = <8000000>;
239 arm,no-tick-in-suspend;
243 compatible = "fsl,imx8mn-soc", "simple-bus";
244 #address-cells = <1>;
245 #size-cells = <1>;
247 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
248 nvmem-cells = <&imx8mn_uid>;
249 nvmem-cell-names = "soc_unique_id";
252 compatible = "fsl,aips-bus", "simple-bus";
254 #address-cells = <1>;
255 #size-cells = <1>;
258 spba2: spba-bus@30000000 {
259 compatible = "fsl,spba-bus", "simple-bus";
260 #address-cells = <1>;
261 #size-cells = <1>;
266 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
273 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
275 dma-names = "rx", "tx";
280 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
287 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
289 dma-names = "rx", "tx";
294 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
301 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
303 dma-names = "rx", "tx";
304 fsl,shared-interrupt;
310 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
317 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
319 dma-names = "rx", "tx";
323 micfil: audio-controller@30080000 {
324 compatible = "fsl,imx8mm-micfil";
335 clock-names = "ipg_clk", "ipg_clk_app",
338 dma-names = "rx";
343 compatible = "fsl,imx35-spdif";
356 clock-names = "core", "rxtx0",
362 dma-names = "rx", "tx";
367 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
374 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
376 dma-names = "rx", "tx";
381 compatible = "fsl,imx8mn-easrc";
385 clock-names = "mem";
390 dma-names = "ctx0_rx", "ctx0_tx",
394 firmware-name = "imx/easrc/easrc-imx8mn.bin";
395 fsl,asrc-rate = <8000>;
396 fsl,asrc-format = <2>;
402 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
407 gpio-controller;
408 #gpio-cells = <2>;
409 interrupt-controller;
410 #interrupt-cells = <2>;
411 gpio-ranges = <&iomuxc 0 10 30>;
415 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
420 gpio-controller;
421 #gpio-cells = <2>;
422 interrupt-controller;
423 #interrupt-cells = <2>;
424 gpio-ranges = <&iomuxc 0 40 21>;
428 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
433 gpio-controller;
434 #gpio-cells = <2>;
435 interrupt-controller;
436 #interrupt-cells = <2>;
437 gpio-ranges = <&iomuxc 0 61 26>;
441 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
446 gpio-controller;
447 #gpio-cells = <2>;
448 interrupt-controller;
449 #interrupt-cells = <2>;
450 gpio-ranges = <&iomuxc 21 108 11>;
454 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
459 gpio-controller;
460 #gpio-cells = <2>;
461 interrupt-controller;
462 #interrupt-cells = <2>;
463 gpio-ranges = <&iomuxc 0 119 30>;
467 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
470 #thermal-sensor-cells = <0>;
474 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
482 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
490 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
497 sdma3: dma-controller@302b0000 {
498 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
503 clock-names = "ipg", "ahb";
504 #dma-cells = <3>;
505 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
508 sdma2: dma-controller@302c0000 {
509 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
514 clock-names = "ipg", "ahb";
515 #dma-cells = <3>;
516 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
520 compatible = "fsl,imx8mn-iomuxc";
524 gpr: iomuxc-gpr@30340000 {
525 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
530 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
533 #address-cells = <1>;
534 #size-cells = <1>;
536 imx8mn_uid: unique-id@410 {
540 cpu_speed_grade: speed-grade@10 {
544 fec_mac_address: mac-address@90 {
550 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
556 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
559 snvs_rtc: snvs-rtc-lp {
560 compatible = "fsl,sec-v4.0-mon-rtc-lp";
566 clock-names = "snvs-rtc";
569 snvs_pwrkey: snvs-powerkey {
570 compatible = "fsl,sec-v4.0-pwrkey";
574 clock-names = "snvs-pwrkey";
576 wakeup-source;
581 clk: clock-controller@30380000 {
582 compatible = "fsl,imx8mn-ccm";
584 #clock-cells = <1>;
587 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
589 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
597 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
601 assigned-clock-rates = <0>, <0>, <0>,
609 src: reset-controller@30390000 {
610 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
613 #reset-cells = <1>;
618 compatible = "fsl,aips-bus", "simple-bus";
620 #address-cells = <1>;
621 #size-cells = <1>;
625 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
630 clock-names = "ipg", "per";
631 #pwm-cells = <2>;
636 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
641 clock-names = "ipg", "per";
642 #pwm-cells = <2>;
647 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
652 clock-names = "ipg", "per";
653 #pwm-cells = <2>;
658 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
663 clock-names = "ipg", "per";
664 #pwm-cells = <2>;
669 compatible = "nxp,sysctr-timer";
673 clock-names = "per";
678 compatible = "fsl,aips-bus", "simple-bus";
680 #address-cells = <1>;
681 #size-cells = <1>;
684 spba1: spba-bus@30800000 {
685 compatible = "fsl,spba-bus", "simple-bus";
686 #address-cells = <1>;
687 #size-cells = <1>;
692 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
693 #address-cells = <1>;
694 #size-cells = <0>;
699 clock-names = "ipg", "per";
701 dma-names = "rx", "tx";
706 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
707 #address-cells = <1>;
708 #size-cells = <0>;
713 clock-names = "ipg", "per";
715 dma-names = "rx", "tx";
720 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
721 #address-cells = <1>;
722 #size-cells = <0>;
727 clock-names = "ipg", "per";
729 dma-names = "rx", "tx";
734 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
739 clock-names = "ipg", "per";
741 dma-names = "rx", "tx";
746 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
751 clock-names = "ipg", "per";
753 dma-names = "rx", "tx";
758 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
763 clock-names = "ipg", "per";
769 compatible = "fsl,sec-v4.0";
770 #address-cells = <1>;
771 #size-cells = <1>;
777 clock-names = "aclk", "ipg";
780 compatible = "fsl,sec-v4.0-job-ring";
786 compatible = "fsl,sec-v4.0-job-ring";
792 compatible = "fsl,sec-v4.0-job-ring";
799 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
800 #address-cells = <1>;
801 #size-cells = <0>;
809 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
810 #address-cells = <1>;
811 #size-cells = <0>;
819 #address-cells = <1>;
820 #size-cells = <0>;
821 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
829 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
830 #address-cells = <1>;
831 #size-cells = <0>;
839 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
844 clock-names = "ipg", "per";
846 dma-names = "rx", "tx";
851 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
855 #mbox-cells = <2>;
859 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
865 clock-names = "ipg", "ahb", "per";
866 fsl,tuning-start-tap = <20>;
867 fsl,tuning-step= <2>;
868 bus-width = <4>;
873 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
879 clock-names = "ipg", "ahb", "per";
880 fsl,tuning-start-tap = <20>;
881 fsl,tuning-step= <2>;
882 bus-width = <4>;
887 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
893 clock-names = "ipg", "ahb", "per";
894 fsl,tuning-start-tap = <20>;
895 fsl,tuning-step= <2>;
896 bus-width = <4>;
901 #address-cells = <1>;
902 #size-cells = <0>;
903 compatible = "nxp,imx8mm-fspi";
905 reg-names = "fspi_base", "fspi_mmap";
909 clock-names = "fspi_en", "fspi";
913 sdma1: dma-controller@30bd0000 {
914 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
919 clock-names = "ipg", "ahb";
920 #dma-cells = <3>;
921 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
925 compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
936 clock-names = "ipg", "ahb", "ptp",
938 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
942 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
946 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
947 fsl,num-tx-queues = <3>;
948 fsl,num-rx-queues = <3>;
949 nvmem-cells = <&fec_mac_address>;
950 nvmem-cell-names = "mac-address";
952 fsl,stop-mode = <&gpr 0x10 3>;
959 compatible = "fsl,aips-bus", "simple-bus";
961 #address-cells = <1>;
962 #size-cells = <1>;
966 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
970 clock-names = "usb1_ctrl_root_clk";
971 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
972 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
979 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
980 #index-cells = <1>;
985 dma_apbh: dma-controller@33000000 {
986 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
992 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
993 #dma-cells = <1>;
994 dma-channels = <4>;
998 gpmi: nand-controller@33002000 {
999 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
1000 #address-cells = <1>;
1001 #size-cells = <1>;
1003 reg-names = "gpmi-nand", "bch";
1005 interrupt-names = "bch";
1008 clock-names = "gpmi_io", "gpmi_bch_apb";
1010 dma-names = "rx-tx";
1014 gic: interrupt-controller@38800000 {
1015 compatible = "arm,gic-v3";
1018 #interrupt-cells = <3>;
1019 interrupt-controller;
1023 ddrc: memory-controller@3d400000 {
1024 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
1026 clock-names = "core", "pll", "alt", "apb";
1033 ddr-pmu@3d800000 {
1034 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
1041 #phy-cells = <0>;
1042 compatible = "usb-nop-xceiv";
1044 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1045 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
1046 clock-names = "main_clk";