Lines Matching +full:psci +full:- +full:suspend +full:- +full:param
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8mm-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
43 #address-cells = <1>;
44 #size-cells = <0>;
46 idle-states {
47 entry-method = "psci";
49 cpu_pd_wait: cpu-pd-wait {
50 compatible = "arm,idle-state";
51 arm,psci-suspend-param = <0x0010033>;
52 local-timer-stop;
53 entry-latency-us = <1000>;
54 exit-latency-us = <700>;
55 min-residency-us = <2700>;
61 compatible = "arm,cortex-a53";
63 clock-latency = <61036>; /* two CLK32 periods */
65 enable-method = "psci";
66 next-level-cache = <&A53_L2>;
67 operating-points-v2 = <&a53_opp_table>;
68 nvmem-cells = <&cpu_speed_grade>;
69 nvmem-cell-names = "speed_grade";
70 cpu-idle-states = <&cpu_pd_wait>;
71 #cooling-cells = <2>;
76 compatible = "arm,cortex-a53";
78 clock-latency = <61036>; /* two CLK32 periods */
80 enable-method = "psci";
81 next-level-cache = <&A53_L2>;
82 operating-points-v2 = <&a53_opp_table>;
83 cpu-idle-states = <&cpu_pd_wait>;
84 #cooling-cells = <2>;
89 compatible = "arm,cortex-a53";
91 clock-latency = <61036>; /* two CLK32 periods */
93 enable-method = "psci";
94 next-level-cache = <&A53_L2>;
95 operating-points-v2 = <&a53_opp_table>;
96 cpu-idle-states = <&cpu_pd_wait>;
97 #cooling-cells = <2>;
102 compatible = "arm,cortex-a53";
104 clock-latency = <61036>; /* two CLK32 periods */
106 enable-method = "psci";
107 next-level-cache = <&A53_L2>;
108 operating-points-v2 = <&a53_opp_table>;
109 cpu-idle-states = <&cpu_pd_wait>;
110 #cooling-cells = <2>;
113 A53_L2: l2-cache0 {
118 a53_opp_table: opp-table {
119 compatible = "operating-points-v2";
120 opp-shared;
122 opp-1200000000 {
123 opp-hz = /bits/ 64 <1200000000>;
124 opp-microvolt = <850000>;
125 opp-supported-hw = <0xe>, <0x7>;
126 clock-latency-ns = <150000>;
127 opp-suspend;
130 opp-1600000000 {
131 opp-hz = /bits/ 64 <1600000000>;
132 opp-microvolt = <950000>;
133 opp-supported-hw = <0xc>, <0x7>;
134 clock-latency-ns = <150000>;
135 opp-suspend;
138 opp-1800000000 {
139 opp-hz = /bits/ 64 <1800000000>;
140 opp-microvolt = <1000000>;
141 opp-supported-hw = <0x8>, <0x3>;
142 clock-latency-ns = <150000>;
143 opp-suspend;
147 osc_32k: clock-osc-32k {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <32768>;
151 clock-output-names = "osc_32k";
154 osc_24m: clock-osc-24m {
155 compatible = "fixed-clock";
156 #clock-cells = <0>;
157 clock-frequency = <24000000>;
158 clock-output-names = "osc_24m";
161 clk_ext1: clock-ext1 {
162 compatible = "fixed-clock";
163 #clock-cells = <0>;
164 clock-frequency = <133000000>;
165 clock-output-names = "clk_ext1";
168 clk_ext2: clock-ext2 {
169 compatible = "fixed-clock";
170 #clock-cells = <0>;
171 clock-frequency = <133000000>;
172 clock-output-names = "clk_ext2";
175 clk_ext3: clock-ext3 {
176 compatible = "fixed-clock";
177 #clock-cells = <0>;
178 clock-frequency = <133000000>;
179 clock-output-names = "clk_ext3";
182 clk_ext4: clock-ext4 {
183 compatible = "fixed-clock";
184 #clock-cells = <0>;
185 clock-frequency= <133000000>;
186 clock-output-names = "clk_ext4";
189 psci {
190 compatible = "arm,psci-1.0";
195 compatible = "arm,cortex-a53-pmu";
201 compatible = "arm,armv8-timer";
203 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
206 clock-frequency = <8000000>;
207 arm,no-tick-in-suspend;
210 thermal-zones {
211 cpu-thermal {
212 polling-delay-passive = <250>;
213 polling-delay = <2000>;
214 thermal-sensors = <&tmu>;
229 cooling-maps {
232 cooling-device =
243 #phy-cells = <0>;
244 compatible = "usb-nop-xceiv";
246 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
247 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
248 clock-names = "main_clk";
252 #phy-cells = <0>;
253 compatible = "usb-nop-xceiv";
255 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
256 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
257 clock-names = "main_clk";
261 compatible = "fsl,imx8mm-soc", "simple-bus";
262 #address-cells = <1>;
263 #size-cells = <1>;
265 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
266 nvmem-cells = <&imx8mm_uid>;
267 nvmem-cell-names = "soc_unique_id";
270 compatible = "fsl,aips-bus", "simple-bus";
272 #address-cells = <1>;
273 #size-cells = <1>;
276 spba2: spba-bus@30000000 {
277 compatible = "fsl,spba-bus", "simple-bus";
278 #address-cells = <1>;
279 #size-cells = <1>;
284 #sound-dai-cells = <0>;
285 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
291 clock-names = "bus", "mclk1", "mclk2", "mclk3";
293 dma-names = "rx", "tx";
298 #sound-dai-cells = <0>;
299 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
305 clock-names = "bus", "mclk1", "mclk2", "mclk3";
307 dma-names = "rx", "tx";
312 #sound-dai-cells = <0>;
313 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
319 clock-names = "bus", "mclk1", "mclk2", "mclk3";
321 dma-names = "rx", "tx";
326 #sound-dai-cells = <0>;
327 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
333 clock-names = "bus", "mclk1", "mclk2", "mclk3";
335 dma-names = "rx", "tx";
340 #sound-dai-cells = <0>;
341 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
347 clock-names = "bus", "mclk1", "mclk2", "mclk3";
349 dma-names = "rx", "tx";
353 micfil: audio-controller@30080000 {
354 compatible = "fsl,imx8mm-micfil";
365 clock-names = "ipg_clk", "ipg_clk_app",
368 dma-names = "rx";
373 compatible = "fsl,imx35-spdif";
386 clock-names = "core", "rxtx0",
392 dma-names = "rx", "tx";
398 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
403 gpio-controller;
404 #gpio-cells = <2>;
405 interrupt-controller;
406 #interrupt-cells = <2>;
407 gpio-ranges = <&iomuxc 0 10 30>;
411 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
416 gpio-controller;
417 #gpio-cells = <2>;
418 interrupt-controller;
419 #interrupt-cells = <2>;
420 gpio-ranges = <&iomuxc 0 40 21>;
424 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
429 gpio-controller;
430 #gpio-cells = <2>;
431 interrupt-controller;
432 #interrupt-cells = <2>;
433 gpio-ranges = <&iomuxc 0 61 26>;
437 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
442 gpio-controller;
443 #gpio-cells = <2>;
444 interrupt-controller;
445 #interrupt-cells = <2>;
446 gpio-ranges = <&iomuxc 0 87 32>;
450 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
455 gpio-controller;
456 #gpio-cells = <2>;
457 interrupt-controller;
458 #interrupt-cells = <2>;
459 gpio-ranges = <&iomuxc 0 119 30>;
463 compatible = "fsl,imx8mm-tmu";
466 #thermal-sensor-cells = <0>;
470 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
478 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
486 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
493 sdma2: dma-controller@302c0000 {
494 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
499 clock-names = "ipg", "ahb";
500 #dma-cells = <3>;
501 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
504 sdma3: dma-controller@302b0000 {
505 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
510 clock-names = "ipg", "ahb";
511 #dma-cells = <3>;
512 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
516 compatible = "fsl,imx8mm-iomuxc";
520 gpr: iomuxc-gpr@30340000 {
521 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
526 compatible = "fsl,imx8mm-ocotp", "syscon";
530 #address-cells = <1>;
531 #size-cells = <1>;
533 imx8mm_uid: unique-id@410 {
537 cpu_speed_grade: speed-grade@10 {
541 fec_mac_address: mac-address@90 {
547 compatible = "fsl,imx8mm-anatop", "syscon";
552 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
555 snvs_rtc: snvs-rtc-lp {
556 compatible = "fsl,sec-v4.0-mon-rtc-lp";
562 clock-names = "snvs-rtc";
565 snvs_pwrkey: snvs-powerkey {
566 compatible = "fsl,sec-v4.0-pwrkey";
570 clock-names = "snvs-pwrkey";
572 wakeup-source;
577 clk: clock-controller@30380000 {
578 compatible = "fsl,imx8mm-ccm";
580 #clock-cells = <1>;
583 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
585 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
594 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
598 assigned-clock-rates = <0>, <0>, <0>,
607 src: reset-controller@30390000 {
608 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
611 #reset-cells = <1>;
616 compatible = "fsl,aips-bus", "simple-bus";
618 #address-cells = <1>;
619 #size-cells = <1>;
623 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
628 clock-names = "ipg", "per";
629 #pwm-cells = <2>;
634 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
639 clock-names = "ipg", "per";
640 #pwm-cells = <2>;
645 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
650 clock-names = "ipg", "per";
651 #pwm-cells = <2>;
656 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
661 clock-names = "ipg", "per";
662 #pwm-cells = <2>;
667 compatible = "nxp,sysctr-timer";
671 clock-names = "per";
676 compatible = "fsl,aips-bus", "simple-bus";
678 #address-cells = <1>;
679 #size-cells = <1>;
683 spba1: spba-bus@30800000 {
684 compatible = "fsl,spba-bus", "simple-bus";
685 #address-cells = <1>;
686 #size-cells = <1>;
691 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
692 #address-cells = <1>;
693 #size-cells = <0>;
698 clock-names = "ipg", "per";
700 dma-names = "rx", "tx";
705 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
706 #address-cells = <1>;
707 #size-cells = <0>;
712 clock-names = "ipg", "per";
714 dma-names = "rx", "tx";
719 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
720 #address-cells = <1>;
721 #size-cells = <0>;
726 clock-names = "ipg", "per";
728 dma-names = "rx", "tx";
733 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
738 clock-names = "ipg", "per";
740 dma-names = "rx", "tx";
745 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
750 clock-names = "ipg", "per";
752 dma-names = "rx", "tx";
757 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
762 clock-names = "ipg", "per";
768 compatible = "fsl,sec-v4.0";
769 #address-cells = <1>;
770 #size-cells = <1>;
776 clock-names = "aclk", "ipg";
779 compatible = "fsl,sec-v4.0-job-ring";
785 compatible = "fsl,sec-v4.0-job-ring";
791 compatible = "fsl,sec-v4.0-job-ring";
798 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
799 #address-cells = <1>;
800 #size-cells = <0>;
808 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
809 #address-cells = <1>;
810 #size-cells = <0>;
818 #address-cells = <1>;
819 #size-cells = <0>;
820 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
828 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
829 #address-cells = <1>;
830 #size-cells = <0>;
838 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
843 clock-names = "ipg", "per";
845 dma-names = "rx", "tx";
850 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
854 #mbox-cells = <2>;
858 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
864 clock-names = "ipg", "ahb", "per";
865 fsl,tuning-start-tap = <20>;
866 fsl,tuning-step= <2>;
867 bus-width = <4>;
872 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
878 clock-names = "ipg", "ahb", "per";
879 fsl,tuning-start-tap = <20>;
880 fsl,tuning-step= <2>;
881 bus-width = <4>;
886 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
892 clock-names = "ipg", "ahb", "per";
893 fsl,tuning-start-tap = <20>;
894 fsl,tuning-step= <2>;
895 bus-width = <4>;
900 #address-cells = <1>;
901 #size-cells = <0>;
902 compatible = "nxp,imx8mm-fspi";
904 reg-names = "fspi_base", "fspi_mmap";
908 clock-names = "fspi_en", "fspi";
912 sdma1: dma-controller@30bd0000 {
913 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
918 clock-names = "ipg", "ahb";
919 #dma-cells = <3>;
920 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
924 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
935 clock-names = "ipg", "ahb", "ptp",
937 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
941 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
945 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
946 fsl,num-tx-queues = <3>;
947 fsl,num-rx-queues = <3>;
948 nvmem-cells = <&fec_mac_address>;
949 nvmem-cell-names = "mac-address";
951 fsl,stop-mode = <&gpr 0x10 3>;
958 compatible = "fsl,aips-bus", "simple-bus";
960 #address-cells = <1>;
961 #size-cells = <1>;
965 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
969 clock-names = "usb1_ctrl_root_clk";
970 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
971 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
978 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
979 #index-cells = <1>;
984 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
988 clock-names = "usb1_ctrl_root_clk";
989 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
990 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
997 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
998 #index-cells = <1>;
1004 dma_apbh: dma-controller@33000000 {
1005 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1011 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1012 #dma-cells = <1>;
1013 dma-channels = <4>;
1017 gpmi: nand-controller@33002000{
1018 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
1019 #address-cells = <1>;
1020 #size-cells = <1>;
1022 reg-names = "gpmi-nand", "bch";
1024 interrupt-names = "bch";
1027 clock-names = "gpmi_io", "gpmi_bch_apb";
1029 dma-names = "rx-tx";
1033 gic: interrupt-controller@38800000 {
1034 compatible = "arm,gic-v3";
1037 #interrupt-cells = <3>;
1038 interrupt-controller;
1042 ddrc: memory-controller@3d400000 {
1043 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
1045 clock-names = "core", "pll", "alt", "apb";
1052 ddr-pmu@3d800000 {
1053 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";