Lines Matching +full:0 +full:x3e000000
44 #size-cells = <0>;
51 arm,psci-suspend-param = <0x0010033>;
59 A53_0: cpu@0 {
62 reg = <0x0>;
77 reg = <0x1>;
90 reg = <0x2>;
103 reg = <0x3>;
125 opp-supported-hw = <0xe>, <0x7>;
133 opp-supported-hw = <0xc>, <0x7>;
141 opp-supported-hw = <0x8>, <0x3>;
149 #clock-cells = <0>;
156 #clock-cells = <0>;
163 #clock-cells = <0>;
170 #clock-cells = <0>;
177 #clock-cells = <0>;
184 #clock-cells = <0>;
243 #phy-cells = <0>;
252 #phy-cells = <0>;
260 soc@0 {
264 ranges = <0x0 0x0 0x0 0x3e000000>;
265 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
271 reg = <0x30000000 0x400000>;
274 ranges = <0x30000000 0x30000000 0x400000>;
280 reg = <0x30000000 0x100000>;
284 #sound-dai-cells = <0>;
286 reg = <0x30010000 0x10000>;
292 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
298 #sound-dai-cells = <0>;
300 reg = <0x30020000 0x10000>;
306 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
312 #sound-dai-cells = <0>;
314 reg = <0x30030000 0x10000>;
320 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
326 #sound-dai-cells = <0>;
328 reg = <0x30050000 0x10000>;
334 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
340 #sound-dai-cells = <0>;
342 reg = <0x30060000 0x10000>;
348 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
355 reg = <0x30080000 0x10000>;
367 dmas = <&sdma2 24 25 0x80000000>;
374 reg = <0x30090000 0x10000>;
391 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
399 reg = <0x30200000 0x10000>;
407 gpio-ranges = <&iomuxc 0 10 30>;
412 reg = <0x30210000 0x10000>;
420 gpio-ranges = <&iomuxc 0 40 21>;
425 reg = <0x30220000 0x10000>;
433 gpio-ranges = <&iomuxc 0 61 26>;
438 reg = <0x30230000 0x10000>;
446 gpio-ranges = <&iomuxc 0 87 32>;
451 reg = <0x30240000 0x10000>;
459 gpio-ranges = <&iomuxc 0 119 30>;
464 reg = <0x30260000 0x10000>;
466 #thermal-sensor-cells = <0>;
471 reg = <0x30280000 0x10000>;
479 reg = <0x30290000 0x10000>;
487 reg = <0x302a0000 0x10000>;
495 reg = <0x302c0000 0x10000>;
506 reg = <0x302b0000 0x10000>;
517 reg = <0x30330000 0x10000>;
522 reg = <0x30340000 0x10000>;
527 reg = <0x30350000 0x10000>;
534 reg = <0x4 0x8>;
538 reg = <0x10 4>;
542 reg = <0x90 6>;
548 reg = <0x30360000 0x10000>;
552 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
553 reg = <0x30370000 0x10000>;
556 compatible = "fsl,sec-v4.0-mon-rtc-lp";
558 offset = <0x34>;
566 compatible = "fsl,sec-v4.0-pwrkey";
579 reg = <0x30380000 0x10000>;
598 assigned-clock-rates = <0>, <0>, <0>,
609 reg = <0x30390000 0x10000>;
617 reg = <0x30400000 0x400000>;
620 ranges = <0x30400000 0x30400000 0x400000>;
624 reg = <0x30660000 0x10000>;
635 reg = <0x30670000 0x10000>;
646 reg = <0x30680000 0x10000>;
657 reg = <0x30690000 0x10000>;
668 reg = <0x306a0000 0x20000>;
677 reg = <0x30800000 0x400000>;
680 ranges = <0x30800000 0x30800000 0x400000>,
681 <0x8000000 0x8000000 0x10000000>;
687 reg = <0x30800000 0x100000>;
693 #size-cells = <0>;
694 reg = <0x30820000 0x10000>;
699 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
707 #size-cells = <0>;
708 reg = <0x30830000 0x10000>;
721 #size-cells = <0>;
722 reg = <0x30840000 0x10000>;
734 reg = <0x30860000 0x10000>;
739 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
746 reg = <0x30880000 0x10000>;
751 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
758 reg = <0x30890000 0x10000>;
768 compatible = "fsl,sec-v4.0";
771 reg = <0x30900000 0x40000>;
772 ranges = <0 0x30900000 0x40000>;
779 compatible = "fsl,sec-v4.0-job-ring";
780 reg = <0x1000 0x1000>;
785 compatible = "fsl,sec-v4.0-job-ring";
786 reg = <0x2000 0x1000>;
791 compatible = "fsl,sec-v4.0-job-ring";
792 reg = <0x3000 0x1000>;
800 #size-cells = <0>;
801 reg = <0x30a20000 0x10000>;
810 #size-cells = <0>;
811 reg = <0x30a30000 0x10000>;
819 #size-cells = <0>;
821 reg = <0x30a40000 0x10000>;
830 #size-cells = <0>;
831 reg = <0x30a50000 0x10000>;
839 reg = <0x30a60000 0x10000>;
844 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
851 reg = <0x30aa0000 0x10000>;
859 reg = <0x30b40000 0x10000>;
873 reg = <0x30b50000 0x10000>;
887 reg = <0x30b60000 0x10000>;
901 #size-cells = <0>;
903 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
914 reg = <0x30bd0000 0x10000>;
925 reg = <0x30be0000 0x10000>;
945 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
951 fsl,stop-mode = <&gpr 0x10 3>;
959 reg = <0x32c00000 0x400000>;
962 ranges = <0x32c00000 0x32c00000 0x400000>;
966 reg = <0x32e40000 0x200>;
973 fsl,usbmisc = <&usbmisc1 0>;
980 reg = <0x32e40200 0x200>;
985 reg = <0x32e50000 0x200>;
992 fsl,usbmisc = <&usbmisc2 0>;
999 reg = <0x32e50200 0x200>;
1006 reg = <0x33000000 0x2000>;
1021 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1028 dmas = <&dma_apbh 0>;
1035 reg = <0x38800000 0x10000>, /* GIC Dist */
1036 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
1044 reg = <0x3d400000 0x400000>;
1054 reg = <0x3d800000 0x400000>;