Lines Matching +full:combined +full:- +full:sensors
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
28 // 8 clusters having 2 Cortex-A72 cores each
31 compatible = "arm,cortex-a72";
32 enable-method = "psci";
35 d-cache-size = <0x8000>;
36 d-cache-line-size = <64>;
37 d-cache-sets = <128>;
38 i-cache-size = <0xC000>;
39 i-cache-line-size = <64>;
40 i-cache-sets = <192>;
41 next-level-cache = <&cluster0_l2>;
42 cpu-idle-states = <&cpu_pw15>;
43 #cooling-cells = <2>;
48 compatible = "arm,cortex-a72";
49 enable-method = "psci";
52 d-cache-size = <0x8000>;
53 d-cache-line-size = <64>;
54 d-cache-sets = <128>;
55 i-cache-size = <0xC000>;
56 i-cache-line-size = <64>;
57 i-cache-sets = <192>;
58 next-level-cache = <&cluster0_l2>;
59 cpu-idle-states = <&cpu_pw15>;
60 #cooling-cells = <2>;
65 compatible = "arm,cortex-a72";
66 enable-method = "psci";
69 d-cache-size = <0x8000>;
70 d-cache-line-size = <64>;
71 d-cache-sets = <128>;
72 i-cache-size = <0xC000>;
73 i-cache-line-size = <64>;
74 i-cache-sets = <192>;
75 next-level-cache = <&cluster1_l2>;
76 cpu-idle-states = <&cpu_pw15>;
77 #cooling-cells = <2>;
82 compatible = "arm,cortex-a72";
83 enable-method = "psci";
86 d-cache-size = <0x8000>;
87 d-cache-line-size = <64>;
88 d-cache-sets = <128>;
89 i-cache-size = <0xC000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <192>;
92 next-level-cache = <&cluster1_l2>;
93 cpu-idle-states = <&cpu_pw15>;
94 #cooling-cells = <2>;
99 compatible = "arm,cortex-a72";
100 enable-method = "psci";
103 d-cache-size = <0x8000>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 i-cache-size = <0xC000>;
107 i-cache-line-size = <64>;
108 i-cache-sets = <192>;
109 next-level-cache = <&cluster2_l2>;
110 cpu-idle-states = <&cpu_pw15>;
111 #cooling-cells = <2>;
116 compatible = "arm,cortex-a72";
117 enable-method = "psci";
120 d-cache-size = <0x8000>;
121 d-cache-line-size = <64>;
122 d-cache-sets = <128>;
123 i-cache-size = <0xC000>;
124 i-cache-line-size = <64>;
125 i-cache-sets = <192>;
126 next-level-cache = <&cluster2_l2>;
127 cpu-idle-states = <&cpu_pw15>;
128 #cooling-cells = <2>;
133 compatible = "arm,cortex-a72";
134 enable-method = "psci";
137 d-cache-size = <0x8000>;
138 d-cache-line-size = <64>;
139 d-cache-sets = <128>;
140 i-cache-size = <0xC000>;
141 i-cache-line-size = <64>;
142 i-cache-sets = <192>;
143 next-level-cache = <&cluster3_l2>;
144 cpu-idle-states = <&cpu_pw15>;
145 #cooling-cells = <2>;
150 compatible = "arm,cortex-a72";
151 enable-method = "psci";
154 d-cache-size = <0x8000>;
155 d-cache-line-size = <64>;
156 d-cache-sets = <128>;
157 i-cache-size = <0xC000>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <192>;
160 next-level-cache = <&cluster3_l2>;
161 cpu-idle-states = <&cpu_pw15>;
162 #cooling-cells = <2>;
167 compatible = "arm,cortex-a72";
168 enable-method = "psci";
171 d-cache-size = <0x8000>;
172 d-cache-line-size = <64>;
173 d-cache-sets = <128>;
174 i-cache-size = <0xC000>;
175 i-cache-line-size = <64>;
176 i-cache-sets = <192>;
177 next-level-cache = <&cluster4_l2>;
178 cpu-idle-states = <&cpu_pw15>;
179 #cooling-cells = <2>;
184 compatible = "arm,cortex-a72";
185 enable-method = "psci";
188 d-cache-size = <0x8000>;
189 d-cache-line-size = <64>;
190 d-cache-sets = <128>;
191 i-cache-size = <0xC000>;
192 i-cache-line-size = <64>;
193 i-cache-sets = <192>;
194 next-level-cache = <&cluster4_l2>;
195 cpu-idle-states = <&cpu_pw15>;
196 #cooling-cells = <2>;
201 compatible = "arm,cortex-a72";
202 enable-method = "psci";
205 d-cache-size = <0x8000>;
206 d-cache-line-size = <64>;
207 d-cache-sets = <128>;
208 i-cache-size = <0xC000>;
209 i-cache-line-size = <64>;
210 i-cache-sets = <192>;
211 next-level-cache = <&cluster5_l2>;
212 cpu-idle-states = <&cpu_pw15>;
213 #cooling-cells = <2>;
218 compatible = "arm,cortex-a72";
219 enable-method = "psci";
222 d-cache-size = <0x8000>;
223 d-cache-line-size = <64>;
224 d-cache-sets = <128>;
225 i-cache-size = <0xC000>;
226 i-cache-line-size = <64>;
227 i-cache-sets = <192>;
228 next-level-cache = <&cluster5_l2>;
229 cpu-idle-states = <&cpu_pw15>;
230 #cooling-cells = <2>;
235 compatible = "arm,cortex-a72";
236 enable-method = "psci";
239 d-cache-size = <0x8000>;
240 d-cache-line-size = <64>;
241 d-cache-sets = <128>;
242 i-cache-size = <0xC000>;
243 i-cache-line-size = <64>;
244 i-cache-sets = <192>;
245 next-level-cache = <&cluster6_l2>;
246 cpu-idle-states = <&cpu_pw15>;
247 #cooling-cells = <2>;
252 compatible = "arm,cortex-a72";
253 enable-method = "psci";
256 d-cache-size = <0x8000>;
257 d-cache-line-size = <64>;
258 d-cache-sets = <128>;
259 i-cache-size = <0xC000>;
260 i-cache-line-size = <64>;
261 i-cache-sets = <192>;
262 next-level-cache = <&cluster6_l2>;
263 cpu-idle-states = <&cpu_pw15>;
264 #cooling-cells = <2>;
269 compatible = "arm,cortex-a72";
270 enable-method = "psci";
273 d-cache-size = <0x8000>;
274 d-cache-line-size = <64>;
275 d-cache-sets = <128>;
276 i-cache-size = <0xC000>;
277 i-cache-line-size = <64>;
278 i-cache-sets = <192>;
279 next-level-cache = <&cluster7_l2>;
280 cpu-idle-states = <&cpu_pw15>;
281 #cooling-cells = <2>;
286 compatible = "arm,cortex-a72";
287 enable-method = "psci";
290 d-cache-size = <0x8000>;
291 d-cache-line-size = <64>;
292 d-cache-sets = <128>;
293 i-cache-size = <0xC000>;
294 i-cache-line-size = <64>;
295 i-cache-sets = <192>;
296 next-level-cache = <&cluster7_l2>;
297 cpu-idle-states = <&cpu_pw15>;
298 #cooling-cells = <2>;
301 cluster0_l2: l2-cache0 {
303 cache-size = <0x100000>;
304 cache-line-size = <64>;
305 cache-sets = <1024>;
306 cache-level = <2>;
309 cluster1_l2: l2-cache1 {
311 cache-size = <0x100000>;
312 cache-line-size = <64>;
313 cache-sets = <1024>;
314 cache-level = <2>;
317 cluster2_l2: l2-cache2 {
319 cache-size = <0x100000>;
320 cache-line-size = <64>;
321 cache-sets = <1024>;
322 cache-level = <2>;
325 cluster3_l2: l2-cache3 {
327 cache-size = <0x100000>;
328 cache-line-size = <64>;
329 cache-sets = <1024>;
330 cache-level = <2>;
333 cluster4_l2: l2-cache4 {
335 cache-size = <0x100000>;
336 cache-line-size = <64>;
337 cache-sets = <1024>;
338 cache-level = <2>;
341 cluster5_l2: l2-cache5 {
343 cache-size = <0x100000>;
344 cache-line-size = <64>;
345 cache-sets = <1024>;
346 cache-level = <2>;
349 cluster6_l2: l2-cache6 {
351 cache-size = <0x100000>;
352 cache-line-size = <64>;
353 cache-sets = <1024>;
354 cache-level = <2>;
357 cluster7_l2: l2-cache7 {
359 cache-size = <0x100000>;
360 cache-line-size = <64>;
361 cache-sets = <1024>;
362 cache-level = <2>;
365 cpu_pw15: cpu-pw15 {
366 compatible = "arm,idle-state";
367 idle-state-name = "PW15";
368 arm,psci-suspend-param = <0x0>;
369 entry-latency-us = <2000>;
370 exit-latency-us = <2000>;
371 min-residency-us = <6000>;
375 gic: interrupt-controller@6000000 {
376 compatible = "arm,gic-v3";
383 #interrupt-cells = <3>;
384 #address-cells = <2>;
385 #size-cells = <2>;
387 interrupt-controller;
390 its: gic-its@6020000 {
391 compatible = "arm,gic-v3-its";
392 msi-controller;
398 compatible = "arm,armv8-timer";
406 compatible = "arm,cortex-a72-pmu";
411 compatible = "arm,psci-0.2";
416 // DRAM space - 1, size : 2 GB DRAM
421 ddr1: memory-controller@1080000 {
422 compatible = "fsl,qoriq-memory-controller";
425 little-endian;
428 ddr2: memory-controller@1090000 {
429 compatible = "fsl,qoriq-memory-controller";
432 little-endian;
435 // One clock unit-sysclk node which bootloader require during DT fix-up
437 compatible = "fixed-clock";
438 #clock-cells = <0>;
439 clock-frequency = <100000000>; // fixed up by bootloader
440 clock-output-names = "sysclk";
443 thermal-zones {
444 cluster6-7 {
445 polling-delay-passive = <1000>;
446 polling-delay = <5000>;
447 thermal-sensors = <&tmu 0>;
450 cluster6_7_alert: cluster6-7-alert {
456 cluster6_7_crit: cluster6-7-crit {
463 cooling-maps {
466 cooling-device =
487 ddr-cluster5 {
488 polling-delay-passive = <1000>;
489 polling-delay = <5000>;
490 thermal-sensors = <&tmu 1>;
493 ddr-cluster5-alert {
499 ddr-cluster5-crit {
508 polling-delay-passive = <1000>;
509 polling-delay = <5000>;
510 thermal-sensors = <&tmu 2>;
513 wriop-alert {
519 wriop-crit {
527 dce-qbman-hsio2 {
528 polling-delay-passive = <1000>;
529 polling-delay = <5000>;
530 thermal-sensors = <&tmu 3>;
533 dce-qbman-alert {
539 dce-qbman-crit {
547 ccn-dpaa-tbu {
548 polling-delay-passive = <1000>;
549 polling-delay = <5000>;
550 thermal-sensors = <&tmu 4>;
553 ccn-dpaa-alert {
559 ccn-dpaa-crit {
567 cluster4-hsio3 {
568 polling-delay-passive = <1000>;
569 polling-delay = <5000>;
570 thermal-sensors = <&tmu 5>;
573 clust4-hsio3-alert {
579 clust4-hsio3-crit {
587 cluster2-3 {
588 polling-delay-passive = <1000>;
589 polling-delay = <5000>;
590 thermal-sensors = <&tmu 6>;
593 cluster2-3-alert {
599 cluster2-3-crit {
609 compatible = "simple-bus";
610 #address-cells = <2>;
611 #size-cells = <2>;
613 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
616 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
617 fsl,sec-era = <10>;
618 #address-cells = <1>;
619 #size-cells = <1>;
623 dma-coherent;
627 compatible = "fsl,sec-v5.0-job-ring",
628 "fsl,sec-v4.0-job-ring";
634 compatible = "fsl,sec-v5.0-job-ring",
635 "fsl,sec-v4.0-job-ring";
641 compatible = "fsl,sec-v5.0-job-ring",
642 "fsl,sec-v4.0-job-ring";
648 compatible = "fsl,sec-v5.0-job-ring",
649 "fsl,sec-v4.0-job-ring";
655 clockgen: clock-controller@1300000 {
656 compatible = "fsl,lx2160a-clockgen";
658 #clock-cells = <2>;
663 compatible = "fsl,lx2160a-dcfg", "syscon";
665 little-endian;
669 compatible = "fsl,lx2160a-isc", "syscon";
671 little-endian;
672 #address-cells = <1>;
673 #size-cells = <1>;
676 extirq: interrupt-controller@14 {
677 compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq";
678 #interrupt-cells = <2>;
679 #address-cells = <0>;
680 interrupt-controller;
682 interrupt-map =
695 interrupt-map-mask = <0xffffffff 0x0>;
700 compatible = "fsl,qoriq-tmu";
703 fsl,tmu-range = <0x800000e6 0x8001017d>;
704 fsl,tmu-calibration =
709 little-endian;
710 #thermal-sensor-cells = <1>;
714 compatible = "fsl,vf610-i2c";
715 #address-cells = <1>;
716 #size-cells = <0>;
719 clock-names = "i2c";
722 scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
727 compatible = "fsl,vf610-i2c";
728 #address-cells = <1>;
729 #size-cells = <0>;
732 clock-names = "i2c";
739 compatible = "fsl,vf610-i2c";
740 #address-cells = <1>;
741 #size-cells = <0>;
744 clock-names = "i2c";
751 compatible = "fsl,vf610-i2c";
752 #address-cells = <1>;
753 #size-cells = <0>;
756 clock-names = "i2c";
763 compatible = "fsl,vf610-i2c";
764 #address-cells = <1>;
765 #size-cells = <0>;
768 clock-names = "i2c";
771 scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
776 compatible = "fsl,vf610-i2c";
777 #address-cells = <1>;
778 #size-cells = <0>;
781 clock-names = "i2c";
788 compatible = "fsl,vf610-i2c";
789 #address-cells = <1>;
790 #size-cells = <0>;
793 clock-names = "i2c";
800 compatible = "fsl,vf610-i2c";
801 #address-cells = <1>;
802 #size-cells = <0>;
805 clock-names = "i2c";
812 compatible = "nxp,lx2160a-fspi";
813 #address-cells = <1>;
814 #size-cells = <0>;
817 reg-names = "fspi_base", "fspi_mmap";
823 clock-names = "fspi_en", "fspi";
828 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
829 #address-cells = <1>;
830 #size-cells = <0>;
835 clock-names = "dspi";
836 spi-num-chipselects = <5>;
837 bus-num = <0>;
842 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
843 #address-cells = <1>;
844 #size-cells = <0>;
849 clock-names = "dspi";
850 spi-num-chipselects = <5>;
851 bus-num = <1>;
856 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
857 #address-cells = <1>;
858 #size-cells = <0>;
863 clock-names = "dspi";
864 spi-num-chipselects = <5>;
865 bus-num = <2>;
875 dma-coherent;
876 voltage-ranges = <1800 1800 3300 3300>;
877 sdhci,auto-cmd12;
878 little-endian;
879 bus-width = <4>;
889 dma-coherent;
890 voltage-ranges = <1800 1800 3300 3300>;
891 sdhci,auto-cmd12;
892 broken-cd;
893 little-endian;
894 bus-width = <4>;
899 compatible = "fsl,lx2160ar1-flexcan";
905 clock-names = "ipg", "per";
906 fsl,clk-source = <0>;
911 compatible = "fsl,lx2160ar1-flexcan";
917 clock-names = "ipg", "per";
918 fsl,clk-source = <0>;
923 compatible = "arm,sbsa-uart","arm,pl011";
926 current-speed = <115200>;
931 compatible = "arm,sbsa-uart","arm,pl011";
934 current-speed = <115200>;
939 compatible = "arm,sbsa-uart","arm,pl011";
942 current-speed = <115200>;
947 compatible = "arm,sbsa-uart","arm,pl011";
950 current-speed = <115200>;
955 compatible = "fsl,qoriq-gpio";
958 gpio-controller;
959 little-endian;
960 #gpio-cells = <2>;
961 interrupt-controller;
962 #interrupt-cells = <2>;
966 compatible = "fsl,qoriq-gpio";
969 gpio-controller;
970 little-endian;
971 #gpio-cells = <2>;
972 interrupt-controller;
973 #interrupt-cells = <2>;
977 compatible = "fsl,qoriq-gpio";
980 gpio-controller;
981 little-endian;
982 #gpio-cells = <2>;
983 interrupt-controller;
984 #interrupt-cells = <2>;
988 compatible = "fsl,qoriq-gpio";
991 gpio-controller;
992 little-endian;
993 #gpio-cells = <2>;
994 interrupt-controller;
995 #interrupt-cells = <2>;
999 compatible = "arm,sbsa-gwdt";
1003 timeout-sec = <30>;
1006 rcpm: power-controller@1e34040 {
1007 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+";
1009 #fsl,rcpm-wakeup-cells = <7>;
1010 little-endian;
1014 compatible = "fsl,lx2160a-ftm-alarm";
1016 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1025 snps,quirk-frame-length-adjustment = <0x20>;
1027 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1036 snps,quirk-frame-length-adjustment = <0x20>;
1038 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1043 compatible = "fsl,lx2160a-ahci";
1046 reg-names = "ahci", "sata-ecc";
1050 dma-coherent;
1055 compatible = "fsl,lx2160a-ahci";
1058 reg-names = "ahci", "sata-ecc";
1062 dma-coherent;
1067 compatible = "fsl,lx2160a-ahci";
1070 reg-names = "ahci", "sata-ecc";
1074 dma-coherent;
1079 compatible = "fsl,lx2160a-ahci";
1082 reg-names = "ahci", "sata-ecc";
1086 dma-coherent;
1091 compatible = "fsl,lx2160a-pcie";
1094 reg-names = "csr_axi_slave", "config_axi_slave";
1098 interrupt-names = "aer", "pme", "intr";
1099 #address-cells = <3>;
1100 #size-cells = <2>;
1102 dma-coherent;
1103 apio-wins = <8>;
1104 ppio-wins = <8>;
1105 bus-range = <0x0 0xff>;
1106 … ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1107 msi-parent = <&its>;
1108 #interrupt-cells = <1>;
1109 interrupt-map-mask = <0 0 0 7>;
1110 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1114 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1119 compatible = "fsl,lx2160a-pcie";
1122 reg-names = "csr_axi_slave", "config_axi_slave";
1126 interrupt-names = "aer", "pme", "intr";
1127 #address-cells = <3>;
1128 #size-cells = <2>;
1130 dma-coherent;
1131 apio-wins = <8>;
1132 ppio-wins = <8>;
1133 bus-range = <0x0 0xff>;
1134 … ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1135 msi-parent = <&its>;
1136 #interrupt-cells = <1>;
1137 interrupt-map-mask = <0 0 0 7>;
1138 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1142 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1147 compatible = "fsl,lx2160a-pcie";
1150 reg-names = "csr_axi_slave", "config_axi_slave";
1154 interrupt-names = "aer", "pme", "intr";
1155 #address-cells = <3>;
1156 #size-cells = <2>;
1158 dma-coherent;
1159 apio-wins = <256>;
1160 ppio-wins = <24>;
1161 bus-range = <0x0 0xff>;
1162 … ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1163 msi-parent = <&its>;
1164 #interrupt-cells = <1>;
1165 interrupt-map-mask = <0 0 0 7>;
1166 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1170 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1175 compatible = "fsl,lx2160a-pcie";
1178 reg-names = "csr_axi_slave", "config_axi_slave";
1182 interrupt-names = "aer", "pme", "intr";
1183 #address-cells = <3>;
1184 #size-cells = <2>;
1186 dma-coherent;
1187 apio-wins = <8>;
1188 ppio-wins = <8>;
1189 bus-range = <0x0 0xff>;
1190 … ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1191 msi-parent = <&its>;
1192 #interrupt-cells = <1>;
1193 interrupt-map-mask = <0 0 0 7>;
1194 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1198 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1203 compatible = "fsl,lx2160a-pcie";
1206 reg-names = "csr_axi_slave", "config_axi_slave";
1210 interrupt-names = "aer", "pme", "intr";
1211 #address-cells = <3>;
1212 #size-cells = <2>;
1214 dma-coherent;
1215 apio-wins = <256>;
1216 ppio-wins = <24>;
1217 bus-range = <0x0 0xff>;
1218 … ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1219 msi-parent = <&its>;
1220 #interrupt-cells = <1>;
1221 interrupt-map-mask = <0 0 0 7>;
1222 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1226 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1231 compatible = "fsl,lx2160a-pcie";
1234 reg-names = "csr_axi_slave", "config_axi_slave";
1238 interrupt-names = "aer", "pme", "intr";
1239 #address-cells = <3>;
1240 #size-cells = <2>;
1242 dma-coherent;
1243 apio-wins = <8>;
1244 ppio-wins = <8>;
1245 bus-range = <0x0 0xff>;
1246 … ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1247 msi-parent = <&its>;
1248 #interrupt-cells = <1>;
1249 interrupt-map-mask = <0 0 0 7>;
1250 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1254 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1259 compatible = "arm,mmu-500";
1261 #iommu-cells = <1>;
1262 #global-interrupts = <14>;
1265 // combined secure
1267 // global non-secure fault
1269 // combined non-secure
1271 // performance counter interrupts 0-9
1347 dma-coherent;
1351 compatible = "fsl,dpaa2-console";
1355 ptp-timer@8b95000 {
1356 compatible = "fsl,dpaa2-ptp";
1360 little-endian;
1361 fsl,extts-fifo;
1364 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
1366 compatible = "fsl,fman-memac-mdio";
1369 #address-cells = <1>;
1370 #size-cells = <0>;
1371 little-endian;
1376 compatible = "fsl,fman-memac-mdio";
1379 little-endian;
1380 #address-cells = <1>;
1381 #size-cells = <0>;
1386 compatible = "fsl,fman-memac-mdio";
1388 little-endian;
1389 #address-cells = <1>;
1390 #size-cells = <0>;
1393 pcs1: ethernet-phy@0 {
1399 compatible = "fsl,fman-memac-mdio";
1401 little-endian;
1402 #address-cells = <1>;
1403 #size-cells = <0>;
1406 pcs2: ethernet-phy@0 {
1412 compatible = "fsl,fman-memac-mdio";
1414 little-endian;
1415 #address-cells = <1>;
1416 #size-cells = <0>;
1419 pcs3: ethernet-phy@0 {
1425 compatible = "fsl,fman-memac-mdio";
1427 little-endian;
1428 #address-cells = <1>;
1429 #size-cells = <0>;
1432 pcs4: ethernet-phy@0 {
1438 compatible = "fsl,fman-memac-mdio";
1440 little-endian;
1441 #address-cells = <1>;
1442 #size-cells = <0>;
1445 pcs5: ethernet-phy@0 {
1451 compatible = "fsl,fman-memac-mdio";
1453 little-endian;
1454 #address-cells = <1>;
1455 #size-cells = <0>;
1458 pcs6: ethernet-phy@0 {
1464 compatible = "fsl,fman-memac-mdio";
1466 little-endian;
1467 #address-cells = <1>;
1468 #size-cells = <0>;
1471 pcs7: ethernet-phy@0 {
1477 compatible = "fsl,fman-memac-mdio";
1479 little-endian;
1480 #address-cells = <1>;
1481 #size-cells = <0>;
1484 pcs8: ethernet-phy@0 {
1490 compatible = "fsl,fman-memac-mdio";
1492 little-endian;
1493 #address-cells = <1>;
1494 #size-cells = <0>;
1497 pcs9: ethernet-phy@0 {
1503 compatible = "fsl,fman-memac-mdio";
1505 little-endian;
1506 #address-cells = <1>;
1507 #size-cells = <0>;
1510 pcs10: ethernet-phy@0 {
1516 compatible = "fsl,fman-memac-mdio";
1518 little-endian;
1519 #address-cells = <1>;
1520 #size-cells = <0>;
1523 pcs11: ethernet-phy@0 {
1529 compatible = "fsl,fman-memac-mdio";
1531 little-endian;
1532 #address-cells = <1>;
1533 #size-cells = <0>;
1536 pcs12: ethernet-phy@0 {
1542 compatible = "fsl,fman-memac-mdio";
1544 little-endian;
1545 #address-cells = <1>;
1546 #size-cells = <0>;
1549 pcs13: ethernet-phy@0 {
1555 compatible = "fsl,fman-memac-mdio";
1557 little-endian;
1558 #address-cells = <1>;
1559 #size-cells = <0>;
1562 pcs14: ethernet-phy@0 {
1568 compatible = "fsl,fman-memac-mdio";
1570 little-endian;
1571 #address-cells = <1>;
1572 #size-cells = <0>;
1575 pcs15: ethernet-phy@0 {
1581 compatible = "fsl,fman-memac-mdio";
1583 little-endian;
1584 #address-cells = <1>;
1585 #size-cells = <0>;
1588 pcs16: ethernet-phy@0 {
1594 compatible = "fsl,fman-memac-mdio";
1596 little-endian;
1597 #address-cells = <1>;
1598 #size-cells = <0>;
1601 pcs17: ethernet-phy@0 {
1607 compatible = "fsl,fman-memac-mdio";
1609 little-endian;
1610 #address-cells = <1>;
1611 #size-cells = <0>;
1614 pcs18: ethernet-phy@0 {
1619 fsl_mc: fsl-mc@80c000000 {
1620 compatible = "fsl,qoriq-mc";
1623 msi-parent = <&its>;
1624 /* iommu-map property is fixed up by u-boot */
1625 iommu-map = <0 &smmu 0 0>;
1626 dma-coherent;
1627 #address-cells = <3>;
1628 #size-cells = <1>;
1631 * Region type 0x0 - MC portals
1632 * Region type 0x1 - QBMAN portals
1641 #address-cells = <1>;
1642 #size-cells = <0>;
1645 compatible = "fsl,qoriq-mc-dpmac";
1647 pcs-handle = <&pcs1>;
1651 compatible = "fsl,qoriq-mc-dpmac";
1653 pcs-handle = <&pcs2>;
1657 compatible = "fsl,qoriq-mc-dpmac";
1659 pcs-handle = <&pcs3>;
1663 compatible = "fsl,qoriq-mc-dpmac";
1665 pcs-handle = <&pcs4>;
1669 compatible = "fsl,qoriq-mc-dpmac";
1671 pcs-handle = <&pcs5>;
1675 compatible = "fsl,qoriq-mc-dpmac";
1677 pcs-handle = <&pcs6>;
1681 compatible = "fsl,qoriq-mc-dpmac";
1683 pcs-handle = <&pcs7>;
1687 compatible = "fsl,qoriq-mc-dpmac";
1689 pcs-handle = <&pcs8>;
1693 compatible = "fsl,qoriq-mc-dpmac";
1695 pcs-handle = <&pcs9>;
1699 compatible = "fsl,qoriq-mc-dpmac";
1701 pcs-handle = <&pcs10>;
1705 compatible = "fsl,qoriq-mc-dpmac";
1707 pcs-handle = <&pcs11>;
1711 compatible = "fsl,qoriq-mc-dpmac";
1713 pcs-handle = <&pcs12>;
1717 compatible = "fsl,qoriq-mc-dpmac";
1719 pcs-handle = <&pcs13>;
1723 compatible = "fsl,qoriq-mc-dpmac";
1725 pcs-handle = <&pcs14>;
1729 compatible = "fsl,qoriq-mc-dpmac";
1731 pcs-handle = <&pcs15>;
1735 compatible = "fsl,qoriq-mc-dpmac";
1737 pcs-handle = <&pcs16>;
1741 compatible = "fsl,qoriq-mc-dpmac";
1743 pcs-handle = <&pcs17>;
1747 compatible = "fsl,qoriq-mc-dpmac";
1749 pcs-handle = <&pcs18>;